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A '''control store''' is the part of a [[Central processing unit|CPU's]] [[control unit]] that stores the CPU's [[microprogram]]. It is usually accessed by a [[microsequencer]]. Early types ofA control store tookimplementation thewhose formcontents ofare diode-arraysunalterable thatis were accessed via address decoders, but were later implementedknown as writable microcode that was stored in a form of [[read Read-only memory|Read Only Memory]] called(ROM) aor writableRead controlOnly store.Storage The(ROS); outputsone generallywhose hadcontents toare goalterable throughis aknown register to preventas a race condition from occurring. The register was clocked by the clock signal of the system itWritable wasControl runningStore on(WCS).
<!-- WCS is not a form of ROM -->
==Implementation==
===Early use===
Early control stores were implemented as a diode-array accessed via address decoders, a form of read-only memory. This tradition dates back to the ''program timing matrix'' on the [[MIT Whirlwind]], first described in 1947. Modern [[VLSI]] processors instead use matrices of [[field-effect transistor]]s to build the [[Read-only memory|ROM]] and/or [[programmable logic array|PLA]] structures used to control the processor as well as its internal sequencer in a [[microcode]]d implementation. [[IBM System/360]] used a variety of techniques: [[CCROS]] (Card Capacitor Read-Only Storage) on the [[IBM System/360 Model 30|Model 30]], [[Transformer_read-only_storage|TROS]] (Transformer Read-Only Storage) on the [[IBM System/360 Model 40|Model 40]], and [[BCROS]] (Balanced Capacitor Read-Only Storage) on theModels [[IBM System/360 Model 50|50]], [[IBM System/360 Model 5065|65]] and [[IBM System/360 Model 67|67]].
===Writable stores===
Some computers wereare built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode wasis stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''Writable Instruction Set Computer'' or ''WISC''.<ref> [{{cite journal | url = http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf "| title = Writable instruction set, stack oriented computers: The WISC Concept "] article| byjournal = The Journal of Forth Application and Research | volume = 5 | issue = 1 | pages=49–71 | first = Philip | last = Koopman Jr. | date = 1987 }}</ref> Many of these machines were experimental laboratory prototypes, such as the WISC CPU/16<ref> [{{cite book | chapter-url = http:// wwwusers.ece.cmu.edu/~koopman/stack_computers/sec4_2.html "| chapter = Architecture of the WISC CPU/16 "] by| Philtitle = Stack Computers: the new wave | url = https://users.ece.cmu.edu/~koopman/stack_computers/index.html | first = Philip | last = Koopman Jr. | date = 1989 }}</ref> and the RTX 32P.<ref> [{{cite book | chapter-url = http:// wwwusers.ece.cmu.edu/~koopman/stack_computers/sec5_3.html "| chapter = Architecture of the RTX 32P "] by| title = Stack Computers: the new wave | url = https://users.ece.cmu.edu/~koopman/stack_computers/index.html | first = Philip | last = Koopman Jr. | date = 1989 }}</ref> ▼
The original [[IBM System/360|System/360]] models of [[IBM mainframe]] hadhave read-only control store, but later System/360, [[IBM System/370|System/370]] and successor models loadedload part or all of their microprograms from floppy disks or other [[Direct access storage device|DASD ]] into a writable control store consisting of ultra-high speed [[random-access memory|random-access]] [[ read-writeread–write memory]]. The System/370 architecture includedincludes a facility called '''Initial-Microprogram Load''' ('''IML''' or '''IMPL''')<ref>{{cite manual ▼▲Some computers were built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode was stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''Writable Instruction Set Computer'' or ''WISC''.<ref>[http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf "Writable instruction set, stack oriented computers: The WISC Concept"] article by Philip Koopman Jr. 1987</ref> Many of these machines were experimental laboratory prototypes, such as the WISC CPU/16<ref>[http://www.ece.cmu.edu/~koopman/stack_computers/sec4_2.html "Architecture of the WISC CPU/16"] by Phil Koopman 1989</ref> and the RTX 32P.<ref>[http://www.ece.cmu.edu/~koopman/stack_computers/sec5_3.html "Architecture of the RTX 32P"] by Philip Koopman 1989</ref>
▲The original [[IBM System/360|System/360]] models of [[IBM mainframe]] had read-only control store, but later System/360, [[IBM System/370|System/370]] and successor models loaded part or all of their microprograms from floppy disks or other DASD into a writable control store consisting of ultra-high speed [[random-access memory|random-access]] [[read-write memory]]. The System/370 architecture included a facility called '''Initial-Microprogram Load''' ('''IML''' or '''IMPL''')<ref>{{cite manual
| author = IBM
| title = IBM System/370 Principles of Operation
| pages = 98, 245
|mode=cs2
}}</ref> that couldcan be invoked from the console, as part of '''[[Power-on reset#Power-on reset on IBM mainframes|Power On Reset]]''' ('''POR''') or from another processor in a [[Tightly coupled system|tightly coupled]] [[multiprocessor]] complex. This permitted IBM to easily repair microprogramming defects in the field. Even when the majority of the control store is stored in ROM, computer vendors would often sell writable control store as an option, allowing the customers to customize the machine's microprogram. Other vendors, e.g., IBM, use the WCS to run microcode for emulator features<ref>{{cite manual
| author = IBM
| title = IBM System/360 Model 85 Functional Characteristics
| id = A22-6916-1
| url = http://www.bitsavers.org/pdf/ibm/360/funcCharfunctional_characteristics/A22-6916-1_360-85_funcChar_Jun68.pdf
| version = SECOND EDITION
| date = June 1968
}}</ref>
Other commercial machines that useduse writable microcode include the [[Burroughs Small Systems]] (1970s and 1980s), the Xerox processors in their [[Lisp machine]]s and [[Xerox Star]] workstations, the [[Digital Equipment Corporation|DEC]] [[VAX]] 8800 ("Nautilus") family, and the [[Symbolics]] L- and G-machines (1980s). Some DEC [[PDP-10]] machines storedstore their microcode in SRAM chips (about 80 bits wide x 2 Kwords), which wasis typically loaded on power-on through some other front-end CPU.<ref>{{Cite newsgroup|url=http://pdp10.nocrew.org/cpu/kl10-ucode.txt|title=Re: What was the size of Microcode in various machines|first=Eric|last=Smith|newsgroup=comp.arch|date=September 3, 2002}}</ref> Many more machines offeredoffer user-programmable writable control stores as an option (including the [[HP 2100]], DEC [[PDP-11|PDP-11/60]] and [[Varian Data Machines]] V-70 series [[minicomputer]]s).
The [[Mentec PDP-11#M11|Mentec M11]] and [[Mentec PDP-11#M1|Mentec M1]] storedstore its microcode in SRAM chips, loaded on power-on through another CPU.
The [[Data General Eclipse MV/8000]] ("Eagle") hadhas a SRAM writable control store, loaded on power-on through another CPU.<ref>{{cite web|author=Mark Smotherman|title=CPSC 330 / The Soul of a New Machine|url=http://www.cs.clemson.edu/~mark/330/eagle.html|quote=4096 x 75-bit SRAM writeable control store: 74-bit microinstruction with 1 parity bit (18 fields)}}</ref>
WCS offeredoffers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs could provide. User-programmable WCS allowedallow the user to optimize the machine for specific purposes. However, it also had the disadvantage of making it harder to debug programs, and making it possible for malicious users to negatively affect the system and data.<ref>{{cite journal |last=McDowell |first=Charlie |date=1982 |title=Protection at the micromachine level |url=https://dl.acm.org/doi/pdf/10.1145/859520.859521 |journal=ACM SIGARCH Computer Architecture News |volume=10 |issue=1 |pages=5 |doi=10.1145/859520.859521 |access-date=2023-11-25 |quote=It is not unusual to find microprograms that are greater than 50K bytes in size. This increase in size, and the expansion of microprograming beyond the traditional bounds of machine instruction emulation, have increased the possibility of both malicious and faulty microprograms, particularly the later.}}</ref>
Some CPU designs compile the instruction set to a writable [[RAM]] or [[Flash memory|FLASH]] inside the CPU (such as the [[Rekursiv]] processor and the [[Imsys]] [[Cjip]]),<ref>{{cite web|url=http://cpushack.com/CPU/cpu7.html |title=Great Microprocessors of the Past and Present (V 13.4.0) |publisher=Cpushack.com |access-date= |accessdate=2010-04-26}}</ref> or an FPGA ([[reconfigurable computing]]).
Several Intel CPUs in the [[x86]] architecture family have writable microcode,<ref>
[{{cite book | url = http://www.intel.com/Assets/PDF/manual/253668.pdf "| title = Intel(R) 64 and IA-32 Architectures Software Developer’sDeveloper's Manual", Volume 3A: System Programming Guide, Part 1], | at = chapter 9.11: "Microcode update facilities", | date = December 2009}}</ref> starting with the [[Pentium Pro]] in 1995.<ref name="Stiller_1996"/><ref name="Gwennap_1997">{{cite magazine |title=P6 Microcode Can Be Patched - Intel Discloses Details of Download Mechanism for Fixing CPU Bugs |author-last=Gwennap |author-first=Linley |date=1997-09-15 |magazine=[[Microprocessor Report]] |publisher=[[MicroDesign Resources]] |url=https://www.ele.uva.es/~jesman/BigSeti/ftp/Cajon_Desastre/MPR/111204.pdf |access-date=2017-06-26 |url-status=live |archive-url=https://web.archive.org/web/20220519184528/https://www.ele.uva.es/~jesman/BigSeti/ftp/Cajon_Desastre/MPR/111204.pdf |archive-date=2022-05-19}} (2 pages)</ref>
</ref> starting with the [[Pentium Pro]] in 1995.<ref>{{cite magazine |last=Gwennap |first=Linley |date=1997-09-15 |title=P6 Microcode can be Patched |url=https://www.ele.uva.es/~jesman/BigSeti/ftp/Cajon_Desastre/MPR/111204.pdf |magazine=[[Microprocessor Report]] |access-date=2017-06-26 }}</ref>
This has allowed bugs in the [[Intel Core 2]] microcode and Intel [[Xeon]] microcode to be fixed in software, rather than requiring the entire chip to be replaced.
Such fixes can be installed by Linux,<ref>[{{cite web|url=http://urbanmyth.org/microcode/ "|title=Intel Microcode Update Utility for Linux"]|archive-url=https://web.archive.org/web/20120226174302/http://urbanmyth.org/microcode/|archive-date=2012-02-26}}</ref> [[FreeBSD]],<ref>{{cite webmailing list |url=httphttps://wwwlists.freebsd.org/cgipipermail/cvsweb.cgifreebsd-hackers/ports/sysutils/devcpu2018-March/052359.html |title=ports/sysutils/devcpu/New microcode updating tool for FreeBSD |publisherauthor=Freebsd.orgStefan Blachmann |mailing-list=freebsd-hackers |date=20082018-0903-2302 |accessdateaccess-date=20102019-0407-2609}}</ref> Microsoft Windows,<ref>[{{cite web| url = http://support.microsoft.com/kb/936357| title = "A microcode reliability update is available that improves the reliability of systems that use Intel processors"]| website = Microsoft Support| date = June 22, 2007| archive-url = https://web.archive.org/web/20070628171253/http://support.microsoft.com/kb/936357| archive-date = 2007-06-28}}</ref> or the motherboard BIOS.<ref>[http{{cite web| url = https://www.intel.com/supportcontent/motherboardswww/serverus/sben/cssupport/articles/000007784/server-021619products.htmhtml | title = "BIOS Update required when Missing Microcode message is seen during POST" | website = [[Intel]] | access-date = 2022-01-13}}</ref>
===Timing, latching and avoiding a race condition===
The control store usually has a register on its outputs. The outputs that go back into the sequencer to determine the next address have to go through some sort of register to prevent the creation of a [[race condition]].<ref>
Don Lancaster.
[https://www.tinaja.com/ebooks/tvtcb.pdf "TV Typewriter Cookbook"].
p. 62.
([[TV Typewriter]])
</ref>
In most designs all of the other bits also go through a register. This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle. This register is known as a pipeline register. Very often the execution of the next microinstruction is dependent on the result of the current microinstruction, which will not be stable until the end of the current microcycle. It can be seen that either way, all of the outputs of the control store go into one big register. Historically it used to be possible to buy EPROMs with these register bits on the same chip.
The [[clock signal]] determining the [[clock rate]], which is the cycle time of the system, primarily clocks this register.
== References ==
<ref name="Stiller_1996">{{cite magazine |title=Prozessorgeflüster |series=Trends & News / aktuell - Prozessoren |language=de |author-first1=Andreas |author-last1=Stiller |author-first2=Matthias R. |author-last2=Paul<!-- info contributor on processor internals --> |date=1996-05-12 |volume=1996 |issue=6 |magazine=[[c't – magazin für computertechnik]] |publisher=[[Verlag Heinz Heise GmbH & Co KG]] |issn=0724-8679 |page=20 |url=https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |access-date=2017-08-28 |url-status=live |archive-url=https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |archive-date=2017-08-28}}</ref>
}}
==Further reading==
* {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=1 |url=http://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_1_Sep47.pdf |access-date=2021-11-12 |url-status=live |archive-url=https://web.archive.org/web/20210815014917/http://bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_1_Sep47.pdf |archive-date=2021-08-15}} (132 pages)
* {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=2 |url=http://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_2_Sep47.pdf |access-date=2021-11-12 |url-status=live |archive-url=https://web.archive.org/web/20210815015419/http://bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_2_Sep47.pdf |archive-date=2021-08-15}} (79 pages)
* {{cite journal | author-last=Smith | author-first=Richard E. | title=A Historical Overview of Computer Architecture | journal= [[Annals of the History of Computing ]] | publisher=[[IEEE]] year|date= October–December 1988 | volume=10 | issue=4 | pages=277–303 | urldoi= http://doi.ieeecomputersociety.org/10.1109/MAHC.1988.10039 | s2cid=16405547 |url=http://doi = .ieeecomputersociety.org/10.1109/MAHC.1988.10039 | accessdateaccess-date=2006-06-21}} ▼{{wikibooks
|1= Microprocessor Design
|2= Microcode
}}
<!-- The link is dead and the paper can't be found on the server.
* {{Cite paper | author=Everett, R.R., and Swain, F.E. | title=Whirlwind I Computer Block Diagrams | publisher=MIT Servomechanisms Laboratory | year=1947 | version=Report R-127 | url=http://www.cs.stthomas.edu/faculty/resmith/papers/WhirlwindR-127.pdf |format=PDF| accessdate=2006-06-21 }} -->
▲* {{cite journal | last=Smith | first=Richard E. | title=A Historical Overview of Computer Architecture | journal=Annals of the History of Computing | year=1988 | volume=10 | issue=4 | pages=277–303 | url=http://doi.ieeecomputersociety.org/10.1109/MAHC.1988.10039 | doi = 10.1109/MAHC.1988.10039 | accessdate=2006-06-21}}
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