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A '''control store''' is the part of a [[Central processing unit|CPU's]] [[control unit]] that stores the CPU's [[microprogram]]. It is usually accessed by a [[microsequencer]].
<!-- WCS is not a form of ROM -->
==Implementation==
===Early use===
Early control stores were implemented as a diode-array accessed via address decoders, a form of read-only memory. This tradition dates back to the ''program timing matrix'' on the [[MIT Whirlwind]], first described in 1947. Modern [[VLSI]] processors instead use matrices of [[field-effect transistor]]s to build the [[Read-only memory|ROM]] and/or [[programmable logic array|PLA]] structures used to control the processor as well as its internal sequencer in a [[microcode]]d implementation. [[IBM System/360]] used a variety of techniques:
===Writable stores===
Some computers
The original [[IBM System/360|System/360]] models
▲Some computers were built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode was stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''Writable Instruction Set Computer'' or ''WISC''.<ref>[http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf "Writable instruction set, stack oriented computers: The WISC Concept"] article by Philip Koopman Jr. 1987</ref> Many of these machines were experimental laboratory prototypes, such as the WISC CPU/16<ref>[http://www.ece.cmu.edu/~koopman/stack_computers/sec4_2.html "Architecture of the WISC CPU/16"] by Phil Koopman 1989</ref> and the RTX 32P.<ref>[http://www.ece.cmu.edu/~koopman/stack_computers/sec5_3.html "Architecture of the RTX 32P"] by Philip Koopman 1989</ref>
▲The original [[IBM System/360|System/360]] models of [[IBM mainframe]] had read-only control store, but later System/360, [[IBM System/370|System/370]] and successor models loaded part or all of their microprograms from floppy disks or other DASD into a writable control store consisting of ultra-high speed [[random-access memory|random-access]] [[read-write memory]]. The System/370 architecture included a facility called '''Initial-Microprogram Load''' ('''IML''' or '''IMPL''')<ref>{{cite manual
| author = IBM
| title = IBM System/370 Principles of Operation
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| pages = 98, 245
|mode=cs2
}}</ref> that
| author = IBM
| title = IBM System/360 Model 85 Functional Characteristics
| id = A22-6916-1
| url = http://www.bitsavers.org/pdf/ibm/360/
| version = SECOND EDITION
| date = June 1968
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}}</ref>
Other commercial machines that
The [[Mentec PDP-11#M11|Mentec M11]] and [[Mentec PDP-11#M1|Mentec M1]]
The [[Data General Eclipse MV/8000]] ("Eagle")
WCS
Some CPU designs compile the instruction set to a writable [[RAM]] or [[Flash memory|FLASH]] inside the CPU (such as the [[Rekursiv]] processor and the [[Imsys]] [[Cjip]]),<ref>{{cite web|url=http://cpushack.com/CPU/cpu7.html |title=Great Microprocessors of the Past and Present (V 13.4.0) |publisher=Cpushack.com |access-date
Several Intel CPUs in the [[x86]] architecture family have writable microcode,<ref>
This has allowed bugs in the [[Intel Core 2]] microcode and Intel [[Xeon]] microcode to be fixed in software, rather than requiring the entire chip to be replaced.
Such fixes can be installed by Linux,<ref>{{cite web|url=http://urbanmyth.org/microcode/|title=Intel Microcode Update Utility for Linux|archive-url=https://web.archive.org/web/20120226174302/http://urbanmyth.org/microcode/|archive-date=2012-02-26}}</ref> [[FreeBSD]],<ref>{{cite mailing list |url=https://lists.freebsd.org/pipermail/freebsd-hackers/2018-March/052359.html |title=New microcode updating tool for FreeBSD |author=Stefan Blachmann |mailing-list=freebsd-hackers |date=2018-03-02 |
===Timing, latching and avoiding a race condition===
The control store usually has a register on its outputs. The outputs that go back into the sequencer to determine the next address have to go through some sort of register to prevent the creation of a [[race condition]].<ref>
Don Lancaster. [https://www.tinaja.com/ebooks/tvtcb.pdf "TV Typewriter Cookbook"]. p. 62. ([[TV Typewriter]]) </ref> In most designs all of the other bits also go through a register. This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle. This register is known as a pipeline register. Very often the execution of the next microinstruction is dependent on the result of the current microinstruction, which will not be stable until the end of the current microcycle. It can be seen that either way, all of the outputs of the control store go into one big register. Historically it used to be possible to buy EPROMs with these register bits on the same chip. The [[clock signal]] determining the [[clock rate]], which is the cycle time of the system, primarily clocks this register.
== References ==
<ref name="Stiller_1996">{{cite magazine |title=Prozessorgeflüster |series=Trends & News / aktuell - Prozessoren |language=de |author-first1=Andreas |author-last1=Stiller |author-first2=Matthias R. |author-last2=Paul<!-- info contributor on processor internals --> |date=1996-05-12 |volume=1996 |issue=6 |magazine=[[c't – magazin für computertechnik]] |publisher=[[Verlag Heinz Heise GmbH & Co KG]] |issn=0724-8679 |page=20 |url=https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |access-date=2017-08-28 |url-status=live |archive-url=https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |archive-date=2017-08-28}}</ref>
}}
==Further reading==
* {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=1 |url=http://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_1_Sep47.pdf |access-date=2021-11-12 |url-status=live |archive-url=https://web.archive.org/web/20210815014917/http://bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_1_Sep47.pdf |archive-date=2021-08-15}} (132 pages)
* {{Cite book |author-last1=Everett |author-first1=Robert Rivers |author-link1=Robert Everett (computer scientist) |author-last2=Swain |author-first2=F. E. |title=Whirlwind I Computer Block Diagrams |series=[[Project Whirlwind]] (Device 24-X-3) |location=Cambridge, Massachusetts, USA |publisher=[[Servomechanisms Laboratory Massachusetts Institute of Technology]] |date=1947-09-04 |id=Project DIC 6345, Report R-127 |volume=2 |url=http://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_2_Sep47.pdf |access-date=2021-11-12 |url-status=live |archive-url=https://web.archive.org/web/20210815015419/http://bitsavers.org/pdf/mit/whirlwind/R-series/R-127_Whirlwind_I_Computer_Block_Diagrams_Volume_2_Sep47.pdf |archive-date=2021-08-15}} (79 pages)
* {{cite journal |
{{wikibooks
|1= Microprocessor Design
|2= Microcode
}}
▲{{Reflist|30em}}
▲* {{cite journal | last=Smith | first=Richard E. | title=A Historical Overview of Computer Architecture | journal=Annals of the History of Computing | year=1988 | volume=10 | issue=4 | pages=277–303 | url=http://doi.ieeecomputersociety.org/10.1109/MAHC.1988.10039 | doi = 10.1109/MAHC.1988.10039 | accessdate=2006-06-21}}
{{CPU technologies}}
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