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===Writable stores===
 
Some computers were built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode was stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''Writable Instruction Set Computer'' or ''WISC''.<ref>[{{cite journal | url = http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf "| title = Writable instruction set, stack oriented computers: The WISC Concept"] article| byjournal = The Journal of Forth Application and Research | volume = 5 | issue = 1 | pages=49-71 | first = Philip | last = Koopman Jr. | date = 1987}}</ref> Many of these machines were experimental laboratory prototypes, such as the WISC CPU/16<ref>[{{cite book | chapter-url = http://wwwusers.ece.cmu.edu/~koopman/stack_computers/sec4_2.html "| chapter = Architecture of the WISC CPU/16"] by| Philtitle = Stack Computers: the new wave | url = https://users.ece.cmu.edu/~koopman/stack_computers/index.html | first = Philip | last = Koopman Jr. | date = 1989}}</ref> and the RTX 32P.<ref>[{{cite book | chapter-url = http://wwwusers.ece.cmu.edu/~koopman/stack_computers/sec5_3.html "| chapter = Architecture of the RTX 32P"] by| title = Stack Computers: the new wave | url = https://users.ece.cmu.edu/~koopman/stack_computers/index.html | first = Philip | last = Koopman Jr. | date = 1989}}</ref>
 
The original [[IBM System/360|System/360]] models had read-only control store, but later System/360, [[IBM System/370|System/370]] and successor models loaded part or all of their microprograms from floppy disks or other [[Direct access storage device|DASD]] into a writable control store consisting of ultra-high speed [[random-access memory|random-access]] [[read-write memory]]. The System/370 architecture included a facility called '''Initial-Microprogram Load''' ('''IML''' or '''IMPL''')<ref>{{cite manual
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Several Intel CPUs in the [[x86]] architecture family have writable microcode,<ref>
[{{cite book | url = http://www.intel.com/Assets/PDF/manual/253668.pdf "| title = Intel(R) 64 and IA-32 Architectures Software Developer’s Manual", Volume 3A: System Programming Guide, Part 1], | at = chapter 9.11: "Microcode update facilities", | date = December 2009}}</ref> starting with the [[Pentium Pro]] in 1995.<ref>{{cite magazine |last=Gwennap |first=Linley |date=1997-09-15 |title=P6 Microcode can be Patched |url=https://www.ele.uva.es/~jesman/BigSeti/ftp/Cajon_Desastre/MPR/111204.pdf |magazine=[[Microprocessor Report]] |access-date=2017-06-26 }}</ref><ref name="Stiller_1996"/>
</ref> starting with the [[Pentium Pro]] in 1995.<ref>{{cite magazine |last=Gwennap |first=Linley |date=1997-09-15 |title=P6 Microcode can be Patched |url=https://www.ele.uva.es/~jesman/BigSeti/ftp/Cajon_Desastre/MPR/111204.pdf |magazine=[[Microprocessor Report]] |access-date=2017-06-26 }}</ref><ref name="Stiller_1996"/>
This has allowed bugs in the [[Intel Core 2]] microcode and Intel [[Xeon]] microcode to be fixed in software, rather than requiring the entire chip to be replaced.
Such fixes can be installed by Linux,<ref>{{cite web|url=http://urbanmyth.org/microcode/|title=Intel Microcode Update Utility for Linux|archive-url=https://web.archive.org/web/20120226174302/http://urbanmyth.org/microcode/|archive-date=2012-02-26}}</ref> [[FreeBSD]],<ref>{{cite mailing list |url=https://lists.freebsd.org/pipermail/freebsd-hackers/2018-March/052359.html |title=New microcode updating tool for FreeBSD |author=Stefan Blachmann |mailing-list=freebsd-hackers |date=2018-03-02 |access-date=2019-07-09}}</ref> Microsoft Windows,<ref>{{cite web| url = http://support.microsoft.com/kb/936357| title = A microcode reliability update is available that improves the reliability of systems that use Intel processors}}{{dead link}}</ref> or the motherboard BIOS.<ref>{{cite web| url = https://www.intel.com/content/www/us/en/support/articles/000007784/server-products.html | title = BIOS Update required when Missing Microcode message is seen during POST | website = [[Intel]] | access-date = 2022-01-13}}</ref>
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