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Dataflow architecture: Difference between revisions

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{{Short description|Type of low-level computer architecture}}
'''Dataflow architecture''' is a [[computer architecture]] that directly contrasts the traditional [[von Neumann architecture]] or [[control flow architecture]]. Dataflow architectures do not have a [[program counter]], or (at least conceptually) the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions, so that the order of instruction execution is unpredictable: i. e. behavior is nondeterministic.
{{refimproveMore citations needed|date=August 2012}}
'''Dataflow architecture''' is a [[dataflow]]-based [[computer architecture]] that directly contrasts the traditional [[von Neumann architecture]] or [[control flow]] architecture]]. Dataflow architectures do not have ano [[program counter]], orin (at least conceptually)concept: the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions,<ref name=architecture>{{cite journal |last=Veen |first=Arthur H. |date=December 1986 |title=Dataflow Machine Architecture |journal=ACM Computing Surveys |volume=18 |number=4 |pages=365–396 |url=https://www.researchgate.net/publication/220566271 |access-date=5 March 2019 |doi=10.1145/27633.28055 |s2cid=5467025}}</ref> so that the order of instruction execution ismay unpredictable:be i.hard e. behavior isto nondeterministicpredict.
 
Although no commercially successful general-purpose computer hardware has used a dataflow architecture, it has been successfully implemented in specialized hardware such as in [[digital signal processing]], [[network routing]], [[graphics processing]], [[telemetry]], and more recently in data warehousing, and [[artificial intelligence]] (as: polymorphic dataflow<ref>{{Cite news |last=Maxfield |first=Max |date=24 December 2020 |title=Say Hello to Deep Vision's Polymorphic Dataflow Architecture |work=Electronic Engineering Journal |publisher=Techfocus media}}</ref> Convolution Engine,<ref>{{cite web |url=https://kinara.ai/<!-- Prior: https://deepvision.io/ --> |title=Kinara (formerly Deep Vision) |author=<!-- Unstated --> |date=2022 |website=Kinara |access-date=2022-12-11}}</ref> structure-driven,<ref>{{Citationcite web |url=https://hailo.ai/ |title=Hailo |author=<!-- Unstated --> needed|date=March<!-- 2015Undated --> |website=Hailo |access-date=2022-12-11}}</ref> dataflow [[Scheduling (computing)|scheduling]]<ref>{{Cite report |last=Lie |first=Sean |date=29 August 2022 |url=https://www.cerebras.net/blog/cerebras-architecture-deep-dive-first-look-inside-the-hw/sw-co-design-for-deep-learning |title=Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning |website=Cerebras}}</ref>). It is also very relevant in many software architectures today including [[database]] engine designs and [[parallel computing]] frameworks.{{Citation needed|date=March 2015}}
 
Synchronous dataflow architectures tune to match the workload presented by real-time data path applications such as wire speed packet forwarding. Dataflow architectures that are deterministic in nature enable programmers to manage complex tasks such as processor [[Load balancing (computing)|load balancing]], synchronization and accesses to common resources.<ref name="EN-Genius">[http://www.en-genius.net/site/zones/networkZONE/product_reviews/netp_061608{{cite "press release |date=June 18, 2008 |title=HX300 Family of NPUs and Programmable Ethernet Switches to the Fiber Access Market", ''|url=http://www.en-genius.net/site/zones/networkZONE/product_reviews/netp_061608 |website=EN-Genius'', June|url-status=dead 18 2008]|archive-url=https://web.archive.org/web/20110722151409/http://www.en-genius.net/site/zones/networkZONE/product_reviews/netp_061608 |archive-date=2011-07-22}}</ref>
 
Meanwhile, there is a clash of terminology, since the term ''[[dataflow]]'' is used for a subarea of parallel programming: for [[dataflow programming]].
 
== History ==
Hardware architectures for dataflow was a major topic in [[computer architecture]] research in the 1970s and early 1980s. [[Jack Dennis]] of [[Massachusetts Institute of Technology|MIT]] pioneered the field of static dataflow architectures while the Manchester Dataflow Machine<ref name="Manchester-Dataflow">[https://web.archive.org/web/20120730230237/http://cnc.cs.manchester.ac.uk/projects/dataflow.html Manchester Dataflow Research Project, Research Reports: Abstracts, September 1997]</ref> and MIT Tagged Token architecture were major projects in dynamic dataflow.
 
The research, however, never overcame the problems related to:
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* Efficiently broadcasting data tokens in a massively parallel system.
* Efficiently dispatching instruction tokens in a massively parallel system.
* Building [[Contentcontent-addressable_memoryaddressable | CAMmemory]]s (CAM) large enough to hold all of the dependencies of a real program.
Instructions and their data dependencies proved to be too fine-grained to be effectively distributed in a large network. That is, the time for the instructions and tagged results to travel through a large connection network was longer than the time to actually do themany computations.
 
Nonetheless, [[out-of-order execution]] (OOE) has become the dominant computing paradigm since the 1990s. It is a form of restricted dataflow. This paradigm introduced the idea of an ''execution window''. The ''execution window'' follows the sequential order of the von Neumann architecture, however within the window, instructions are allowed to be completed in data dependency order. This is accomplished in CPUs that dynamically tag the data dependencies of the code in the execution window. The logical complexity of dynamically keeping track of the data dependencies, restricts [[out-of-order execution|''OOE'']] [[CPU]]s to a small number of execution units (2-6) and limits the execution window sizes to the range of 32 to 200 instructions, much smaller than envisioned for full dataflow machines.{{cn|date=July 2023}}
 
== Dataflow architecture topics ==
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== See also ==
* [[Dataflow]]
* [[Parallel computing]]
* [[SISAL]]
* [[BMDFM | BMDFM: Binary Modular Dataflow Machine]] (BMDFM)
* [[Systolic array]]
* [[Transport triggered architecture]]
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== References ==
{{reflistReflist}}
 
{{refimprove|date=August 2012}}
{{CPUProcessor technologies}}
 
{{CPU technologies}}
{{Hardware acceleration}}
[[Category:Hardware acceleration]]