@INPROCEEDINGS{chisel:dac2012,

author = {Jonathan Bachrach and Huy Vo and Brian Richards and Yunsup Lee and

Andrew Waterman and Rimas Avizienis and John Wawrzynek and Krste

Asanovic},

title = {Chisel: constructing hardware in a {Scala} embedded language},

booktitle = {The 49th Annual Design Automation Conference (DAC 2012)},

year = {2012},

editor = {Patrick Groeneveld and Donatella Sciuto and Soha Hassoun},

pages = {1216--1225},

address = {San Francisco, {CA}, {USA}},

month = {June},

publisher = {ACM},

bibdate = {2012-06-01},

bibsource = {DBLP, http://dblp.uni-trier.de/db/conf/dac/dac2012.html#BachrachVRLWAWA12},

isbn = {978-1-4503-1199-1},

url = {http://dl.acm.org/citation.cfm?id=2228360}

}

@ARTICLE{patmos:rts2018,

author = {Martin Schoeberl and Wolfgang Puffitsch and Stefan Hepp and Benedikt

Huber and Daniel Prokesch},

title = {Patmos: A Time-predictable Microprocessor},

journal = {Real-Time Systems},

year = {2018},

volume = {54(2)},

pages = {389--423},

month = {Apr},

doi = {10.1007/s11241-018-9300-4},

issn = {1573-1383}

}

@BOOK{Scala,

title = {Programming in Scala, 3rd Edition},

publisher = {Artima Inc},

year = {2016},

author = {Bill Venners and Lex Spoon and Martin Odersky},

owner = {martin},

timestamp = {2017.11.15}

}

@INPROCEEDINGS{lipsi:arcs2018,

author = {Martin Schoeberl},

title = {Lipsi: Probably the Smallest Processor in the World},

booktitle = {Architecture of Computing Systems -- ARCS 2018},

year = {2018},

pages = {18--30},

publisher = {Springer International Publishing},

doi = {10.1007/978-3-319-77610-1_2},

isbn = {978-3-319-77610-1},

url = {https://www.jopdesign.com/doc/lipsi.pdf}

}

@INPROCEEDINGS{leros:arcs2019,

author = {Martin Schoeberl and Petersen, {Morten Borup}},

title = {Leros: The return of the accumulator machine},

booktitle = {Architecture of Computing Systems - ARCS 2019 - 32nd International

Conference, Proceedings},

year = {2019},

editor = {Martin Schoeberl and Thilo Pionteck and Sascha Uhrig and J{\"u}rgen

Brehm and Christian Hochberger},

pages = {115--127},

month = {1},

publisher = {Springer},

day = {1},

doi = {10.1007/978-3-030-18656-2_9},

isbn = {9783030186555},

language = {English}

}

@BOOK{dally:vhdl:2016,

title = {Digital design using VHDL: A systems approach},

publisher = {Cambridge University Press},

year = {2016},

author = {William J. Dally and R. Curtis Harting and Tor M. Aamodt},

pages = {664}

}

@techreport{rocket:techrep,

Author = {Asanović, Krste and Avizienis, Rimas and Bachrach, Jonathan and Beamer, Scott and Biancolin, David and Celio, Christopher and Cook, Henry and Dabbelt, Daniel and Hauser, John and Izraelevitz, Adam and Karandikar, Sagar and Keller, Ben and Kim, Donggyu and Koenig, John and Lee, Yunsup and Love, Eric and Maas, Martin and Magyar, Albert and Mao, Howard and Moreto, Miquel and Ou, Albert and Patterson, David A. and Richards, Brian and Schmidt, Colin and Twigg, Stephen and Vo, Huy and Waterman, Andrew},

Title = {The Rocket Chip Generator},

Institution = {EECS Department, University of California, Berkeley},

Year = {2016},

Month = {Apr},

URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html},

Number = {UCB/EECS-2016-17},

Abstract = {Rocket Chip is an open-source Sysem-on-Chip design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. Rocket Chip generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM). For SoC designers interested in utilizing heterogeneous specialization for added efficiency gains, Rocket Chip supports the integration of custom accelerators in the form of instruction set extensions, coprocessors, or fully independent novel cores. Rocket Chip has been taped out (manufactured) eleven times, and yielded functional silicon prototypes capable of booting Linux.}

}

@INPROCEEDINGS{s4nocni:arcs2019,

author = {Martin Schoeberl and Luca Pezzarossa and Jens Spars{\o}},

title = {A minimal network interface for a simple network-on-chip},

booktitle = {Architecture of Computing Systems - ARCS 2019},

year = {2019},

editor = {Martin Schoeberl and Thilo Pionteck and Sascha Uhrig and J{\"u}rgen

Brehm and Christian Hochberger},

pages = {295--307},

month = {1},

publisher = {Springer},

day = {1},

doi = {10.1007/978-3-030-18656-2\_22},

isbn = {9783030186555},

language = {English}

}

@INPROCEEDINGS{t-crest:memnoc,

author = {Martin Schoeberl and David VH Chong and Wolfgang Puffitsch and Jens

Spars{\o}},

title = {A Time-predictable Memory Network-on-Chip},

booktitle = {Proceedings of the 14th International Workshop on Worst-Case Execution

Time Analysis (WCET 2014)},

year = {2014},

pages = {53--62},

address = {Madrid, Spain},

month = {July},

doi = {10.4230/OASIcs.WCET.2014.53},

url = {http://www.jopdesign.com/doc/memnoc.pdf}

}

@INPROCEEDINGS{t-crest:ownspm,

author = {Martin Schoeberl and T{\'o}rur Biskopst{\o} Str{\o}m and Oktay Baris

and Jens Spars\o{}},

title = {Scratchpad Memories with Ownership},

booktitle = {2019 Design, Automation and Test in Europe Conference Exhibition

(DATE)},

year = {2019}

}

@TECHREPORT{risc-v,

author = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanovic,

Krste},

title = {The {RISC-V} Instruction Set Manual, Volume {I}: Base User-Level {ISA}},

institution = {EECS Department, University of California, Berkeley},

year = {2011},

number = {UCB/EECS-2011-62},

month = {May},

url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.html}

}

@PHDTHESIS{Zimmer:EECS-2015-181,

author = {Zimmer, Michael},

title = {Predictable Processors for Mixed-Criticality Systems and Precision-Timed

I/O},

school = {EECS Department, University of California, Berkeley},

year = {2015},

month = {Aug},

number = {UCB/EECS-2015-181},

url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-181.html}

}

@INPROCEEDINGS{OpenSoC:ispass2016,

author = {Farzaf Fatollahi-Fard and David Donofrio and George Michelogiannakis

and John Shalf},

title = {OpenSoC Fabric: On-chip network generator},

booktitle = {2016 IEEE International Symposium on Performance Analysis of Systems

and Software (ISPASS)},

year = {2016},

pages = {194--203},

month = {April},

doi = {10.1109/ISPASS.2016.7482094}

}

@INPROCEEDINGS{RoCC:2015,

author={Schuyler Eldridge and Amos Waterland and Margo Seltzer and Jonathan Appavooand Ajay Joshi},

booktitle={2015 International Conference on Parallel Architecture and Compilation (PACT)},

title={Towards General-Purpose Neural Network Computing},

year={2015},

volume={},

number={},

pages={99--112},

keywords={feedforward neural nets;learning (artificial intelligence);neural net architecture;recurrent neural nets;general-purpose neural network computing;machine learning;hardware accelerator;software-hardware extension;power consumption;X-FILES;feedforward neural network;feedback neural network;neural network accelerator architecture;DANA;Artificial neural networks;Hardware;Software;Registers;Standards;Accelerator architectures},

doi={10.1109/PACT.2015.21},

ISSN={1089-795X},

month={Oct},}

@inproceedings{eldridge2015,

author = {Schuyler Eldridge and

Amos Waterland and

Margo Seltzer and

Jonathan Appavoo and

Ajay Joshi},

title = {Towards General-Purpose Neural Network Computing},

booktitle = {2015 International Conference on Parallel Architecture and Compilation,

{PACT} 2015, San Francisco, CA, USA, October 18-21, 2015},

pages = {99--112},

year = {2015},

url = {http://dx.doi.org/10.1109/PACT.2015.21},

doi = {10.1109/PACT.2015.21},

timestamp = {Wed, 04 May 2016 14:25:23 +0200},

biburl = {http://dblp.uni-trier.de/rec/bib/conf/IEEEpact/EldridgeWSAJ15},

bibsource = {dblp computer science bibliography, http://dblp.org}

}

@MISC{axi4standard,

author = {ARM},

title = {{AMBA} {AXI} and {ACE} Protocol Specification {AXI3}, {AXI4}, and {AXI4-Lite}

{ACE} and {ACE-Lite}},

howpublished = {\url{https://developer.arm.com/documentation/ihi0022/e/}},

year = {2011}

}

@MISC{soc:avalon,

author = {Altera},

title = {Avalon Interface Specification},

month = {April},

year = {2005}

}

@MISC{soc:wishbone,

author = {Wade D. Peterson},

title = {{WISHBONE} System-on-Chip {(SoC)} Interconnection Architecture for

Portable {IP} Cores, Revision: B.3},

howpublished = {Available at http://www.opencores.org},

month = {September},

year = {2002}

}

@MISC{soc:opb,

author = {IBM},

title = {On-Chip Peripheral Bus Architecture Specifications v2.1},

month = {April},

year = {2001},

owner = {admin},

timestamp = {2006.08.27}

}

@MISC{soc:amba,

author = {ARM},

title = {{AMBA} Specification (Rev 2.0)},

month = {May},

year = {1999},

owner = {admin},

timestamp = {2006.08.27}

}

@INPROCEEDINGS{simpcon,

author = {Martin Schoeberl},

title = {{SimpCon} - a Simple and Efficient {SoC} Interconnect},

booktitle = {Proceedings of the 15th Austrian Workshop on Microelectronics, Austrochip

2007},

year = {2007},

address = {Graz, Austria},

month = {October},

url = {http://www.jopdesign.com/doc/simpcon_austrochip2007.pdf}

}

@MISC{soc:ocp,

author = {{OCP-IP Association}},

title = {Open Core Protocol Specification 2.1},

howpublished = {http://www.ocpip.org/},

year = {2005},

owner = {admin},

timestamp = {2006.08.27}

}

@ARTICLE{t-crest:2015,

author = {Martin Schoeberl and Sahar Abbaspour and Benny Akesson and Neil Audsley

and Raffaele Capasso and Jamie Garside and Kees Goossens and Sven

Goossens and Scott Hansen and Reinhold Heckmann and Stefan Hepp and

Benedikt Huber and Alexander Jordan and Evangelia Kasapaki and Jens

Knoop and Yonghui Li and Daniel Prokesch and Wolfgang Puffitsch and

Peter Puschner and Andr\'{e} Rocha and Cl\'{a}udio Silva and Jens

Spars{\o} and Alessandro Tocchi},

title = {{T-CREST}: Time-predictable Multi-Core Architecture for Embedded

Systems},

journal = {Journal of Systems Architecture},

year = {2015},

volume = {61},

pages = {449--471},

number = {9},

doi = {10.1016/j.sysarc.2015.04.002},

issn = {1383-7621},

keywords = {Real-time systems},

url = {http://www.jopdesign.com/doc/t-crest-jnl.pdf}

}

@TECHREPORT{patmos:handbook,

author = {Martin Schoeberl and Florian Brandner and Stefan Hepp and Wolfgang

Puffitsch and Daniel Prokesch},

title = {Patmos Reference Handbook},

institution = {Technical University of Denmark},

year = {2014},

url = {http://patmos.compute.dtu.dk/patmos_handbook.pdf}

}

@INPROCEEDINGS{Constellation:2022,

author={Zhao, Jerry and Agrawal, Animesh and Nikolic, Borivoje and Asanović, Krste},

booktitle={2022 15th IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc)},

title={Constellation: An Open-Source {SoC}-Capable {NoC} Generator},

year={2022},

pages={1--7},

doi={10.1109/NoCArc57472.2022.9911299}}

@INPROCEEDINGS{kevin:formal:woset2021,

author = {Kevin Laeufer and Jonathan Bachrach and Koushik Sen},

title = {Open-Source Formal Verification for Chisel},

booktitle = {Proceedings of the Fourth Workshop on Open-Source EDA Technology

(WOSET)},

year = {2021},

owner = {martin},

timestamp = {2022.06.15}

}

@Book{harris2021digital,

author = {Harris, S. and Harris, D.},

title = {Digital Design and Computer Architecture, RISC-V Edition},

isbn = {9780128200643},

publisher = {Elsevier Science},

url = {https://books.google.dk/books?id=Bj9FzwEACAAJ},

year = {2021},

}

@INPROCEEDINGS{micro2022xiangshan,

author={Xu, Yinan and Yu, Zihao and Tang, Dan and Chen, Guokai and Chen, Lu and Gou, Lingrui and Jin, Yue and Li, Qianruo and Li, Xin and Li, Zuojun and Lin, Jiawei and Liu, Tong and Liu, Zhigang and Tan, Jiazhan and Wang, Huaqiang and Wang, Huizhe and Wang, Kaifan and Zhang, Chuanqi and Zhang, Fawang and Zhang, Linjuan and Zhang, Zifei and Zhao, Yangyang and Zhou, Yaoyang and Zhou, Yike and Zou, Jiangrui and Cai, Ye and Huan, Dandan and Li, Zusong and Zhao, Jiye and Chen, Zihao and He, Wei and Quan, Qiyuan and Liu, Xingwu and Wang, Sa and Shi, Kan and Sun, Ninghui and Bao, Yungang},

booktitle={2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)},

title={{Towards Developing High Performance RISC-V Processors Using Agile Methodology}},

year={2022},

volume={},

number={},

pages={1178-1199},

doi={10.1109/MICRO56248.2022.00080}

}