1/* 2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11#include <linux/clk-provider.h> 12#include <linux/clkdev.h> 13#include <linux/clk/at91_pmc.h> 14#include <linux/delay.h> 15#include <linux/of.h> 16#include <linux/of_address.h> 17#include <linux/of_irq.h> 18#include <linux/io.h> 19#include <linux/interrupt.h> 20#include <linux/irq.h> 21#include <linux/sched.h> 22#include <linux/wait.h> 23 24#include "pmc.h" 25 26#define SLOW_CLOCK_FREQ 32768 27#define MAINF_DIV 16 28#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \ 29 SLOW_CLOCK_FREQ) 30#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ) 31#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT 32 33#define MOR_KEY_MASK (0xff << 16) 34 35struct clk_main_osc { 36 struct clk_hw hw; 37 struct at91_pmc *pmc; 38 unsigned int irq; 39 wait_queue_head_t wait; 40}; 41 42#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) 43 44struct clk_main_rc_osc { 45 struct clk_hw hw; 46 struct at91_pmc *pmc; 47 unsigned int irq; 48 wait_queue_head_t wait; 49 unsigned long frequency; 50 unsigned long accuracy; 51}; 52 53#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) 54 55struct clk_rm9200_main { 56 struct clk_hw hw; 57 struct at91_pmc *pmc; 58}; 59 60#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw) 61 62struct clk_sam9x5_main { 63 struct clk_hw hw; 64 struct at91_pmc *pmc; 65 unsigned int irq; 66 wait_queue_head_t wait; 67 u8 parent; 68}; 69 70#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw) 71 72static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id) 73{ 74 struct clk_main_osc *osc = dev_id; 75 76 wake_up(&osc->wait); 77 disable_irq_nosync(osc->irq); 78 79 return IRQ_HANDLED; 80} 81 82static int clk_main_osc_prepare(struct clk_hw *hw) 83{ 84 struct clk_main_osc *osc = to_clk_main_osc(hw); 85 struct at91_pmc *pmc = osc->pmc; 86 u32 tmp; 87 88 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 89 if (tmp & AT91_PMC_OSCBYPASS) 90 return 0; 91 92 if (!(tmp & AT91_PMC_MOSCEN)) { 93 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY; 94 pmc_write(pmc, AT91_CKGR_MOR, tmp); 95 } 96 97 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) { 98 enable_irq(osc->irq); 99 wait_event(osc->wait, 100 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS); 101 } 102 103 return 0; 104} 105 106static void clk_main_osc_unprepare(struct clk_hw *hw) 107{ 108 struct clk_main_osc *osc = to_clk_main_osc(hw); 109 struct at91_pmc *pmc = osc->pmc; 110 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 111 112 if (tmp & AT91_PMC_OSCBYPASS) 113 return; 114 115 if (!(tmp & AT91_PMC_MOSCEN)) 116 return; 117 118 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN); 119 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); 120} 121 122static int clk_main_osc_is_prepared(struct clk_hw *hw) 123{ 124 struct clk_main_osc *osc = to_clk_main_osc(hw); 125 struct at91_pmc *pmc = osc->pmc; 126 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 127 128 if (tmp & AT91_PMC_OSCBYPASS) 129 return 1; 130 131 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) && 132 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN)); 133} 134 135static const struct clk_ops main_osc_ops = { 136 .prepare = clk_main_osc_prepare, 137 .unprepare = clk_main_osc_unprepare, 138 .is_prepared = clk_main_osc_is_prepared, 139}; 140 141static struct clk * __init 142at91_clk_register_main_osc(struct at91_pmc *pmc, 143 unsigned int irq, 144 const char *name, 145 const char *parent_name, 146 bool bypass) 147{ 148 int ret; 149 struct clk_main_osc *osc; 150 struct clk *clk = NULL; 151 struct clk_init_data init; 152 153 if (!pmc || !irq || !name || !parent_name) 154 return ERR_PTR(-EINVAL); 155 156 osc = kzalloc(sizeof(*osc), GFP_KERNEL); 157 if (!osc) 158 return ERR_PTR(-ENOMEM); 159 160 init.name = name; 161 init.ops = &main_osc_ops; 162 init.parent_names = &parent_name; 163 init.num_parents = 1; 164 init.flags = CLK_IGNORE_UNUSED; 165 166 osc->hw.init = &init; 167 osc->pmc = pmc; 168 osc->irq = irq; 169 170 init_waitqueue_head(&osc->wait); 171 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); 172 ret = request_irq(osc->irq, clk_main_osc_irq_handler, 173 IRQF_TRIGGER_HIGH, name, osc); 174 if (ret) 175 return ERR_PTR(ret); 176 177 if (bypass) 178 pmc_write(pmc, AT91_CKGR_MOR, 179 (pmc_read(pmc, AT91_CKGR_MOR) & 180 ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) | 181 AT91_PMC_OSCBYPASS | AT91_PMC_KEY); 182 183 clk = clk_register(NULL, &osc->hw); 184 if (IS_ERR(clk)) { 185 free_irq(irq, osc); 186 kfree(osc); 187 } 188 189 return clk; 190} 191 192void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, 193 struct at91_pmc *pmc) 194{ 195 struct clk *clk; 196 unsigned int irq; 197 const char *name = np->name; 198 const char *parent_name; 199 bool bypass; 200 201 of_property_read_string(np, "clock-output-names", &name); 202 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 203 parent_name = of_clk_get_parent_name(np, 0); 204 205 irq = irq_of_parse_and_map(np, 0); 206 if (!irq) 207 return; 208 209 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); 210 if (IS_ERR(clk)) 211 return; 212 213 of_clk_add_provider(np, of_clk_src_simple_get, clk); 214} 215 216static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id) 217{ 218 struct clk_main_rc_osc *osc = dev_id; 219 220 wake_up(&osc->wait); 221 disable_irq_nosync(osc->irq); 222 223 return IRQ_HANDLED; 224} 225 226static int clk_main_rc_osc_prepare(struct clk_hw *hw) 227{ 228 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 229 struct at91_pmc *pmc = osc->pmc; 230 u32 tmp; 231 232 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 233 234 if (!(tmp & AT91_PMC_MOSCRCEN)) { 235 tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY; 236 pmc_write(pmc, AT91_CKGR_MOR, tmp); 237 } 238 239 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) { 240 enable_irq(osc->irq); 241 wait_event(osc->wait, 242 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS); 243 } 244 245 return 0; 246} 247 248static void clk_main_rc_osc_unprepare(struct clk_hw *hw) 249{ 250 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 251 struct at91_pmc *pmc = osc->pmc; 252 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); 253 254 if (!(tmp & AT91_PMC_MOSCRCEN)) 255 return; 256 257 tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN); 258 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); 259} 260 261static int clk_main_rc_osc_is_prepared(struct clk_hw *hw) 262{ 263 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 264 struct at91_pmc *pmc = osc->pmc; 265 266 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) && 267 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN)); 268} 269 270static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw, 271 unsigned long parent_rate) 272{ 273 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 274 275 return osc->frequency; 276} 277 278static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw, 279 unsigned long parent_acc) 280{ 281 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); 282 283 return osc->accuracy; 284} 285 286static const struct clk_ops main_rc_osc_ops = { 287 .prepare = clk_main_rc_osc_prepare, 288 .unprepare = clk_main_rc_osc_unprepare, 289 .is_prepared = clk_main_rc_osc_is_prepared, 290 .recalc_rate = clk_main_rc_osc_recalc_rate, 291 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, 292}; 293 294static struct clk * __init 295at91_clk_register_main_rc_osc(struct at91_pmc *pmc, 296 unsigned int irq, 297 const char *name, 298 u32 frequency, u32 accuracy) 299{ 300 int ret; 301 struct clk_main_rc_osc *osc; 302 struct clk *clk = NULL; 303 struct clk_init_data init; 304 305 if (!pmc || !irq || !name || !frequency) 306 return ERR_PTR(-EINVAL); 307 308 osc = kzalloc(sizeof(*osc), GFP_KERNEL); 309 if (!osc) 310 return ERR_PTR(-ENOMEM); 311 312 init.name = name; 313 init.ops = &main_rc_osc_ops; 314 init.parent_names = NULL; 315 init.num_parents = 0; 316 init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED; 317 318 osc->hw.init = &init; 319 osc->pmc = pmc; 320 osc->irq = irq; 321 osc->frequency = frequency; 322 osc->accuracy = accuracy; 323 324 init_waitqueue_head(&osc->wait); 325 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); 326 ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler, 327 IRQF_TRIGGER_HIGH, name, osc); 328 if (ret) 329 return ERR_PTR(ret); 330 331 clk = clk_register(NULL, &osc->hw); 332 if (IS_ERR(clk)) { 333 free_irq(irq, osc); 334 kfree(osc); 335 } 336 337 return clk; 338} 339 340void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, 341 struct at91_pmc *pmc) 342{ 343 struct clk *clk; 344 unsigned int irq; 345 u32 frequency = 0; 346 u32 accuracy = 0; 347 const char *name = np->name; 348 349 of_property_read_string(np, "clock-output-names", &name); 350 of_property_read_u32(np, "clock-frequency", &frequency); 351 of_property_read_u32(np, "clock-accuracy", &accuracy); 352 353 irq = irq_of_parse_and_map(np, 0); 354 if (!irq) 355 return; 356 357 clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency, 358 accuracy); 359 if (IS_ERR(clk)) 360 return; 361 362 of_clk_add_provider(np, of_clk_src_simple_get, clk); 363} 364 365 366static int clk_main_probe_frequency(struct at91_pmc *pmc) 367{ 368 unsigned long prep_time, timeout; 369 u32 tmp; 370 371 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT); 372 do { 373 prep_time = jiffies; 374 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 375 if (tmp & AT91_PMC_MAINRDY) 376 return 0; 377 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT); 378 } while (time_before(prep_time, timeout)); 379 380 return -ETIMEDOUT; 381} 382 383static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc, 384 unsigned long parent_rate) 385{ 386 u32 tmp; 387 388 if (parent_rate) 389 return parent_rate; 390 391 pr_warn("Main crystal frequency not set, using approximate value\n"); 392 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 393 if (!(tmp & AT91_PMC_MAINRDY)) 394 return 0; 395 396 return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; 397} 398 399static int clk_rm9200_main_prepare(struct clk_hw *hw) 400{ 401 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 402 403 return clk_main_probe_frequency(clkmain->pmc); 404} 405 406static int clk_rm9200_main_is_prepared(struct clk_hw *hw) 407{ 408 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 409 410 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY); 411} 412 413static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw, 414 unsigned long parent_rate) 415{ 416 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); 417 418 return clk_main_recalc_rate(clkmain->pmc, parent_rate); 419} 420 421static const struct clk_ops rm9200_main_ops = { 422 .prepare = clk_rm9200_main_prepare, 423 .is_prepared = clk_rm9200_main_is_prepared, 424 .recalc_rate = clk_rm9200_main_recalc_rate, 425}; 426 427static struct clk * __init 428at91_clk_register_rm9200_main(struct at91_pmc *pmc, 429 const char *name, 430 const char *parent_name) 431{ 432 struct clk_rm9200_main *clkmain; 433 struct clk *clk = NULL; 434 struct clk_init_data init; 435 436 if (!pmc || !name) 437 return ERR_PTR(-EINVAL); 438 439 if (!parent_name) 440 return ERR_PTR(-EINVAL); 441 442 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); 443 if (!clkmain) 444 return ERR_PTR(-ENOMEM); 445 446 init.name = name; 447 init.ops = &rm9200_main_ops; 448 init.parent_names = &parent_name; 449 init.num_parents = 1; 450 init.flags = 0; 451 452 clkmain->hw.init = &init; 453 clkmain->pmc = pmc; 454 455 clk = clk_register(NULL, &clkmain->hw); 456 if (IS_ERR(clk)) 457 kfree(clkmain); 458 459 return clk; 460} 461 462void __init of_at91rm9200_clk_main_setup(struct device_node *np, 463 struct at91_pmc *pmc) 464{ 465 struct clk *clk; 466 const char *parent_name; 467 const char *name = np->name; 468 469 parent_name = of_clk_get_parent_name(np, 0); 470 of_property_read_string(np, "clock-output-names", &name); 471 472 clk = at91_clk_register_rm9200_main(pmc, name, parent_name); 473 if (IS_ERR(clk)) 474 return; 475 476 of_clk_add_provider(np, of_clk_src_simple_get, clk); 477} 478 479static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id) 480{ 481 struct clk_sam9x5_main *clkmain = dev_id; 482 483 wake_up(&clkmain->wait); 484 disable_irq_nosync(clkmain->irq); 485 486 return IRQ_HANDLED; 487} 488 489static int clk_sam9x5_main_prepare(struct clk_hw *hw) 490{ 491 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 492 struct at91_pmc *pmc = clkmain->pmc; 493 494 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { 495 enable_irq(clkmain->irq); 496 wait_event(clkmain->wait, 497 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 498 } 499 500 return clk_main_probe_frequency(pmc); 501} 502 503static int clk_sam9x5_main_is_prepared(struct clk_hw *hw) 504{ 505 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 506 507 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 508} 509 510static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw, 511 unsigned long parent_rate) 512{ 513 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 514 515 return clk_main_recalc_rate(clkmain->pmc, parent_rate); 516} 517 518static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index) 519{ 520 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 521 struct at91_pmc *pmc = clkmain->pmc; 522 u32 tmp; 523 524 if (index > 1) 525 return -EINVAL; 526 527 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; 528 529 if (index && !(tmp & AT91_PMC_MOSCSEL)) 530 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL); 531 else if (!index && (tmp & AT91_PMC_MOSCSEL)) 532 pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL); 533 534 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { 535 enable_irq(clkmain->irq); 536 wait_event(clkmain->wait, 537 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); 538 } 539 540 return 0; 541} 542 543static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw) 544{ 545 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); 546 547 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN); 548} 549 550static const struct clk_ops sam9x5_main_ops = { 551 .prepare = clk_sam9x5_main_prepare, 552 .is_prepared = clk_sam9x5_main_is_prepared, 553 .recalc_rate = clk_sam9x5_main_recalc_rate, 554 .set_parent = clk_sam9x5_main_set_parent, 555 .get_parent = clk_sam9x5_main_get_parent, 556}; 557 558static struct clk * __init 559at91_clk_register_sam9x5_main(struct at91_pmc *pmc, 560 unsigned int irq, 561 const char *name, 562 const char **parent_names, 563 int num_parents) 564{ 565 int ret; 566 struct clk_sam9x5_main *clkmain; 567 struct clk *clk = NULL; 568 struct clk_init_data init; 569 570 if (!pmc || !irq || !name) 571 return ERR_PTR(-EINVAL); 572 573 if (!parent_names || !num_parents) 574 return ERR_PTR(-EINVAL); 575 576 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); 577 if (!clkmain) 578 return ERR_PTR(-ENOMEM); 579 580 init.name = name; 581 init.ops = &sam9x5_main_ops; 582 init.parent_names = parent_names; 583 init.num_parents = num_parents; 584 init.flags = CLK_SET_PARENT_GATE; 585 586 clkmain->hw.init = &init; 587 clkmain->pmc = pmc; 588 clkmain->irq = irq; 589 clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & 590 AT91_PMC_MOSCEN); 591 init_waitqueue_head(&clkmain->wait); 592 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN); 593 ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler, 594 IRQF_TRIGGER_HIGH, name, clkmain); 595 if (ret) 596 return ERR_PTR(ret); 597 598 clk = clk_register(NULL, &clkmain->hw); 599 if (IS_ERR(clk)) { 600 free_irq(clkmain->irq, clkmain); 601 kfree(clkmain); 602 } 603 604 return clk; 605} 606 607void __init of_at91sam9x5_clk_main_setup(struct device_node *np, 608 struct at91_pmc *pmc) 609{ 610 struct clk *clk; 611 const char *parent_names[2]; 612 int num_parents; 613 unsigned int irq; 614 const char *name = np->name; 615 int i; 616 617 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 618 if (num_parents <= 0 || num_parents > 2) 619 return; 620 621 for (i = 0; i < num_parents; ++i) { 622 parent_names[i] = of_clk_get_parent_name(np, i); 623 if (!parent_names[i]) 624 return; 625 } 626 627 of_property_read_string(np, "clock-output-names", &name); 628 629 irq = irq_of_parse_and_map(np, 0); 630 if (!irq) 631 return; 632 633 clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names, 634 num_parents); 635 if (IS_ERR(clk)) 636 return; 637 638 of_clk_add_provider(np, of_clk_src_simple_get, clk); 639} 640