1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5250 SoC. 11*/ 12 13#include <dt-bindings/clock/exynos5250.h> 14#include <linux/clk.h> 15#include <linux/clkdev.h> 16#include <linux/clk-provider.h> 17#include <linux/of.h> 18#include <linux/of_address.h> 19#include <linux/syscore_ops.h> 20 21#include "clk.h" 22 23#define APLL_LOCK 0x0 24#define APLL_CON0 0x100 25#define SRC_CPU 0x200 26#define DIV_CPU0 0x500 27#define PWR_CTRL1 0x1020 28#define PWR_CTRL2 0x1024 29#define MPLL_LOCK 0x4000 30#define MPLL_CON0 0x4100 31#define SRC_CORE1 0x4204 32#define GATE_IP_ACP 0x8800 33#define GATE_IP_ISP0 0xc800 34#define GATE_IP_ISP1 0xc804 35#define CPLL_LOCK 0x10020 36#define EPLL_LOCK 0x10030 37#define VPLL_LOCK 0x10040 38#define GPLL_LOCK 0x10050 39#define CPLL_CON0 0x10120 40#define EPLL_CON0 0x10130 41#define VPLL_CON0 0x10140 42#define GPLL_CON0 0x10150 43#define SRC_TOP0 0x10210 44#define SRC_TOP1 0x10214 45#define SRC_TOP2 0x10218 46#define SRC_TOP3 0x1021c 47#define SRC_GSCL 0x10220 48#define SRC_DISP1_0 0x1022c 49#define SRC_MAU 0x10240 50#define SRC_FSYS 0x10244 51#define SRC_GEN 0x10248 52#define SRC_PERIC0 0x10250 53#define SRC_PERIC1 0x10254 54#define SRC_MASK_GSCL 0x10320 55#define SRC_MASK_DISP1_0 0x1032c 56#define SRC_MASK_MAU 0x10334 57#define SRC_MASK_FSYS 0x10340 58#define SRC_MASK_GEN 0x10344 59#define SRC_MASK_PERIC0 0x10350 60#define SRC_MASK_PERIC1 0x10354 61#define DIV_TOP0 0x10510 62#define DIV_TOP1 0x10514 63#define DIV_GSCL 0x10520 64#define DIV_DISP1_0 0x1052c 65#define DIV_GEN 0x1053c 66#define DIV_MAU 0x10544 67#define DIV_FSYS0 0x10548 68#define DIV_FSYS1 0x1054c 69#define DIV_FSYS2 0x10550 70#define DIV_PERIC0 0x10558 71#define DIV_PERIC1 0x1055c 72#define DIV_PERIC2 0x10560 73#define DIV_PERIC3 0x10564 74#define DIV_PERIC4 0x10568 75#define DIV_PERIC5 0x1056c 76#define GATE_IP_GSCL 0x10920 77#define GATE_IP_DISP1 0x10928 78#define GATE_IP_MFC 0x1092c 79#define GATE_IP_G3D 0x10930 80#define GATE_IP_GEN 0x10934 81#define GATE_IP_FSYS 0x10944 82#define GATE_IP_PERIC 0x10950 83#define GATE_IP_PERIS 0x10960 84#define BPLL_LOCK 0x20010 85#define BPLL_CON0 0x20110 86#define SRC_CDREX 0x20200 87#define PLL_DIV2_SEL 0x20a24 88 89/*Below definitions are used for PWR_CTRL settings*/ 90#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) 91#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) 92#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 93#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 94#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 95#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 96#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 97#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 98 99#define PWR_CTRL2_DIV2_UP_EN (1 << 25) 100#define PWR_CTRL2_DIV1_UP_EN (1 << 24) 101#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) 102#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) 103#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) 104#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) 105 106/* list of PLLs to be registered */ 107enum exynos5250_plls { 108 apll, mpll, cpll, epll, vpll, gpll, bpll, 109 nr_plls /* number of PLLs */ 110}; 111 112static void __iomem *reg_base; 113 114#ifdef CONFIG_PM_SLEEP 115static struct samsung_clk_reg_dump *exynos5250_save; 116 117/* 118 * list of controller registers to be saved and restored during a 119 * suspend/resume cycle. 120 */ 121static unsigned long exynos5250_clk_regs[] __initdata = { 122 SRC_CPU, 123 DIV_CPU0, 124 PWR_CTRL1, 125 PWR_CTRL2, 126 SRC_CORE1, 127 SRC_TOP0, 128 SRC_TOP1, 129 SRC_TOP2, 130 SRC_TOP3, 131 SRC_GSCL, 132 SRC_DISP1_0, 133 SRC_MAU, 134 SRC_FSYS, 135 SRC_GEN, 136 SRC_PERIC0, 137 SRC_PERIC1, 138 SRC_MASK_GSCL, 139 SRC_MASK_DISP1_0, 140 SRC_MASK_MAU, 141 SRC_MASK_FSYS, 142 SRC_MASK_GEN, 143 SRC_MASK_PERIC0, 144 SRC_MASK_PERIC1, 145 DIV_TOP0, 146 DIV_TOP1, 147 DIV_GSCL, 148 DIV_DISP1_0, 149 DIV_GEN, 150 DIV_MAU, 151 DIV_FSYS0, 152 DIV_FSYS1, 153 DIV_FSYS2, 154 DIV_PERIC0, 155 DIV_PERIC1, 156 DIV_PERIC2, 157 DIV_PERIC3, 158 DIV_PERIC4, 159 DIV_PERIC5, 160 GATE_IP_GSCL, 161 GATE_IP_MFC, 162 GATE_IP_G3D, 163 GATE_IP_GEN, 164 GATE_IP_FSYS, 165 GATE_IP_PERIC, 166 GATE_IP_PERIS, 167 SRC_CDREX, 168 PLL_DIV2_SEL, 169 GATE_IP_DISP1, 170 GATE_IP_ACP, 171 GATE_IP_ISP0, 172 GATE_IP_ISP1, 173}; 174 175static int exynos5250_clk_suspend(void) 176{ 177 samsung_clk_save(reg_base, exynos5250_save, 178 ARRAY_SIZE(exynos5250_clk_regs)); 179 180 return 0; 181} 182 183static void exynos5250_clk_resume(void) 184{ 185 samsung_clk_restore(reg_base, exynos5250_save, 186 ARRAY_SIZE(exynos5250_clk_regs)); 187} 188 189static struct syscore_ops exynos5250_clk_syscore_ops = { 190 .suspend = exynos5250_clk_suspend, 191 .resume = exynos5250_clk_resume, 192}; 193 194static void exynos5250_clk_sleep_init(void) 195{ 196 exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs, 197 ARRAY_SIZE(exynos5250_clk_regs)); 198 if (!exynos5250_save) { 199 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 200 __func__); 201 return; 202 } 203 204 register_syscore_ops(&exynos5250_clk_syscore_ops); 205} 206#else 207static void exynos5250_clk_sleep_init(void) {} 208#endif 209 210/* list of all parent clock list */ 211PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 212PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; 213PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 214PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 215PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 216PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" }; 217PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" }; 218PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 219PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 220PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 221PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" }; 222PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; 223PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; 224PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; 225PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; 226PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; 227PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; 228PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; 229PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; 230PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" }; 231PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 232PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; 233PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 234 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", 235 "mout_mpll_user", "mout_epll", "mout_vpll", 236 "mout_cpll", "none", "none", 237 "none", "none", "none", 238 "none" }; 239PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 240 "sclk_uhostphy", "fin_pll", 241 "mout_mpll_user", "mout_epll", "mout_vpll", 242 "mout_cpll", "none", "none", 243 "none", "none", "none", 244 "none" }; 245PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 246 "sclk_uhostphy", "fin_pll", 247 "mout_mpll_user", "mout_epll", "mout_vpll", 248 "mout_cpll", "none", "none", 249 "none", "none", "none", 250 "none" }; 251PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 252 "sclk_uhostphy", "fin_pll", 253 "mout_mpll_user", "mout_epll", "mout_vpll", 254 "mout_cpll", "none", "none", 255 "none", "none", "none", 256 "none" }; 257PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 258 "spdif_extclk" }; 259 260/* fixed rate clocks generated outside the soc */ 261static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 262 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 263}; 264 265/* fixed rate clocks generated inside the soc */ 266static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 267 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 268 FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 269 FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 270 FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 271}; 272 273static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 274 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 275 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 276}; 277 278static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 279 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 280}; 281 282static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 283 /* 284 * NOTE: Following table is sorted by (clock domain, register address, 285 * bitfield shift) triplet in ascending order. When adding new entries, 286 * please make sure that the order is kept, to avoid merge conflicts 287 * and make further work with defined data easier. 288 */ 289 290 /* 291 * CMU_CPU 292 */ 293 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 294 CLK_SET_RATE_PARENT, 0, "mout_apll"), 295 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 296 297 /* 298 * CMU_CORE 299 */ 300 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 301 302 /* 303 * CMU_TOP 304 */ 305 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 306 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 307 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 308 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), 309 310 MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1), 311 MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), 312 313 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 314 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), 315 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 316 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 317 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 318 MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1), 319 320 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), 321 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), 322 MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1), 323 MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p, 324 SRC_TOP3, 20, 1), 325 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), 326 327 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 328 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 329 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 330 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 331 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 332 333 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 334 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 335 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 336 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 337 338 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 339 340 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 341 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 342 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 343 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 344 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 345 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 346 347 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 348 349 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 350 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 351 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 352 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 353 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 354 355 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 356 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 357 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 358 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 359 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 360 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 361 362 /* 363 * CMU_CDREX 364 */ 365 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 366 367 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 368 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 369}; 370 371static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 372 /* 373 * NOTE: Following table is sorted by (clock domain, register address, 374 * bitfield shift) triplet in ascending order. When adding new entries, 375 * please make sure that the order is kept, to avoid merge conflicts 376 * and make further work with defined data easier. 377 */ 378 379 /* 380 * CMU_CPU 381 */ 382 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 383 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 384 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), 385 386 /* 387 * CMU_TOP 388 */ 389 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), 390 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 391 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 392 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), 393 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 394 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 395 24, 3), 396 397 DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3), 398 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), 399 400 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 401 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 402 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 403 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 404 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 405 406 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 407 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 408 DIV_F(0, "div_mipi1_pre", "div_mipi1", 409 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 410 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 411 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4), 412 413 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 414 415 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 416 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 417 418 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 419 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 420 421 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 422 DIV_F(0, "div_mmc_pre0", "div_mmc0", 423 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 424 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 425 DIV_F(0, "div_mmc_pre1", "div_mmc1", 426 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 427 428 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 429 DIV_F(0, "div_mmc_pre2", "div_mmc2", 430 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 431 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 432 DIV_F(0, "div_mmc_pre3", "div_mmc3", 433 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 434 435 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 436 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 437 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 438 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 439 440 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 441 DIV_F(0, "div_spi_pre0", "div_spi0", 442 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 443 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 444 DIV_F(0, "div_spi_pre1", "div_spi1", 445 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 446 447 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 448 DIV_F(0, "div_spi_pre2", "div_spi2", 449 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 450 451 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 452 453 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 454 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 455 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 456 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 457 458 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 459 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 460}; 461 462static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 463 /* 464 * NOTE: Following table is sorted by (clock domain, register address, 465 * bitfield shift) triplet in ascending order. When adding new entries, 466 * please make sure that the order is kept, to avoid merge conflicts 467 * and make further work with defined data easier. 468 */ 469 470 /* 471 * CMU_ACP 472 */ 473 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), 474 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0), 475 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), 476 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), 477 478 /* 479 * CMU_TOP 480 */ 481 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer", 482 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 483 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", 484 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 485 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", 486 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 487 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa", 488 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 489 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb", 490 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 491 492 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", 493 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 494 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1", 495 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 496 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp", 497 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 498 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 499 SRC_MASK_DISP1_0, 20, 0, 0), 500 501 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", 502 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 503 504 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", 505 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 506 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", 507 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 508 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", 509 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 510 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", 511 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 512 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 513 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 514 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3", 515 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 516 517 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg", 518 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 519 520 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 521 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 522 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 523 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 524 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", 525 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 526 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", 527 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 528 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm", 529 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 530 531 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", 532 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 533 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", 534 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 535 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 536 SRC_MASK_PERIC1, 4, 0, 0), 537 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", 538 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 539 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", 540 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 541 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", 542 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 543 544 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 545 0), 546 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 547 0), 548 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 549 0), 550 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 551 0), 552 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 553 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 554 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub", 555 GATE_IP_GSCL, 7, 0, 0), 556 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub", 557 GATE_IP_GSCL, 8, 0, 0), 558 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub", 559 GATE_IP_GSCL, 9, 0, 0), 560 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", 561 GATE_IP_GSCL, 10, 0, 0), 562 563 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, 564 0), 565 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, 566 0), 567 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, 568 0), 569 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), 570 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, 571 0), 572 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 573 0), 574 575 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), 576 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 577 0), 578 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 579 0), 580 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0, 581 CLK_SET_RATE_PARENT, 0), 582 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), 583 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), 584 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), 585 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0, 586 0), 587 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0), 588 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0), 589 590 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0), 591 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0), 592 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0), 593 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0), 594 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0), 595 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0), 596 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0), 597 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0), 598 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0), 599 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0), 600 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0), 601 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0), 602 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200", 603 GATE_IP_FSYS, 24, 0, 0), 604 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0, 605 0), 606 607 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0), 608 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0), 609 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0), 610 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0), 611 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0), 612 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0), 613 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0), 614 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0), 615 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0), 616 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0), 617 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0), 618 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0), 619 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0), 620 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0), 621 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0), 622 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0), 623 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0), 624 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0), 625 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0), 626 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0), 627 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0), 628 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0), 629 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0), 630 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0), 631 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0), 632 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0), 633 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0), 634 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0), 635 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0), 636 637 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0), 638 GATE(CLK_SYSREG, "sysreg", "div_aclk66", 639 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 640 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 641 0), 642 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66", 643 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0), 644 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66", 645 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0), 646 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66", 647 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0), 648 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0), 649 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0), 650 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0), 651 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0), 652 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0), 653 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0), 654 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0), 655 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0), 656 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0), 657 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0), 658 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0), 659 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0), 660 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), 661 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), 662 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), 663 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", 664 GATE_IP_DISP1, 9, 0, 0), 665 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", 666 GATE_IP_DISP1, 8, 0, 0), 667 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0), 668 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub", 669 GATE_IP_ISP0, 8, 0, 0), 670 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub", 671 GATE_IP_ISP0, 9, 0, 0), 672 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub", 673 GATE_IP_ISP0, 10, 0, 0), 674 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub", 675 GATE_IP_ISP0, 11, 0, 0), 676 GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub", 677 GATE_IP_ISP0, 12, 0, 0), 678 GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub", 679 GATE_IP_ISP0, 13, 0, 0), 680 GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub", 681 GATE_IP_ISP1, 4, 0, 0), 682 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub", 683 GATE_IP_ISP1, 5, 0, 0), 684 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub", 685 GATE_IP_ISP1, 6, 0, 0), 686 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub", 687 GATE_IP_ISP1, 7, 0, 0), 688}; 689 690static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 691 /* sorted in descending order */ 692 /* PLL_36XX_RATE(rate, m, p, s, k) */ 693 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 694 /* Not in UM, but need for eDP on snow */ 695 PLL_36XX_RATE(70500000, 94, 2, 4, 0), 696 { }, 697}; 698 699static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { 700 /* sorted in descending order */ 701 /* PLL_36XX_RATE(rate, m, p, s, k) */ 702 PLL_36XX_RATE(192000000, 64, 2, 2, 0), 703 PLL_36XX_RATE(180633600, 90, 3, 2, 20762), 704 PLL_36XX_RATE(180000000, 90, 3, 2, 0), 705 PLL_36XX_RATE(73728000, 98, 2, 4, 19923), 706 PLL_36XX_RATE(67737600, 90, 2, 4, 20762), 707 PLL_36XX_RATE(49152000, 98, 3, 4, 19923), 708 PLL_36XX_RATE(45158400, 90, 3, 4, 20762), 709 PLL_36XX_RATE(32768000, 131, 3, 5, 4719), 710 { }, 711}; 712 713static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { 714 /* sorted in descending order */ 715 /* PLL_35XX_RATE(rate, m, p, s) */ 716 PLL_35XX_RATE(1700000000, 425, 6, 0), 717 PLL_35XX_RATE(1600000000, 200, 3, 0), 718 PLL_35XX_RATE(1500000000, 250, 4, 0), 719 PLL_35XX_RATE(1400000000, 175, 3, 0), 720 PLL_35XX_RATE(1300000000, 325, 6, 0), 721 PLL_35XX_RATE(1200000000, 200, 4, 0), 722 PLL_35XX_RATE(1100000000, 275, 6, 0), 723 PLL_35XX_RATE(1000000000, 125, 3, 0), 724 PLL_35XX_RATE(900000000, 150, 4, 0), 725 PLL_35XX_RATE(800000000, 100, 3, 0), 726 PLL_35XX_RATE(700000000, 175, 3, 1), 727 PLL_35XX_RATE(600000000, 200, 4, 1), 728 PLL_35XX_RATE(500000000, 125, 3, 1), 729 PLL_35XX_RATE(400000000, 100, 3, 1), 730 PLL_35XX_RATE(300000000, 200, 4, 2), 731 PLL_35XX_RATE(200000000, 100, 3, 2), 732}; 733 734static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 735 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 736 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 737 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 738 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL), 739 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 740 BPLL_CON0, NULL), 741 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, 742 GPLL_CON0, NULL), 743 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 744 CPLL_CON0, NULL), 745 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 746 EPLL_CON0, NULL), 747 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 748 VPLL_LOCK, VPLL_CON0, NULL), 749}; 750 751static const struct of_device_id ext_clk_match[] __initconst = { 752 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 753 { }, 754}; 755 756/* register exynox5250 clocks */ 757static void __init exynos5250_clk_init(struct device_node *np) 758{ 759 struct samsung_clk_provider *ctx; 760 unsigned int tmp; 761 762 if (np) { 763 reg_base = of_iomap(np, 0); 764 if (!reg_base) 765 panic("%s: failed to map registers\n", __func__); 766 } else { 767 panic("%s: unable to determine soc\n", __func__); 768 } 769 770 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 771 if (!ctx) 772 panic("%s: unable to allocate context.\n", __func__); 773 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, 774 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 775 ext_clk_match); 776 samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks, 777 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 778 779 if (_get_rate("fin_pll") == 24 * MHZ) { 780 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; 781 exynos5250_plls[apll].rate_table = apll_24mhz_tbl; 782 } 783 784 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 785 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 786 787 samsung_clk_register_pll(ctx, exynos5250_plls, 788 ARRAY_SIZE(exynos5250_plls), 789 reg_base); 790 samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks, 791 ARRAY_SIZE(exynos5250_fixed_rate_clks)); 792 samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks, 793 ARRAY_SIZE(exynos5250_fixed_factor_clks)); 794 samsung_clk_register_mux(ctx, exynos5250_mux_clks, 795 ARRAY_SIZE(exynos5250_mux_clks)); 796 samsung_clk_register_div(ctx, exynos5250_div_clks, 797 ARRAY_SIZE(exynos5250_div_clks)); 798 samsung_clk_register_gate(ctx, exynos5250_gate_clks, 799 ARRAY_SIZE(exynos5250_gate_clks)); 800 801 /* 802 * Enable arm clock down (in idle) and set arm divider 803 * ratios in WFI/WFE state. 804 */ 805 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO | 806 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 807 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 808 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 809 __raw_writel(tmp, reg_base + PWR_CTRL1); 810 811 /* 812 * Enable arm clock up (on exiting idle). Set arm divider 813 * ratios when not in idle along with the standby duration 814 * ratios. 815 */ 816 tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN | 817 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL | 818 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); 819 __raw_writel(tmp, reg_base + PWR_CTRL2); 820 821 exynos5250_clk_sleep_init(); 822 823 samsung_clk_of_add_provider(np, ctx); 824 825 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 826 _get_rate("div_arm2")); 827} 828CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); 829