1/* 2 * Copyright (c) 2010 Picochip Ltd., Jamie Iles 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18#ifndef __PICOXCELL_CRYPTO_REGS_H__ 19#define __PICOXCELL_CRYPTO_REGS_H__ 20 21#define SPA_STATUS_OK 0 22#define SPA_STATUS_ICV_FAIL 1 23#define SPA_STATUS_MEMORY_ERROR 2 24#define SPA_STATUS_BLOCK_ERROR 3 25 26#define SPA_IRQ_CTRL_STAT_CNT_OFFSET 16 27#define SPA_IRQ_STAT_STAT_MASK (1 << 4) 28#define SPA_FIFO_STAT_STAT_OFFSET 16 29#define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET) 30#define SPA_STATUS_RES_CODE_OFFSET 24 31#define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET) 32#define SPA_KEY_SZ_CTX_INDEX_OFFSET 8 33#define SPA_KEY_SZ_CIPHER_OFFSET 31 34 35#define SPA_IRQ_EN_REG_OFFSET 0x00000000 36#define SPA_IRQ_STAT_REG_OFFSET 0x00000004 37#define SPA_IRQ_CTRL_REG_OFFSET 0x00000008 38#define SPA_FIFO_STAT_REG_OFFSET 0x0000000C 39#define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010 40#define SPA_SRC_PTR_REG_OFFSET 0x00000020 41#define SPA_DST_PTR_REG_OFFSET 0x00000024 42#define SPA_OFFSET_REG_OFFSET 0x00000028 43#define SPA_AAD_LEN_REG_OFFSET 0x0000002C 44#define SPA_PROC_LEN_REG_OFFSET 0x00000030 45#define SPA_ICV_LEN_REG_OFFSET 0x00000034 46#define SPA_ICV_OFFSET_REG_OFFSET 0x00000038 47#define SPA_SW_CTRL_REG_OFFSET 0x0000003C 48#define SPA_CTRL_REG_OFFSET 0x00000040 49#define SPA_AUX_INFO_REG_OFFSET 0x0000004C 50#define SPA_STAT_POP_REG_OFFSET 0x00000050 51#define SPA_STATUS_REG_OFFSET 0x00000054 52#define SPA_KEY_SZ_REG_OFFSET 0x00000100 53#define SPA_CIPH_KEY_BASE_REG_OFFSET 0x00004000 54#define SPA_HASH_KEY_BASE_REG_OFFSET 0x00008000 55#define SPA_RC4_CTX_BASE_REG_OFFSET 0x00020000 56 57#define SPA_IRQ_EN_REG_RESET 0x00000000 58#define SPA_IRQ_CTRL_REG_RESET 0x00000000 59#define SPA_FIFO_STAT_REG_RESET 0x00000000 60#define SPA_SDMA_BRST_SZ_REG_RESET 0x00000000 61#define SPA_SRC_PTR_REG_RESET 0x00000000 62#define SPA_DST_PTR_REG_RESET 0x00000000 63#define SPA_OFFSET_REG_RESET 0x00000000 64#define SPA_AAD_LEN_REG_RESET 0x00000000 65#define SPA_PROC_LEN_REG_RESET 0x00000000 66#define SPA_ICV_LEN_REG_RESET 0x00000000 67#define SPA_ICV_OFFSET_REG_RESET 0x00000000 68#define SPA_SW_CTRL_REG_RESET 0x00000000 69#define SPA_CTRL_REG_RESET 0x00000000 70#define SPA_AUX_INFO_REG_RESET 0x00000000 71#define SPA_STAT_POP_REG_RESET 0x00000000 72#define SPA_STATUS_REG_RESET 0x00000000 73#define SPA_KEY_SZ_REG_RESET 0x00000000 74 75#define SPA_CTRL_HASH_ALG_IDX 4 76#define SPA_CTRL_CIPH_MODE_IDX 8 77#define SPA_CTRL_HASH_MODE_IDX 12 78#define SPA_CTRL_CTX_IDX 16 79#define SPA_CTRL_ENCRYPT_IDX 24 80#define SPA_CTRL_AAD_COPY 25 81#define SPA_CTRL_ICV_PT 26 82#define SPA_CTRL_ICV_ENC 27 83#define SPA_CTRL_ICV_APPEND 28 84#define SPA_CTRL_KEY_EXP 29 85 86#define SPA_KEY_SZ_CXT_IDX 8 87#define SPA_KEY_SZ_CIPHER_IDX 31 88 89#define SPA_IRQ_EN_CMD0_EN (1 << 0) 90#define SPA_IRQ_EN_STAT_EN (1 << 4) 91#define SPA_IRQ_EN_GLBL_EN (1 << 31) 92 93#define SPA_CTRL_CIPH_ALG_NULL 0x00 94#define SPA_CTRL_CIPH_ALG_DES 0x01 95#define SPA_CTRL_CIPH_ALG_AES 0x02 96#define SPA_CTRL_CIPH_ALG_RC4 0x03 97#define SPA_CTRL_CIPH_ALG_MULTI2 0x04 98#define SPA_CTRL_CIPH_ALG_KASUMI 0x05 99 100#define SPA_CTRL_HASH_ALG_NULL (0x00 << SPA_CTRL_HASH_ALG_IDX) 101#define SPA_CTRL_HASH_ALG_MD5 (0x01 << SPA_CTRL_HASH_ALG_IDX) 102#define SPA_CTRL_HASH_ALG_SHA (0x02 << SPA_CTRL_HASH_ALG_IDX) 103#define SPA_CTRL_HASH_ALG_SHA224 (0x03 << SPA_CTRL_HASH_ALG_IDX) 104#define SPA_CTRL_HASH_ALG_SHA256 (0x04 << SPA_CTRL_HASH_ALG_IDX) 105#define SPA_CTRL_HASH_ALG_SHA384 (0x05 << SPA_CTRL_HASH_ALG_IDX) 106#define SPA_CTRL_HASH_ALG_SHA512 (0x06 << SPA_CTRL_HASH_ALG_IDX) 107#define SPA_CTRL_HASH_ALG_AESMAC (0x07 << SPA_CTRL_HASH_ALG_IDX) 108#define SPA_CTRL_HASH_ALG_AESCMAC (0x08 << SPA_CTRL_HASH_ALG_IDX) 109#define SPA_CTRL_HASH_ALG_KASF9 (0x09 << SPA_CTRL_HASH_ALG_IDX) 110 111#define SPA_CTRL_CIPH_MODE_NULL (0x00 << SPA_CTRL_CIPH_MODE_IDX) 112#define SPA_CTRL_CIPH_MODE_ECB (0x00 << SPA_CTRL_CIPH_MODE_IDX) 113#define SPA_CTRL_CIPH_MODE_CBC (0x01 << SPA_CTRL_CIPH_MODE_IDX) 114#define SPA_CTRL_CIPH_MODE_CTR (0x02 << SPA_CTRL_CIPH_MODE_IDX) 115#define SPA_CTRL_CIPH_MODE_CCM (0x03 << SPA_CTRL_CIPH_MODE_IDX) 116#define SPA_CTRL_CIPH_MODE_GCM (0x05 << SPA_CTRL_CIPH_MODE_IDX) 117#define SPA_CTRL_CIPH_MODE_OFB (0x07 << SPA_CTRL_CIPH_MODE_IDX) 118#define SPA_CTRL_CIPH_MODE_CFB (0x08 << SPA_CTRL_CIPH_MODE_IDX) 119#define SPA_CTRL_CIPH_MODE_F8 (0x09 << SPA_CTRL_CIPH_MODE_IDX) 120 121#define SPA_CTRL_HASH_MODE_RAW (0x00 << SPA_CTRL_HASH_MODE_IDX) 122#define SPA_CTRL_HASH_MODE_SSLMAC (0x01 << SPA_CTRL_HASH_MODE_IDX) 123#define SPA_CTRL_HASH_MODE_HMAC (0x02 << SPA_CTRL_HASH_MODE_IDX) 124 125#define SPA_FIFO_STAT_EMPTY (1 << 31) 126#define SPA_FIFO_CMD_FULL (1 << 7) 127 128#endif /* __PICOXCELL_CRYPTO_REGS_H__ */ 129