1/* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36#include <linux/err.h> 37#include <linux/module.h> 38#include <linux/gpio.h> 39#include <linux/irq.h> 40#include <linux/slab.h> 41#include <linux/irqdomain.h> 42#include <linux/io.h> 43#include <linux/of_irq.h> 44#include <linux/of_device.h> 45#include <linux/clk.h> 46#include <linux/pinctrl/consumer.h> 47#include <linux/irqchip/chained_irq.h> 48 49/* 50 * GPIO unit register offsets. 51 */ 52#define GPIO_OUT_OFF 0x0000 53#define GPIO_IO_CONF_OFF 0x0004 54#define GPIO_BLINK_EN_OFF 0x0008 55#define GPIO_IN_POL_OFF 0x000c 56#define GPIO_DATA_IN_OFF 0x0010 57#define GPIO_EDGE_CAUSE_OFF 0x0014 58#define GPIO_EDGE_MASK_OFF 0x0018 59#define GPIO_LEVEL_MASK_OFF 0x001c 60 61/* The MV78200 has per-CPU registers for edge mask and level mask */ 62#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 63#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 64 65/* The Armada XP has per-CPU registers for interrupt cause, interrupt 66 * mask and interrupt level mask. Those are relative to the 67 * percpu_membase. */ 68#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 69#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 70#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 71 72#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 73#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 74#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 75 76#define MVEBU_MAX_GPIO_PER_BANK 32 77 78struct mvebu_gpio_chip { 79 struct gpio_chip chip; 80 spinlock_t lock; 81 void __iomem *membase; 82 void __iomem *percpu_membase; 83 int irqbase; 84 struct irq_domain *domain; 85 int soc_variant; 86}; 87 88/* 89 * Functions returning addresses of individual registers for a given 90 * GPIO controller. 91 */ 92static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) 93{ 94 return mvchip->membase + GPIO_OUT_OFF; 95} 96 97static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) 98{ 99 return mvchip->membase + GPIO_BLINK_EN_OFF; 100} 101 102static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) 103{ 104 return mvchip->membase + GPIO_IO_CONF_OFF; 105} 106 107static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) 108{ 109 return mvchip->membase + GPIO_IN_POL_OFF; 110} 111 112static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) 113{ 114 return mvchip->membase + GPIO_DATA_IN_OFF; 115} 116 117static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) 118{ 119 int cpu; 120 121 switch (mvchip->soc_variant) { 122 case MVEBU_GPIO_SOC_VARIANT_ORION: 123 case MVEBU_GPIO_SOC_VARIANT_MV78200: 124 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; 125 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 126 cpu = smp_processor_id(); 127 return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 128 default: 129 BUG(); 130 } 131} 132 133static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) 134{ 135 int cpu; 136 137 switch (mvchip->soc_variant) { 138 case MVEBU_GPIO_SOC_VARIANT_ORION: 139 return mvchip->membase + GPIO_EDGE_MASK_OFF; 140 case MVEBU_GPIO_SOC_VARIANT_MV78200: 141 cpu = smp_processor_id(); 142 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); 143 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 144 cpu = smp_processor_id(); 145 return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 146 default: 147 BUG(); 148 } 149} 150 151static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) 152{ 153 int cpu; 154 155 switch (mvchip->soc_variant) { 156 case MVEBU_GPIO_SOC_VARIANT_ORION: 157 return mvchip->membase + GPIO_LEVEL_MASK_OFF; 158 case MVEBU_GPIO_SOC_VARIANT_MV78200: 159 cpu = smp_processor_id(); 160 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); 161 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 162 cpu = smp_processor_id(); 163 return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 164 default: 165 BUG(); 166 } 167} 168 169/* 170 * Functions implementing the gpio_chip methods 171 */ 172 173static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin) 174{ 175 return pinctrl_request_gpio(chip->base + pin); 176} 177 178static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin) 179{ 180 pinctrl_free_gpio(chip->base + pin); 181} 182 183static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 184{ 185 struct mvebu_gpio_chip *mvchip = 186 container_of(chip, struct mvebu_gpio_chip, chip); 187 unsigned long flags; 188 u32 u; 189 190 spin_lock_irqsave(&mvchip->lock, flags); 191 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 192 if (value) 193 u |= 1 << pin; 194 else 195 u &= ~(1 << pin); 196 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); 197 spin_unlock_irqrestore(&mvchip->lock, flags); 198} 199 200static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) 201{ 202 struct mvebu_gpio_chip *mvchip = 203 container_of(chip, struct mvebu_gpio_chip, chip); 204 u32 u; 205 206 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { 207 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ 208 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 209 } else { 210 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 211 } 212 213 return (u >> pin) & 1; 214} 215 216static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) 217{ 218 struct mvebu_gpio_chip *mvchip = 219 container_of(chip, struct mvebu_gpio_chip, chip); 220 unsigned long flags; 221 u32 u; 222 223 spin_lock_irqsave(&mvchip->lock, flags); 224 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 225 if (value) 226 u |= 1 << pin; 227 else 228 u &= ~(1 << pin); 229 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); 230 spin_unlock_irqrestore(&mvchip->lock, flags); 231} 232 233static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 234{ 235 struct mvebu_gpio_chip *mvchip = 236 container_of(chip, struct mvebu_gpio_chip, chip); 237 unsigned long flags; 238 int ret; 239 u32 u; 240 241 /* Check with the pinctrl driver whether this pin is usable as 242 * an input GPIO */ 243 ret = pinctrl_gpio_direction_input(chip->base + pin); 244 if (ret) 245 return ret; 246 247 spin_lock_irqsave(&mvchip->lock, flags); 248 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 249 u |= 1 << pin; 250 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 251 spin_unlock_irqrestore(&mvchip->lock, flags); 252 253 return 0; 254} 255 256static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, 257 int value) 258{ 259 struct mvebu_gpio_chip *mvchip = 260 container_of(chip, struct mvebu_gpio_chip, chip); 261 unsigned long flags; 262 int ret; 263 u32 u; 264 265 /* Check with the pinctrl driver whether this pin is usable as 266 * an output GPIO */ 267 ret = pinctrl_gpio_direction_output(chip->base + pin); 268 if (ret) 269 return ret; 270 271 mvebu_gpio_blink(chip, pin, 0); 272 mvebu_gpio_set(chip, pin, value); 273 274 spin_lock_irqsave(&mvchip->lock, flags); 275 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 276 u &= ~(1 << pin); 277 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 278 spin_unlock_irqrestore(&mvchip->lock, flags); 279 280 return 0; 281} 282 283static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 284{ 285 struct mvebu_gpio_chip *mvchip = 286 container_of(chip, struct mvebu_gpio_chip, chip); 287 return irq_create_mapping(mvchip->domain, pin); 288} 289 290/* 291 * Functions implementing the irq_chip methods 292 */ 293static void mvebu_gpio_irq_ack(struct irq_data *d) 294{ 295 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 296 struct mvebu_gpio_chip *mvchip = gc->private; 297 u32 mask = ~(1 << (d->irq - gc->irq_base)); 298 299 irq_gc_lock(gc); 300 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); 301 irq_gc_unlock(gc); 302} 303 304static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 305{ 306 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 307 struct mvebu_gpio_chip *mvchip = gc->private; 308 u32 mask = 1 << (d->irq - gc->irq_base); 309 310 irq_gc_lock(gc); 311 gc->mask_cache &= ~mask; 312 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 313 irq_gc_unlock(gc); 314} 315 316static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 317{ 318 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 319 struct mvebu_gpio_chip *mvchip = gc->private; 320 u32 mask = 1 << (d->irq - gc->irq_base); 321 322 irq_gc_lock(gc); 323 gc->mask_cache |= mask; 324 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 325 irq_gc_unlock(gc); 326} 327 328static void mvebu_gpio_level_irq_mask(struct irq_data *d) 329{ 330 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 331 struct mvebu_gpio_chip *mvchip = gc->private; 332 u32 mask = 1 << (d->irq - gc->irq_base); 333 334 irq_gc_lock(gc); 335 gc->mask_cache &= ~mask; 336 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 337 irq_gc_unlock(gc); 338} 339 340static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 341{ 342 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 343 struct mvebu_gpio_chip *mvchip = gc->private; 344 u32 mask = 1 << (d->irq - gc->irq_base); 345 346 irq_gc_lock(gc); 347 gc->mask_cache |= mask; 348 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 349 irq_gc_unlock(gc); 350} 351 352/***************************************************************************** 353 * MVEBU GPIO IRQ 354 * 355 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 356 * value of the line or the opposite value. 357 * 358 * Level IRQ handlers: DATA_IN is used directly as cause register. 359 * Interrupt are masked by LEVEL_MASK registers. 360 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 361 * Interrupt are masked by EDGE_MASK registers. 362 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 363 * the polarity to catch the next line transaction. 364 * This is a race condition that might not perfectly 365 * work on some use cases. 366 * 367 * Every eight GPIO lines are grouped (OR'ed) before going up to main 368 * cause register. 369 * 370 * EDGE cause mask 371 * data-in /--------| |-----| |----\ 372 * -----| |----- ---- to main cause reg 373 * X \----------------| |----/ 374 * polarity LEVEL mask 375 * 376 ****************************************************************************/ 377 378static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 379{ 380 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 381 struct irq_chip_type *ct = irq_data_get_chip_type(d); 382 struct mvebu_gpio_chip *mvchip = gc->private; 383 int pin; 384 u32 u; 385 386 pin = d->hwirq; 387 388 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); 389 if (!u) { 390 return -EINVAL; 391 } 392 393 type &= IRQ_TYPE_SENSE_MASK; 394 if (type == IRQ_TYPE_NONE) 395 return -EINVAL; 396 397 /* Check if we need to change chip and handler */ 398 if (!(ct->type & type)) 399 if (irq_setup_alt_chip(d, type)) 400 return -EINVAL; 401 402 /* 403 * Configure interrupt polarity. 404 */ 405 switch (type) { 406 case IRQ_TYPE_EDGE_RISING: 407 case IRQ_TYPE_LEVEL_HIGH: 408 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 409 u &= ~(1 << pin); 410 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 411 break; 412 case IRQ_TYPE_EDGE_FALLING: 413 case IRQ_TYPE_LEVEL_LOW: 414 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 415 u |= 1 << pin; 416 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 417 break; 418 case IRQ_TYPE_EDGE_BOTH: { 419 u32 v; 420 421 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ 422 readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 423 424 /* 425 * set initial polarity based on current input level 426 */ 427 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 428 if (v & (1 << pin)) 429 u |= 1 << pin; /* falling */ 430 else 431 u &= ~(1 << pin); /* rising */ 432 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 433 break; 434 } 435 } 436 return 0; 437} 438 439static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 440{ 441 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq); 442 struct irq_chip *chip = irq_desc_get_chip(desc); 443 u32 cause, type; 444 int i; 445 446 if (mvchip == NULL) 447 return; 448 449 chained_irq_enter(chip, desc); 450 451 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & 452 readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 453 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & 454 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 455 456 for (i = 0; i < mvchip->chip.ngpio; i++) { 457 int irq; 458 459 irq = mvchip->irqbase + i; 460 461 if (!(cause & (1 << i))) 462 continue; 463 464 type = irq_get_trigger_type(irq); 465 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 466 /* Swap polarity (race with GPIO line) */ 467 u32 polarity; 468 469 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 470 polarity ^= 1 << i; 471 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); 472 } 473 474 generic_handle_irq(irq); 475 } 476 477 chained_irq_exit(chip, desc); 478} 479 480#ifdef CONFIG_DEBUG_FS 481#include <linux/seq_file.h> 482 483static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 484{ 485 struct mvebu_gpio_chip *mvchip = 486 container_of(chip, struct mvebu_gpio_chip, chip); 487 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 488 int i; 489 490 out = readl_relaxed(mvebu_gpioreg_out(mvchip)); 491 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 492 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 493 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 494 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 495 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); 496 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 497 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 498 499 for (i = 0; i < chip->ngpio; i++) { 500 const char *label; 501 u32 msk; 502 bool is_out; 503 504 label = gpiochip_is_requested(chip, i); 505 if (!label) 506 continue; 507 508 msk = 1 << i; 509 is_out = !(io_conf & msk); 510 511 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 512 513 if (is_out) { 514 seq_printf(s, " out %s %s\n", 515 out & msk ? "hi" : "lo", 516 blink & msk ? "(blink )" : ""); 517 continue; 518 } 519 520 seq_printf(s, " in %s (act %s) - IRQ", 521 (data_in ^ in_pol) & msk ? "hi" : "lo", 522 in_pol & msk ? "lo" : "hi"); 523 if (!((edg_msk | lvl_msk) & msk)) { 524 seq_printf(s, " disabled\n"); 525 continue; 526 } 527 if (edg_msk & msk) 528 seq_printf(s, " edge "); 529 if (lvl_msk & msk) 530 seq_printf(s, " level"); 531 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 532 } 533} 534#else 535#define mvebu_gpio_dbg_show NULL 536#endif 537 538static const struct of_device_id mvebu_gpio_of_match[] = { 539 { 540 .compatible = "marvell,orion-gpio", 541 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 542 }, 543 { 544 .compatible = "marvell,mv78200-gpio", 545 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 546 }, 547 { 548 .compatible = "marvell,armadaxp-gpio", 549 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 550 }, 551 { 552 /* sentinel */ 553 }, 554}; 555MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); 556 557static int mvebu_gpio_probe(struct platform_device *pdev) 558{ 559 struct mvebu_gpio_chip *mvchip; 560 const struct of_device_id *match; 561 struct device_node *np = pdev->dev.of_node; 562 struct resource *res; 563 struct irq_chip_generic *gc; 564 struct irq_chip_type *ct; 565 struct clk *clk; 566 unsigned int ngpios; 567 int soc_variant; 568 int i, cpu, id; 569 570 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 571 if (match) 572 soc_variant = (int) match->data; 573 else 574 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 575 576 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); 577 if (!mvchip) 578 return -ENOMEM; 579 580 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 581 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 582 return -ENODEV; 583 } 584 585 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 586 if (id < 0) { 587 dev_err(&pdev->dev, "Couldn't get OF id\n"); 588 return id; 589 } 590 591 clk = devm_clk_get(&pdev->dev, NULL); 592 /* Not all SoCs require a clock.*/ 593 if (!IS_ERR(clk)) 594 clk_prepare_enable(clk); 595 596 mvchip->soc_variant = soc_variant; 597 mvchip->chip.label = dev_name(&pdev->dev); 598 mvchip->chip.dev = &pdev->dev; 599 mvchip->chip.request = mvebu_gpio_request; 600 mvchip->chip.free = mvebu_gpio_free; 601 mvchip->chip.direction_input = mvebu_gpio_direction_input; 602 mvchip->chip.get = mvebu_gpio_get; 603 mvchip->chip.direction_output = mvebu_gpio_direction_output; 604 mvchip->chip.set = mvebu_gpio_set; 605 mvchip->chip.to_irq = mvebu_gpio_to_irq; 606 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 607 mvchip->chip.ngpio = ngpios; 608 mvchip->chip.can_sleep = false; 609 mvchip->chip.of_node = np; 610 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 611 612 spin_lock_init(&mvchip->lock); 613 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 614 mvchip->membase = devm_ioremap_resource(&pdev->dev, res); 615 if (IS_ERR(mvchip->membase)) 616 return PTR_ERR(mvchip->membase); 617 618 /* The Armada XP has a second range of registers for the 619 * per-CPU registers */ 620 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 621 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 622 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, 623 res); 624 if (IS_ERR(mvchip->percpu_membase)) 625 return PTR_ERR(mvchip->percpu_membase); 626 } 627 628 /* 629 * Mask and clear GPIO interrupts. 630 */ 631 switch (soc_variant) { 632 case MVEBU_GPIO_SOC_VARIANT_ORION: 633 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 634 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 635 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 636 break; 637 case MVEBU_GPIO_SOC_VARIANT_MV78200: 638 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 639 for (cpu = 0; cpu < 2; cpu++) { 640 writel_relaxed(0, mvchip->membase + 641 GPIO_EDGE_MASK_MV78200_OFF(cpu)); 642 writel_relaxed(0, mvchip->membase + 643 GPIO_LEVEL_MASK_MV78200_OFF(cpu)); 644 } 645 break; 646 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 647 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 648 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 649 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 650 for (cpu = 0; cpu < 4; cpu++) { 651 writel_relaxed(0, mvchip->percpu_membase + 652 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); 653 writel_relaxed(0, mvchip->percpu_membase + 654 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); 655 writel_relaxed(0, mvchip->percpu_membase + 656 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); 657 } 658 break; 659 default: 660 BUG(); 661 } 662 663 gpiochip_add(&mvchip->chip); 664 665 /* Some gpio controllers do not provide irq support */ 666 if (!of_irq_count(np)) 667 return 0; 668 669 /* Setup the interrupt handlers. Each chip can have up to 4 670 * interrupt handlers, with each handler dealing with 8 GPIO 671 * pins. */ 672 for (i = 0; i < 4; i++) { 673 int irq; 674 irq = platform_get_irq(pdev, i); 675 if (irq < 0) 676 continue; 677 irq_set_handler_data(irq, mvchip); 678 irq_set_chained_handler(irq, mvebu_gpio_irq_handler); 679 } 680 681 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); 682 if (mvchip->irqbase < 0) { 683 dev_err(&pdev->dev, "no irqs\n"); 684 return mvchip->irqbase; 685 } 686 687 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, 688 mvchip->membase, handle_level_irq); 689 if (!gc) { 690 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); 691 return -ENOMEM; 692 } 693 694 gc->private = mvchip; 695 ct = &gc->chip_types[0]; 696 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 697 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 698 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 699 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 700 ct->chip.name = mvchip->chip.label; 701 702 ct = &gc->chip_types[1]; 703 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 704 ct->chip.irq_ack = mvebu_gpio_irq_ack; 705 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 706 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 707 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 708 ct->handler = handle_edge_irq; 709 ct->chip.name = mvchip->chip.label; 710 711 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, 712 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 713 714 /* Setup irq domain on top of the generic chip. */ 715 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio, 716 mvchip->irqbase, 717 &irq_domain_simple_ops, 718 mvchip); 719 if (!mvchip->domain) { 720 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 721 mvchip->chip.label); 722 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, 723 IRQ_LEVEL | IRQ_NOPROBE); 724 kfree(gc); 725 return -ENODEV; 726 } 727 728 return 0; 729} 730 731static struct platform_driver mvebu_gpio_driver = { 732 .driver = { 733 .name = "mvebu-gpio", 734 .owner = THIS_MODULE, 735 .of_match_table = mvebu_gpio_of_match, 736 }, 737 .probe = mvebu_gpio_probe, 738}; 739module_platform_driver(mvebu_gpio_driver); 740