1/* 2 * TI OMAP I2C master mode driver 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2004 - 2007 Texas Instruments. 7 * 8 * Originally written by MontaVista Software, Inc. 9 * Additional contributions by: 10 * Tony Lindgren <tony@atomide.com> 11 * Imre Deak <imre.deak@nokia.com> 12 * Juha Yrjölä <juha.yrjola@solidboot.com> 13 * Syed Khasim <x0khasim@ti.com> 14 * Nishant Menon <nm@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27#include <linux/module.h> 28#include <linux/delay.h> 29#include <linux/i2c.h> 30#include <linux/err.h> 31#include <linux/interrupt.h> 32#include <linux/completion.h> 33#include <linux/platform_device.h> 34#include <linux/clk.h> 35#include <linux/io.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/slab.h> 39#include <linux/i2c-omap.h> 40#include <linux/pm_runtime.h> 41 42/* I2C controller revisions */ 43#define OMAP_I2C_OMAP1_REV_2 0x20 44 45/* I2C controller revisions present on specific hardware */ 46#define OMAP_I2C_REV_ON_2430 0x00000036 47#define OMAP_I2C_REV_ON_3430_3530 0x0000003C 48#define OMAP_I2C_REV_ON_3630 0x00000040 49#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 50 51/* timeout waiting for the controller to respond */ 52#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 53 54/* timeout for pm runtime autosuspend */ 55#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ 56 57/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 58enum { 59 OMAP_I2C_REV_REG = 0, 60 OMAP_I2C_IE_REG, 61 OMAP_I2C_STAT_REG, 62 OMAP_I2C_IV_REG, 63 OMAP_I2C_WE_REG, 64 OMAP_I2C_SYSS_REG, 65 OMAP_I2C_BUF_REG, 66 OMAP_I2C_CNT_REG, 67 OMAP_I2C_DATA_REG, 68 OMAP_I2C_SYSC_REG, 69 OMAP_I2C_CON_REG, 70 OMAP_I2C_OA_REG, 71 OMAP_I2C_SA_REG, 72 OMAP_I2C_PSC_REG, 73 OMAP_I2C_SCLL_REG, 74 OMAP_I2C_SCLH_REG, 75 OMAP_I2C_SYSTEST_REG, 76 OMAP_I2C_BUFSTAT_REG, 77 /* only on OMAP4430 */ 78 OMAP_I2C_IP_V2_REVNB_LO, 79 OMAP_I2C_IP_V2_REVNB_HI, 80 OMAP_I2C_IP_V2_IRQSTATUS_RAW, 81 OMAP_I2C_IP_V2_IRQENABLE_SET, 82 OMAP_I2C_IP_V2_IRQENABLE_CLR, 83}; 84 85/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 86#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 87#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ 88#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ 89#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ 90#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ 91#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ 92#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ 93 94/* I2C Status Register (OMAP_I2C_STAT): */ 95#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ 96#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ 97#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ 98#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 99#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 100#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ 101#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ 102#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 103#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 104#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ 105#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ 106#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ 107 108/* I2C WE wakeup enable register */ 109#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ 110#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ 111#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ 112#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ 113#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ 114#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ 115#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ 116#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ 117#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ 118#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ 119 120#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ 121 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ 122 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ 123 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ 124 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) 125 126/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ 127#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ 128#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ 129#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ 130#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ 131 132/* I2C Configuration Register (OMAP_I2C_CON): */ 133#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ 134#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ 135#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ 136#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ 137#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ 138#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ 139#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ 140#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ 141#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ 142#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ 143 144/* I2C SCL time value when Master */ 145#define OMAP_I2C_SCLL_HSSCLL 8 146#define OMAP_I2C_SCLH_HSSCLH 8 147 148/* I2C System Test Register (OMAP_I2C_SYSTEST): */ 149#ifdef DEBUG 150#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 151#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ 152#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 153#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 154#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ 155#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ 156#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ 157#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 158#endif 159 160/* OCP_SYSSTATUS bit definitions */ 161#define SYSS_RESETDONE_MASK (1 << 0) 162 163/* OCP_SYSCONFIG bit definitions */ 164#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) 165#define SYSC_SIDLEMODE_MASK (0x3 << 3) 166#define SYSC_ENAWAKEUP_MASK (1 << 2) 167#define SYSC_SOFTRESET_MASK (1 << 1) 168#define SYSC_AUTOIDLE_MASK (1 << 0) 169 170#define SYSC_IDLEMODE_SMART 0x2 171#define SYSC_CLOCKACTIVITY_FCLK 0x2 172 173/* Errata definitions */ 174#define I2C_OMAP_ERRATA_I207 (1 << 0) 175#define I2C_OMAP_ERRATA_I462 (1 << 1) 176 177#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF 178 179struct omap_i2c_dev { 180 spinlock_t lock; /* IRQ synchronization */ 181 struct device *dev; 182 void __iomem *base; /* virtual */ 183 int irq; 184 int reg_shift; /* bit shift for I2C register addresses */ 185 struct completion cmd_complete; 186 struct resource *ioarea; 187 u32 latency; /* maximum mpu wkup latency */ 188 void (*set_mpu_wkup_lat)(struct device *dev, 189 long latency); 190 u32 speed; /* Speed of bus in kHz */ 191 u32 flags; 192 u16 scheme; 193 u16 cmd_err; 194 u8 *buf; 195 u8 *regs; 196 size_t buf_len; 197 struct i2c_adapter adapter; 198 u8 threshold; 199 u8 fifo_size; /* use as flag and value 200 * fifo_size==0 implies no fifo 201 * if set, should be trsh+1 202 */ 203 u32 rev; 204 unsigned b_hw:1; /* bad h/w fixes */ 205 unsigned receiver:1; /* true when we're in receiver mode */ 206 u16 iestate; /* Saved interrupt register */ 207 u16 pscstate; 208 u16 scllstate; 209 u16 sclhstate; 210 u16 syscstate; 211 u16 westate; 212 u16 errata; 213}; 214 215static const u8 reg_map_ip_v1[] = { 216 [OMAP_I2C_REV_REG] = 0x00, 217 [OMAP_I2C_IE_REG] = 0x01, 218 [OMAP_I2C_STAT_REG] = 0x02, 219 [OMAP_I2C_IV_REG] = 0x03, 220 [OMAP_I2C_WE_REG] = 0x03, 221 [OMAP_I2C_SYSS_REG] = 0x04, 222 [OMAP_I2C_BUF_REG] = 0x05, 223 [OMAP_I2C_CNT_REG] = 0x06, 224 [OMAP_I2C_DATA_REG] = 0x07, 225 [OMAP_I2C_SYSC_REG] = 0x08, 226 [OMAP_I2C_CON_REG] = 0x09, 227 [OMAP_I2C_OA_REG] = 0x0a, 228 [OMAP_I2C_SA_REG] = 0x0b, 229 [OMAP_I2C_PSC_REG] = 0x0c, 230 [OMAP_I2C_SCLL_REG] = 0x0d, 231 [OMAP_I2C_SCLH_REG] = 0x0e, 232 [OMAP_I2C_SYSTEST_REG] = 0x0f, 233 [OMAP_I2C_BUFSTAT_REG] = 0x10, 234}; 235 236static const u8 reg_map_ip_v2[] = { 237 [OMAP_I2C_REV_REG] = 0x04, 238 [OMAP_I2C_IE_REG] = 0x2c, 239 [OMAP_I2C_STAT_REG] = 0x28, 240 [OMAP_I2C_IV_REG] = 0x34, 241 [OMAP_I2C_WE_REG] = 0x34, 242 [OMAP_I2C_SYSS_REG] = 0x90, 243 [OMAP_I2C_BUF_REG] = 0x94, 244 [OMAP_I2C_CNT_REG] = 0x98, 245 [OMAP_I2C_DATA_REG] = 0x9c, 246 [OMAP_I2C_SYSC_REG] = 0x10, 247 [OMAP_I2C_CON_REG] = 0xa4, 248 [OMAP_I2C_OA_REG] = 0xa8, 249 [OMAP_I2C_SA_REG] = 0xac, 250 [OMAP_I2C_PSC_REG] = 0xb0, 251 [OMAP_I2C_SCLL_REG] = 0xb4, 252 [OMAP_I2C_SCLH_REG] = 0xb8, 253 [OMAP_I2C_SYSTEST_REG] = 0xbC, 254 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 255 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, 256 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, 257 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, 258 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, 259 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 260}; 261 262static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 263 int reg, u16 val) 264{ 265 writew_relaxed(val, i2c_dev->base + 266 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 267} 268 269static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 270{ 271 return readw_relaxed(i2c_dev->base + 272 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 273} 274 275static void __omap_i2c_init(struct omap_i2c_dev *dev) 276{ 277 278 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 279 280 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ 281 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); 282 283 /* SCL low and high time values */ 284 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); 285 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate); 286 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) 287 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); 288 289 /* Take the I2C module out of reset: */ 290 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 291 292 /* 293 * Don't write to this register if the IE state is 0 as it can 294 * cause deadlock. 295 */ 296 if (dev->iestate) 297 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 298} 299 300static int omap_i2c_reset(struct omap_i2c_dev *dev) 301{ 302 unsigned long timeout; 303 u16 sysc; 304 305 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { 306 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG); 307 308 /* Disable I2C controller before soft reset */ 309 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 310 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & 311 ~(OMAP_I2C_CON_EN)); 312 313 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); 314 /* For some reason we need to set the EN bit before the 315 * reset done bit gets set. */ 316 timeout = jiffies + OMAP_I2C_TIMEOUT; 317 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 318 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 319 SYSS_RESETDONE_MASK)) { 320 if (time_after(jiffies, timeout)) { 321 dev_warn(dev->dev, "timeout waiting " 322 "for controller reset\n"); 323 return -ETIMEDOUT; 324 } 325 msleep(1); 326 } 327 328 /* SYSC register is cleared by the reset; rewrite it */ 329 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc); 330 331 } 332 return 0; 333} 334 335static int omap_i2c_init(struct omap_i2c_dev *dev) 336{ 337 u16 psc = 0, scll = 0, sclh = 0; 338 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; 339 unsigned long fclk_rate = 12000000; 340 unsigned long internal_clk = 0; 341 struct clk *fclk; 342 343 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { 344 /* 345 * Enabling all wakup sources to stop I2C freezing on 346 * WFI instruction. 347 * REVISIT: Some wkup sources might not be needed. 348 */ 349 dev->westate = OMAP_I2C_WE_ALL; 350 } 351 352 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 353 /* 354 * The I2C functional clock is the armxor_ck, so there's 355 * no need to get "armxor_ck" separately. Now, if OMAP2420 356 * always returns 12MHz for the functional clock, we can 357 * do this bit unconditionally. 358 */ 359 fclk = clk_get(dev->dev, "fck"); 360 fclk_rate = clk_get_rate(fclk); 361 clk_put(fclk); 362 363 /* TRM for 5912 says the I2C clock must be prescaled to be 364 * between 7 - 12 MHz. The XOR input clock is typically 365 * 12, 13 or 19.2 MHz. So we should have code that produces: 366 * 367 * XOR MHz Divider Prescaler 368 * 12 1 0 369 * 13 2 1 370 * 19.2 2 1 371 */ 372 if (fclk_rate > 12000000) 373 psc = fclk_rate / 12000000; 374 } 375 376 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 377 378 /* 379 * HSI2C controller internal clk rate should be 19.2 Mhz for 380 * HS and for all modes on 2430. On 34xx we can use lower rate 381 * to get longer filter period for better noise suppression. 382 * The filter is iclk (fclk for HS) period. 383 */ 384 if (dev->speed > 400 || 385 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 386 internal_clk = 19200; 387 else if (dev->speed > 100) 388 internal_clk = 9600; 389 else 390 internal_clk = 4000; 391 fclk = clk_get(dev->dev, "fck"); 392 fclk_rate = clk_get_rate(fclk) / 1000; 393 clk_put(fclk); 394 395 /* Compute prescaler divisor */ 396 psc = fclk_rate / internal_clk; 397 psc = psc - 1; 398 399 /* If configured for High Speed */ 400 if (dev->speed > 400) { 401 unsigned long scl; 402 403 /* For first phase of HS mode */ 404 scl = internal_clk / 400; 405 fsscll = scl - (scl / 3) - 7; 406 fssclh = (scl / 3) - 5; 407 408 /* For second phase of HS mode */ 409 scl = fclk_rate / dev->speed; 410 hsscll = scl - (scl / 3) - 7; 411 hssclh = (scl / 3) - 5; 412 } else if (dev->speed > 100) { 413 unsigned long scl; 414 415 /* Fast mode */ 416 scl = internal_clk / dev->speed; 417 fsscll = scl - (scl / 3) - 7; 418 fssclh = (scl / 3) - 5; 419 } else { 420 /* Standard mode */ 421 fsscll = internal_clk / (dev->speed * 2) - 7; 422 fssclh = internal_clk / (dev->speed * 2) - 5; 423 } 424 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; 425 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; 426 } else { 427 /* Program desired operating rate */ 428 fclk_rate /= (psc + 1) * 1000; 429 if (psc > 2) 430 psc = 2; 431 scll = fclk_rate / (dev->speed * 2) - 7 + psc; 432 sclh = fclk_rate / (dev->speed * 2) - 7 + psc; 433 } 434 435 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 436 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 437 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 438 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 439 440 dev->pscstate = psc; 441 dev->scllstate = scll; 442 dev->sclhstate = sclh; 443 444 __omap_i2c_init(dev); 445 446 return 0; 447} 448 449/* 450 * Waiting on Bus Busy 451 */ 452static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) 453{ 454 unsigned long timeout; 455 456 timeout = jiffies + OMAP_I2C_TIMEOUT; 457 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { 458 if (time_after(jiffies, timeout)) { 459 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 460 return -ETIMEDOUT; 461 } 462 msleep(1); 463 } 464 465 return 0; 466} 467 468static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) 469{ 470 u16 buf; 471 472 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) 473 return; 474 475 /* 476 * Set up notification threshold based on message size. We're doing 477 * this to try and avoid draining feature as much as possible. Whenever 478 * we have big messages to transfer (bigger than our total fifo size) 479 * then we might use draining feature to transfer the remaining bytes. 480 */ 481 482 dev->threshold = clamp(size, (u8) 1, dev->fifo_size); 483 484 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 485 486 if (is_rx) { 487 /* Clear RX Threshold */ 488 buf &= ~(0x3f << 8); 489 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; 490 } else { 491 /* Clear TX Threshold */ 492 buf &= ~0x3f; 493 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; 494 } 495 496 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); 497 498 if (dev->rev < OMAP_I2C_REV_ON_3630) 499 dev->b_hw = 1; /* Enable hardware fixes */ 500 501 /* calculate wakeup latency constraint for MPU */ 502 if (dev->set_mpu_wkup_lat != NULL) 503 dev->latency = (1000000 * dev->threshold) / 504 (1000 * dev->speed / 8); 505} 506 507/* 508 * Low level master read/write transaction. 509 */ 510static int omap_i2c_xfer_msg(struct i2c_adapter *adap, 511 struct i2c_msg *msg, int stop) 512{ 513 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 514 unsigned long timeout; 515 u16 w; 516 517 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 518 msg->addr, msg->len, msg->flags, stop); 519 520 if (msg->len == 0) 521 return -EINVAL; 522 523 dev->receiver = !!(msg->flags & I2C_M_RD); 524 omap_i2c_resize_fifo(dev, msg->len, dev->receiver); 525 526 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); 527 528 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ 529 dev->buf = msg->buf; 530 dev->buf_len = msg->len; 531 532 /* make sure writes to dev->buf_len are ordered */ 533 barrier(); 534 535 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); 536 537 /* Clear the FIFO Buffers */ 538 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 539 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; 540 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); 541 542 reinit_completion(&dev->cmd_complete); 543 dev->cmd_err = 0; 544 545 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 546 547 /* High speed configuration */ 548 if (dev->speed > 400) 549 w |= OMAP_I2C_CON_OPMODE_HS; 550 551 if (msg->flags & I2C_M_STOP) 552 stop = 1; 553 if (msg->flags & I2C_M_TEN) 554 w |= OMAP_I2C_CON_XA; 555 if (!(msg->flags & I2C_M_RD)) 556 w |= OMAP_I2C_CON_TRX; 557 558 if (!dev->b_hw && stop) 559 w |= OMAP_I2C_CON_STP; 560 561 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 562 563 /* 564 * Don't write stt and stp together on some hardware. 565 */ 566 if (dev->b_hw && stop) { 567 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; 568 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 569 while (con & OMAP_I2C_CON_STT) { 570 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 571 572 /* Let the user know if i2c is in a bad state */ 573 if (time_after(jiffies, delay)) { 574 dev_err(dev->dev, "controller timed out " 575 "waiting for start condition to finish\n"); 576 return -ETIMEDOUT; 577 } 578 cpu_relax(); 579 } 580 581 w |= OMAP_I2C_CON_STP; 582 w &= ~OMAP_I2C_CON_STT; 583 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 584 } 585 586 /* 587 * REVISIT: We should abort the transfer on signals, but the bus goes 588 * into arbitration and we're currently unable to recover from it. 589 */ 590 timeout = wait_for_completion_timeout(&dev->cmd_complete, 591 OMAP_I2C_TIMEOUT); 592 if (timeout == 0) { 593 dev_err(dev->dev, "controller timed out\n"); 594 omap_i2c_reset(dev); 595 __omap_i2c_init(dev); 596 return -ETIMEDOUT; 597 } 598 599 if (likely(!dev->cmd_err)) 600 return 0; 601 602 /* We have an error */ 603 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | 604 OMAP_I2C_STAT_XUDF)) { 605 omap_i2c_reset(dev); 606 __omap_i2c_init(dev); 607 return -EIO; 608 } 609 610 if (dev->cmd_err & OMAP_I2C_STAT_NACK) { 611 if (msg->flags & I2C_M_IGNORE_NAK) 612 return 0; 613 614 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 615 w |= OMAP_I2C_CON_STP; 616 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 617 return -EREMOTEIO; 618 } 619 return -EIO; 620} 621 622 623/* 624 * Prepare controller for a transaction and call omap_i2c_xfer_msg 625 * to do the work during IRQ processing. 626 */ 627static int 628omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 629{ 630 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 631 int i; 632 int r; 633 634 r = pm_runtime_get_sync(dev->dev); 635 if (r < 0) 636 goto out; 637 638 r = omap_i2c_wait_for_bb(dev); 639 if (r < 0) 640 goto out; 641 642 if (dev->set_mpu_wkup_lat != NULL) 643 dev->set_mpu_wkup_lat(dev->dev, dev->latency); 644 645 for (i = 0; i < num; i++) { 646 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); 647 if (r != 0) 648 break; 649 } 650 651 if (r == 0) 652 r = num; 653 654 omap_i2c_wait_for_bb(dev); 655 656 if (dev->set_mpu_wkup_lat != NULL) 657 dev->set_mpu_wkup_lat(dev->dev, -1); 658 659out: 660 pm_runtime_mark_last_busy(dev->dev); 661 pm_runtime_put_autosuspend(dev->dev); 662 return r; 663} 664 665static u32 666omap_i2c_func(struct i2c_adapter *adap) 667{ 668 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 669 I2C_FUNC_PROTOCOL_MANGLING; 670} 671 672static inline void 673omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) 674{ 675 dev->cmd_err |= err; 676 complete(&dev->cmd_complete); 677} 678 679static inline void 680omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) 681{ 682 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 683} 684 685static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) 686{ 687 /* 688 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) 689 * Not applicable for OMAP4. 690 * Under certain rare conditions, RDR could be set again 691 * when the bus is busy, then ignore the interrupt and 692 * clear the interrupt. 693 */ 694 if (stat & OMAP_I2C_STAT_RDR) { 695 /* Step 1: If RDR is set, clear it */ 696 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 697 698 /* Step 2: */ 699 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 700 & OMAP_I2C_STAT_BB)) { 701 702 /* Step 3: */ 703 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 704 & OMAP_I2C_STAT_RDR) { 705 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 706 dev_dbg(dev->dev, "RDR when bus is busy.\n"); 707 } 708 709 } 710 } 711} 712 713/* rev1 devices are apparently only on some 15xx */ 714#ifdef CONFIG_ARCH_OMAP15XX 715 716static irqreturn_t 717omap_i2c_omap1_isr(int this_irq, void *dev_id) 718{ 719 struct omap_i2c_dev *dev = dev_id; 720 u16 iv, w; 721 722 if (pm_runtime_suspended(dev->dev)) 723 return IRQ_NONE; 724 725 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); 726 switch (iv) { 727 case 0x00: /* None */ 728 break; 729 case 0x01: /* Arbitration lost */ 730 dev_err(dev->dev, "Arbitration lost\n"); 731 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); 732 break; 733 case 0x02: /* No acknowledgement */ 734 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); 735 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); 736 break; 737 case 0x03: /* Register access ready */ 738 omap_i2c_complete_cmd(dev, 0); 739 break; 740 case 0x04: /* Receive data ready */ 741 if (dev->buf_len) { 742 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 743 *dev->buf++ = w; 744 dev->buf_len--; 745 if (dev->buf_len) { 746 *dev->buf++ = w >> 8; 747 dev->buf_len--; 748 } 749 } else 750 dev_err(dev->dev, "RRDY IRQ while no data requested\n"); 751 break; 752 case 0x05: /* Transmit data ready */ 753 if (dev->buf_len) { 754 w = *dev->buf++; 755 dev->buf_len--; 756 if (dev->buf_len) { 757 w |= *dev->buf++ << 8; 758 dev->buf_len--; 759 } 760 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 761 } else 762 dev_err(dev->dev, "XRDY IRQ while no data to send\n"); 763 break; 764 default: 765 return IRQ_NONE; 766 } 767 768 return IRQ_HANDLED; 769} 770#else 771#define omap_i2c_omap1_isr NULL 772#endif 773 774/* 775 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing 776 * data to DATA_REG. Otherwise some data bytes can be lost while transferring 777 * them from the memory to the I2C interface. 778 */ 779static int errata_omap3_i462(struct omap_i2c_dev *dev) 780{ 781 unsigned long timeout = 10000; 782 u16 stat; 783 784 do { 785 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 786 if (stat & OMAP_I2C_STAT_XUDF) 787 break; 788 789 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { 790 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | 791 OMAP_I2C_STAT_XDR)); 792 if (stat & OMAP_I2C_STAT_NACK) { 793 dev->cmd_err |= OMAP_I2C_STAT_NACK; 794 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 795 } 796 797 if (stat & OMAP_I2C_STAT_AL) { 798 dev_err(dev->dev, "Arbitration lost\n"); 799 dev->cmd_err |= OMAP_I2C_STAT_AL; 800 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); 801 } 802 803 return -EIO; 804 } 805 806 cpu_relax(); 807 } while (--timeout); 808 809 if (!timeout) { 810 dev_err(dev->dev, "timeout waiting on XUDF bit\n"); 811 return 0; 812 } 813 814 return 0; 815} 816 817static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, 818 bool is_rdr) 819{ 820 u16 w; 821 822 while (num_bytes--) { 823 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 824 *dev->buf++ = w; 825 dev->buf_len--; 826 827 /* 828 * Data reg in 2430, omap3 and 829 * omap4 is 8 bit wide 830 */ 831 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 832 *dev->buf++ = w >> 8; 833 dev->buf_len--; 834 } 835 } 836} 837 838static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, 839 bool is_xdr) 840{ 841 u16 w; 842 843 while (num_bytes--) { 844 w = *dev->buf++; 845 dev->buf_len--; 846 847 /* 848 * Data reg in 2430, omap3 and 849 * omap4 is 8 bit wide 850 */ 851 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 852 w |= *dev->buf++ << 8; 853 dev->buf_len--; 854 } 855 856 if (dev->errata & I2C_OMAP_ERRATA_I462) { 857 int ret; 858 859 ret = errata_omap3_i462(dev); 860 if (ret < 0) 861 return ret; 862 } 863 864 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 865 } 866 867 return 0; 868} 869 870static irqreturn_t 871omap_i2c_isr(int irq, void *dev_id) 872{ 873 struct omap_i2c_dev *dev = dev_id; 874 irqreturn_t ret = IRQ_HANDLED; 875 u16 mask; 876 u16 stat; 877 878 spin_lock(&dev->lock); 879 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 880 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 881 882 if (stat & mask) 883 ret = IRQ_WAKE_THREAD; 884 885 spin_unlock(&dev->lock); 886 887 return ret; 888} 889 890static irqreturn_t 891omap_i2c_isr_thread(int this_irq, void *dev_id) 892{ 893 struct omap_i2c_dev *dev = dev_id; 894 unsigned long flags; 895 u16 bits; 896 u16 stat; 897 int err = 0, count = 0; 898 899 spin_lock_irqsave(&dev->lock, flags); 900 do { 901 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 902 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 903 stat &= bits; 904 905 /* If we're in receiver mode, ignore XDR/XRDY */ 906 if (dev->receiver) 907 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); 908 else 909 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); 910 911 if (!stat) { 912 /* my work here is done */ 913 goto out; 914 } 915 916 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); 917 if (count++ == 100) { 918 dev_warn(dev->dev, "Too much work in one IRQ\n"); 919 break; 920 } 921 922 if (stat & OMAP_I2C_STAT_NACK) { 923 err |= OMAP_I2C_STAT_NACK; 924 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 925 } 926 927 if (stat & OMAP_I2C_STAT_AL) { 928 dev_err(dev->dev, "Arbitration lost\n"); 929 err |= OMAP_I2C_STAT_AL; 930 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); 931 } 932 933 /* 934 * ProDB0017052: Clear ARDY bit twice 935 */ 936 if (stat & OMAP_I2C_STAT_ARDY) 937 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY); 938 939 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 940 OMAP_I2C_STAT_AL)) { 941 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | 942 OMAP_I2C_STAT_RDR | 943 OMAP_I2C_STAT_XRDY | 944 OMAP_I2C_STAT_XDR | 945 OMAP_I2C_STAT_ARDY)); 946 break; 947 } 948 949 if (stat & OMAP_I2C_STAT_RDR) { 950 u8 num_bytes = 1; 951 952 if (dev->fifo_size) 953 num_bytes = dev->buf_len; 954 955 if (dev->errata & I2C_OMAP_ERRATA_I207) { 956 i2c_omap_errata_i207(dev, stat); 957 num_bytes = (omap_i2c_read_reg(dev, 958 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F; 959 } 960 961 omap_i2c_receive_data(dev, num_bytes, true); 962 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 963 continue; 964 } 965 966 if (stat & OMAP_I2C_STAT_RRDY) { 967 u8 num_bytes = 1; 968 969 if (dev->threshold) 970 num_bytes = dev->threshold; 971 972 omap_i2c_receive_data(dev, num_bytes, false); 973 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); 974 continue; 975 } 976 977 if (stat & OMAP_I2C_STAT_XDR) { 978 u8 num_bytes = 1; 979 int ret; 980 981 if (dev->fifo_size) 982 num_bytes = dev->buf_len; 983 984 ret = omap_i2c_transmit_data(dev, num_bytes, true); 985 if (ret < 0) 986 break; 987 988 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); 989 continue; 990 } 991 992 if (stat & OMAP_I2C_STAT_XRDY) { 993 u8 num_bytes = 1; 994 int ret; 995 996 if (dev->threshold) 997 num_bytes = dev->threshold; 998 999 ret = omap_i2c_transmit_data(dev, num_bytes, false); 1000 if (ret < 0) 1001 break; 1002 1003 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); 1004 continue; 1005 } 1006 1007 if (stat & OMAP_I2C_STAT_ROVR) { 1008 dev_err(dev->dev, "Receive overrun\n"); 1009 err |= OMAP_I2C_STAT_ROVR; 1010 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); 1011 break; 1012 } 1013 1014 if (stat & OMAP_I2C_STAT_XUDF) { 1015 dev_err(dev->dev, "Transmit underflow\n"); 1016 err |= OMAP_I2C_STAT_XUDF; 1017 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); 1018 break; 1019 } 1020 } while (stat); 1021 1022 omap_i2c_complete_cmd(dev, err); 1023 1024out: 1025 spin_unlock_irqrestore(&dev->lock, flags); 1026 1027 return IRQ_HANDLED; 1028} 1029 1030static const struct i2c_algorithm omap_i2c_algo = { 1031 .master_xfer = omap_i2c_xfer, 1032 .functionality = omap_i2c_func, 1033}; 1034 1035#ifdef CONFIG_OF 1036static struct omap_i2c_bus_platform_data omap2420_pdata = { 1037 .rev = OMAP_I2C_IP_VERSION_1, 1038 .flags = OMAP_I2C_FLAG_NO_FIFO | 1039 OMAP_I2C_FLAG_SIMPLE_CLOCK | 1040 OMAP_I2C_FLAG_16BIT_DATA_REG | 1041 OMAP_I2C_FLAG_BUS_SHIFT_2, 1042}; 1043 1044static struct omap_i2c_bus_platform_data omap2430_pdata = { 1045 .rev = OMAP_I2C_IP_VERSION_1, 1046 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | 1047 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 1048}; 1049 1050static struct omap_i2c_bus_platform_data omap3_pdata = { 1051 .rev = OMAP_I2C_IP_VERSION_1, 1052 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 1053}; 1054 1055static struct omap_i2c_bus_platform_data omap4_pdata = { 1056 .rev = OMAP_I2C_IP_VERSION_2, 1057}; 1058 1059static const struct of_device_id omap_i2c_of_match[] = { 1060 { 1061 .compatible = "ti,omap4-i2c", 1062 .data = &omap4_pdata, 1063 }, 1064 { 1065 .compatible = "ti,omap3-i2c", 1066 .data = &omap3_pdata, 1067 }, 1068 { 1069 .compatible = "ti,omap2430-i2c", 1070 .data = &omap2430_pdata, 1071 }, 1072 { 1073 .compatible = "ti,omap2420-i2c", 1074 .data = &omap2420_pdata, 1075 }, 1076 { }, 1077}; 1078MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 1079#endif 1080 1081#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14) 1082 1083#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4) 1084#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf) 1085 1086#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7) 1087#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f) 1088#define OMAP_I2C_SCHEME_0 0 1089#define OMAP_I2C_SCHEME_1 1 1090 1091static int 1092omap_i2c_probe(struct platform_device *pdev) 1093{ 1094 struct omap_i2c_dev *dev; 1095 struct i2c_adapter *adap; 1096 struct resource *mem; 1097 const struct omap_i2c_bus_platform_data *pdata = 1098 dev_get_platdata(&pdev->dev); 1099 struct device_node *node = pdev->dev.of_node; 1100 const struct of_device_id *match; 1101 int irq; 1102 int r; 1103 u32 rev; 1104 u16 minor, major; 1105 1106 irq = platform_get_irq(pdev, 0); 1107 if (irq < 0) { 1108 dev_err(&pdev->dev, "no irq resource?\n"); 1109 return irq; 1110 } 1111 1112 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); 1113 if (!dev) 1114 return -ENOMEM; 1115 1116 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1117 dev->base = devm_ioremap_resource(&pdev->dev, mem); 1118 if (IS_ERR(dev->base)) 1119 return PTR_ERR(dev->base); 1120 1121 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); 1122 if (match) { 1123 u32 freq = 100000; /* default to 100000 Hz */ 1124 1125 pdata = match->data; 1126 dev->flags = pdata->flags; 1127 1128 of_property_read_u32(node, "clock-frequency", &freq); 1129 /* convert DT freq value in Hz into kHz for speed */ 1130 dev->speed = freq / 1000; 1131 } else if (pdata != NULL) { 1132 dev->speed = pdata->clkrate; 1133 dev->flags = pdata->flags; 1134 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; 1135 } 1136 1137 dev->dev = &pdev->dev; 1138 dev->irq = irq; 1139 1140 spin_lock_init(&dev->lock); 1141 1142 platform_set_drvdata(pdev, dev); 1143 init_completion(&dev->cmd_complete); 1144 1145 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1146 1147 pm_runtime_enable(dev->dev); 1148 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); 1149 pm_runtime_use_autosuspend(dev->dev); 1150 1151 r = pm_runtime_get_sync(dev->dev); 1152 if (r < 0) 1153 goto err_free_mem; 1154 1155 /* 1156 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. 1157 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. 1158 * Also since the omap_i2c_read_reg uses reg_map_ip_* a 1159 * readw_relaxed is done. 1160 */ 1161 rev = readw_relaxed(dev->base + 0x04); 1162 1163 dev->scheme = OMAP_I2C_SCHEME(rev); 1164 switch (dev->scheme) { 1165 case OMAP_I2C_SCHEME_0: 1166 dev->regs = (u8 *)reg_map_ip_v1; 1167 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); 1168 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); 1169 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev); 1170 break; 1171 case OMAP_I2C_SCHEME_1: 1172 /* FALLTHROUGH */ 1173 default: 1174 dev->regs = (u8 *)reg_map_ip_v2; 1175 rev = (rev << 16) | 1176 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO); 1177 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev); 1178 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev); 1179 dev->rev = rev; 1180 } 1181 1182 dev->errata = 0; 1183 1184 if (dev->rev >= OMAP_I2C_REV_ON_2430 && 1185 dev->rev < OMAP_I2C_REV_ON_4430_PLUS) 1186 dev->errata |= I2C_OMAP_ERRATA_I207; 1187 1188 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) 1189 dev->errata |= I2C_OMAP_ERRATA_I462; 1190 1191 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1192 u16 s; 1193 1194 /* Set up the fifo size - Get total size */ 1195 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; 1196 dev->fifo_size = 0x8 << s; 1197 1198 /* 1199 * Set up notification threshold as half the total available 1200 * size. This is to ensure that we can handle the status on int 1201 * call back latencies. 1202 */ 1203 1204 dev->fifo_size = (dev->fifo_size / 2); 1205 1206 if (dev->rev < OMAP_I2C_REV_ON_3630) 1207 dev->b_hw = 1; /* Enable hardware fixes */ 1208 1209 /* calculate wakeup latency constraint for MPU */ 1210 if (dev->set_mpu_wkup_lat != NULL) 1211 dev->latency = (1000000 * dev->fifo_size) / 1212 (1000 * dev->speed / 8); 1213 } 1214 1215 /* reset ASAP, clearing any IRQs */ 1216 omap_i2c_init(dev); 1217 1218 if (dev->rev < OMAP_I2C_OMAP1_REV_2) 1219 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, 1220 IRQF_NO_SUSPEND, pdev->name, dev); 1221 else 1222 r = devm_request_threaded_irq(&pdev->dev, dev->irq, 1223 omap_i2c_isr, omap_i2c_isr_thread, 1224 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1225 pdev->name, dev); 1226 1227 if (r) { 1228 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); 1229 goto err_unuse_clocks; 1230 } 1231 1232 adap = &dev->adapter; 1233 i2c_set_adapdata(adap, dev); 1234 adap->owner = THIS_MODULE; 1235 adap->class = I2C_CLASS_DEPRECATED; 1236 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); 1237 adap->algo = &omap_i2c_algo; 1238 adap->dev.parent = &pdev->dev; 1239 adap->dev.of_node = pdev->dev.of_node; 1240 1241 /* i2c device drivers may be active on return from add_adapter() */ 1242 adap->nr = pdev->id; 1243 r = i2c_add_numbered_adapter(adap); 1244 if (r) { 1245 dev_err(dev->dev, "failure adding adapter\n"); 1246 goto err_unuse_clocks; 1247 } 1248 1249 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, 1250 major, minor, dev->speed); 1251 1252 pm_runtime_mark_last_busy(dev->dev); 1253 pm_runtime_put_autosuspend(dev->dev); 1254 1255 return 0; 1256 1257err_unuse_clocks: 1258 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1259 pm_runtime_put(dev->dev); 1260 pm_runtime_disable(&pdev->dev); 1261err_free_mem: 1262 1263 return r; 1264} 1265 1266static int omap_i2c_remove(struct platform_device *pdev) 1267{ 1268 struct omap_i2c_dev *dev = platform_get_drvdata(pdev); 1269 int ret; 1270 1271 i2c_del_adapter(&dev->adapter); 1272 ret = pm_runtime_get_sync(&pdev->dev); 1273 if (ret < 0) 1274 return ret; 1275 1276 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1277 pm_runtime_put(&pdev->dev); 1278 pm_runtime_disable(&pdev->dev); 1279 return 0; 1280} 1281 1282#ifdef CONFIG_PM 1283#ifdef CONFIG_PM_RUNTIME 1284static int omap_i2c_runtime_suspend(struct device *dev) 1285{ 1286 struct platform_device *pdev = to_platform_device(dev); 1287 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1288 1289 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); 1290 1291 if (_dev->scheme == OMAP_I2C_SCHEME_0) 1292 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); 1293 else 1294 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1295 OMAP_I2C_IP_V2_INTERRUPTS_MASK); 1296 1297 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { 1298 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ 1299 } else { 1300 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); 1301 1302 /* Flush posted write */ 1303 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); 1304 } 1305 1306 return 0; 1307} 1308 1309static int omap_i2c_runtime_resume(struct device *dev) 1310{ 1311 struct platform_device *pdev = to_platform_device(dev); 1312 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1313 1314 if (!_dev->regs) 1315 return 0; 1316 1317 __omap_i2c_init(_dev); 1318 1319 return 0; 1320} 1321#endif /* CONFIG_PM_RUNTIME */ 1322 1323static struct dev_pm_ops omap_i2c_pm_ops = { 1324 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, 1325 omap_i2c_runtime_resume, NULL) 1326}; 1327#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) 1328#else 1329#define OMAP_I2C_PM_OPS NULL 1330#endif /* CONFIG_PM */ 1331 1332static struct platform_driver omap_i2c_driver = { 1333 .probe = omap_i2c_probe, 1334 .remove = omap_i2c_remove, 1335 .driver = { 1336 .name = "omap_i2c", 1337 .owner = THIS_MODULE, 1338 .pm = OMAP_I2C_PM_OPS, 1339 .of_match_table = of_match_ptr(omap_i2c_of_match), 1340 }, 1341}; 1342 1343/* I2C may be needed to bring up other drivers */ 1344static int __init 1345omap_i2c_init_driver(void) 1346{ 1347 return platform_driver_register(&omap_i2c_driver); 1348} 1349subsys_initcall(omap_i2c_init_driver); 1350 1351static void __exit omap_i2c_exit_driver(void) 1352{ 1353 platform_driver_unregister(&omap_i2c_driver); 1354} 1355module_exit(omap_i2c_exit_driver); 1356 1357MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); 1358MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); 1359MODULE_LICENSE("GPL"); 1360MODULE_ALIAS("platform:omap_i2c"); 1361