1/* 2 * isp.h 3 * 4 * TI OMAP3 ISP - Core 5 * 6 * Copyright (C) 2009-2010 Nokia Corporation 7 * Copyright (C) 2009 Texas Instruments, Inc. 8 * 9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 * Sakari Ailus <sakari.ailus@iki.fi> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#ifndef OMAP3_ISP_CORE_H 18#define OMAP3_ISP_CORE_H 19 20#include <media/omap3isp.h> 21#include <media/v4l2-device.h> 22#include <linux/clk-provider.h> 23#include <linux/device.h> 24#include <linux/io.h> 25#include <linux/iommu.h> 26#include <linux/platform_device.h> 27#include <linux/wait.h> 28 29#include "ispstat.h" 30#include "ispccdc.h" 31#include "ispreg.h" 32#include "ispresizer.h" 33#include "isppreview.h" 34#include "ispcsiphy.h" 35#include "ispcsi2.h" 36#include "ispccp2.h" 37 38#define ISP_TOK_TERM 0xFFFFFFFF /* 39 * terminating token for ISP 40 * modules reg list 41 */ 42#define to_isp_device(ptr_module) \ 43 container_of(ptr_module, struct isp_device, isp_##ptr_module) 44#define to_device(ptr_module) \ 45 (to_isp_device(ptr_module)->dev) 46 47enum isp_mem_resources { 48 OMAP3_ISP_IOMEM_MAIN, 49 OMAP3_ISP_IOMEM_CCP2, 50 OMAP3_ISP_IOMEM_CCDC, 51 OMAP3_ISP_IOMEM_HIST, 52 OMAP3_ISP_IOMEM_H3A, 53 OMAP3_ISP_IOMEM_PREV, 54 OMAP3_ISP_IOMEM_RESZ, 55 OMAP3_ISP_IOMEM_SBL, 56 OMAP3_ISP_IOMEM_CSI2A_REGS1, 57 OMAP3_ISP_IOMEM_CSIPHY2, 58 OMAP3_ISP_IOMEM_CSI2A_REGS2, 59 OMAP3_ISP_IOMEM_CSI2C_REGS1, 60 OMAP3_ISP_IOMEM_CSIPHY1, 61 OMAP3_ISP_IOMEM_CSI2C_REGS2, 62 OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE, 63 OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL, 64 OMAP3_ISP_IOMEM_LAST 65}; 66 67enum isp_sbl_resource { 68 OMAP3_ISP_SBL_CSI1_READ = 0x1, 69 OMAP3_ISP_SBL_CSI1_WRITE = 0x2, 70 OMAP3_ISP_SBL_CSI2A_WRITE = 0x4, 71 OMAP3_ISP_SBL_CSI2C_WRITE = 0x8, 72 OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10, 73 OMAP3_ISP_SBL_CCDC_WRITE = 0x20, 74 OMAP3_ISP_SBL_PREVIEW_READ = 0x40, 75 OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80, 76 OMAP3_ISP_SBL_RESIZER_READ = 0x100, 77 OMAP3_ISP_SBL_RESIZER_WRITE = 0x200, 78}; 79 80enum isp_subclk_resource { 81 OMAP3_ISP_SUBCLK_CCDC = (1 << 0), 82 OMAP3_ISP_SUBCLK_AEWB = (1 << 1), 83 OMAP3_ISP_SUBCLK_AF = (1 << 2), 84 OMAP3_ISP_SUBCLK_HIST = (1 << 3), 85 OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4), 86 OMAP3_ISP_SUBCLK_RESIZER = (1 << 5), 87}; 88 89/* ISP: OMAP 34xx ES 1.0 */ 90#define ISP_REVISION_1_0 0x10 91/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */ 92#define ISP_REVISION_2_0 0x20 93/* ISP2P: OMAP 36xx */ 94#define ISP_REVISION_15_0 0xF0 95 96/* 97 * struct isp_res_mapping - Map ISP io resources to ISP revision. 98 * @isp_rev: ISP_REVISION_x_x 99 * @map: bitmap for enum isp_mem_resources 100 */ 101struct isp_res_mapping { 102 u32 isp_rev; 103 u32 map; 104}; 105 106/* 107 * struct isp_reg - Structure for ISP register values. 108 * @reg: 32-bit Register address. 109 * @val: 32-bit Register value. 110 */ 111struct isp_reg { 112 enum isp_mem_resources mmio_range; 113 u32 reg; 114 u32 val; 115}; 116 117enum isp_xclk_id { 118 ISP_XCLK_A, 119 ISP_XCLK_B, 120}; 121 122struct isp_xclk { 123 struct isp_device *isp; 124 struct clk_hw hw; 125 struct clk_lookup *lookup; 126 struct clk *clk; 127 enum isp_xclk_id id; 128 129 spinlock_t lock; /* Protects enabled and divider */ 130 bool enabled; 131 unsigned int divider; 132}; 133 134/* 135 * struct isp_device - ISP device structure. 136 * @dev: Device pointer specific to the OMAP3 ISP. 137 * @revision: Stores current ISP module revision. 138 * @irq_num: Currently used IRQ number. 139 * @mmio_base: Array with kernel base addresses for ioremapped ISP register 140 * regions. 141 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register 142 * regions. 143 * @mapping: IOMMU mapping 144 * @stat_lock: Spinlock for handling statistics 145 * @isp_mutex: Mutex for serializing requests to ISP. 146 * @stop_failure: Indicates that an entity failed to stop. 147 * @crashed: Bitmask of crashed entities (indexed by entity ID) 148 * @has_context: Context has been saved at least once and can be restored. 149 * @ref_count: Reference count for handling multiple ISP requests. 150 * @cam_ick: Pointer to camera interface clock structure. 151 * @cam_mclk: Pointer to camera functional clock structure. 152 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. 153 * @l3_ick: Pointer to OMAP3 L3 bus interface clock. 154 * @xclks: External clocks provided by the ISP 155 * @irq: Currently attached ISP ISR callbacks information structure. 156 * @isp_af: Pointer to current settings for ISP AutoFocus SCM. 157 * @isp_hist: Pointer to current settings for ISP Histogram SCM. 158 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and 159 * White Balance SCM. 160 * @isp_res: Pointer to current settings for ISP Resizer. 161 * @isp_prev: Pointer to current settings for ISP Preview. 162 * @isp_ccdc: Pointer to current settings for ISP CCDC. 163 * @platform_cb: ISP driver callback function pointers for platform code 164 * 165 * This structure is used to store the OMAP ISP Information. 166 */ 167struct isp_device { 168 struct v4l2_device v4l2_dev; 169 struct media_device media_dev; 170 struct device *dev; 171 u32 revision; 172 173 /* platform HW resources */ 174 struct isp_platform_data *pdata; 175 unsigned int irq_num; 176 177 void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST]; 178 unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST]; 179 180 struct dma_iommu_mapping *mapping; 181 182 /* ISP Obj */ 183 spinlock_t stat_lock; /* common lock for statistic drivers */ 184 struct mutex isp_mutex; /* For handling ref_count field */ 185 bool stop_failure; 186 u32 crashed; 187 int has_context; 188 int ref_count; 189 unsigned int autoidle; 190#define ISP_CLK_CAM_ICK 0 191#define ISP_CLK_CAM_MCLK 1 192#define ISP_CLK_CSI2_FCK 2 193#define ISP_CLK_L3_ICK 3 194 struct clk *clock[4]; 195 struct isp_xclk xclks[2]; 196 197 /* ISP modules */ 198 struct ispstat isp_af; 199 struct ispstat isp_aewb; 200 struct ispstat isp_hist; 201 struct isp_res_device isp_res; 202 struct isp_prev_device isp_prev; 203 struct isp_ccdc_device isp_ccdc; 204 struct isp_csi2_device isp_csi2a; 205 struct isp_csi2_device isp_csi2c; 206 struct isp_ccp2_device isp_ccp2; 207 struct isp_csiphy isp_csiphy1; 208 struct isp_csiphy isp_csiphy2; 209 210 unsigned int sbl_resources; 211 unsigned int subclk_resources; 212}; 213 214#define v4l2_dev_to_isp_device(dev) \ 215 container_of(dev, struct isp_device, v4l2_dev) 216 217void omap3isp_hist_dma_done(struct isp_device *isp); 218 219void omap3isp_flush(struct isp_device *isp); 220 221int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, 222 atomic_t *stopping); 223 224int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait, 225 atomic_t *stopping); 226 227int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe, 228 enum isp_pipeline_stream_state state); 229void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe); 230void omap3isp_configure_bridge(struct isp_device *isp, 231 enum ccdc_input_entity input, 232 const struct isp_parallel_platform_data *pdata, 233 unsigned int shift, unsigned int bridge); 234 235struct isp_device *omap3isp_get(struct isp_device *isp); 236void omap3isp_put(struct isp_device *isp); 237 238void omap3isp_print_status(struct isp_device *isp); 239 240void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res); 241void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res); 242 243void omap3isp_subclk_enable(struct isp_device *isp, 244 enum isp_subclk_resource res); 245void omap3isp_subclk_disable(struct isp_device *isp, 246 enum isp_subclk_resource res); 247 248int omap3isp_pipeline_pm_use(struct media_entity *entity, int use); 249 250int omap3isp_register_entities(struct platform_device *pdev, 251 struct v4l2_device *v4l2_dev); 252void omap3isp_unregister_entities(struct platform_device *pdev); 253 254/* 255 * isp_reg_readl - Read value of an OMAP3 ISP register 256 * @isp: Device pointer specific to the OMAP3 ISP. 257 * @isp_mmio_range: Range to which the register offset refers to. 258 * @reg_offset: Register offset to read from. 259 * 260 * Returns an unsigned 32 bit value with the required register contents. 261 */ 262static inline 263u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range, 264 u32 reg_offset) 265{ 266 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); 267} 268 269/* 270 * isp_reg_writel - Write value to an OMAP3 ISP register 271 * @isp: Device pointer specific to the OMAP3 ISP. 272 * @reg_value: 32 bit value to write to the register. 273 * @isp_mmio_range: Range to which the register offset refers to. 274 * @reg_offset: Register offset to write into. 275 */ 276static inline 277void isp_reg_writel(struct isp_device *isp, u32 reg_value, 278 enum isp_mem_resources isp_mmio_range, u32 reg_offset) 279{ 280 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); 281} 282 283/* 284 * isp_reg_clr - Clear individual bits in an OMAP3 ISP register 285 * @isp: Device pointer specific to the OMAP3 ISP. 286 * @mmio_range: Range to which the register offset refers to. 287 * @reg: Register offset to work on. 288 * @clr_bits: 32 bit value which would be cleared in the register. 289 */ 290static inline 291void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range, 292 u32 reg, u32 clr_bits) 293{ 294 u32 v = isp_reg_readl(isp, mmio_range, reg); 295 296 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg); 297} 298 299/* 300 * isp_reg_set - Set individual bits in an OMAP3 ISP register 301 * @isp: Device pointer specific to the OMAP3 ISP. 302 * @mmio_range: Range to which the register offset refers to. 303 * @reg: Register offset to work on. 304 * @set_bits: 32 bit value which would be set in the register. 305 */ 306static inline 307void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, 308 u32 reg, u32 set_bits) 309{ 310 u32 v = isp_reg_readl(isp, mmio_range, reg); 311 312 isp_reg_writel(isp, v | set_bits, mmio_range, reg); 313} 314 315/* 316 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register 317 * @isp: Device pointer specific to the OMAP3 ISP. 318 * @mmio_range: Range to which the register offset refers to. 319 * @reg: Register offset to work on. 320 * @clr_bits: 32 bit value which would be cleared in the register. 321 * @set_bits: 32 bit value which would be set in the register. 322 * 323 * The clear operation is done first, and then the set operation. 324 */ 325static inline 326void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range, 327 u32 reg, u32 clr_bits, u32 set_bits) 328{ 329 u32 v = isp_reg_readl(isp, mmio_range, reg); 330 331 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); 332} 333 334static inline enum v4l2_buf_type 335isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad) 336{ 337 if (pad >= subdev->entity.num_pads) 338 return 0; 339 340 if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK) 341 return V4L2_BUF_TYPE_VIDEO_OUTPUT; 342 else 343 return V4L2_BUF_TYPE_VIDEO_CAPTURE; 344} 345 346#endif /* OMAP3_ISP_CORE_H */ 347