1/* 2 * Tegra30 Memory Controller 3 * 4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 */ 19 20#include <linux/err.h> 21#include <linux/kernel.h> 22#include <linux/module.h> 23#include <linux/ratelimit.h> 24#include <linux/platform_device.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27 28#define DRV_NAME "tegra30-mc" 29 30#define MC_INTSTATUS 0x0 31#define MC_INTMASK 0x4 32 33#define MC_INT_ERR_SHIFT 6 34#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT) 35#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT) 36#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2) 37#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3) 38#define MC_INT_INVALID_SMMU_PAGE BIT(MC_INT_ERR_SHIFT + 4) 39 40#define MC_ERR_STATUS 0x8 41#define MC_ERR_ADR 0xc 42 43#define MC_ERR_TYPE_SHIFT 28 44#define MC_ERR_TYPE_MASK (7 << MC_ERR_TYPE_SHIFT) 45#define MC_ERR_TYPE_DECERR_EMEM 2 46#define MC_ERR_TYPE_SECURITY_TRUSTZONE 3 47#define MC_ERR_TYPE_SECURITY_CARVEOUT 4 48#define MC_ERR_TYPE_INVALID_SMMU_PAGE 6 49 50#define MC_ERR_INVALID_SMMU_PAGE_SHIFT 25 51#define MC_ERR_INVALID_SMMU_PAGE_MASK (7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT) 52#define MC_ERR_RW_SHIFT 16 53#define MC_ERR_RW BIT(MC_ERR_RW_SHIFT) 54#define MC_ERR_SECURITY BIT(MC_ERR_RW_SHIFT + 1) 55 56#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */ 57 58#define MC_EMEM_ARB_CFG 0x90 59#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 60#define MC_EMEM_ARB_TIMING_RCD 0x98 61#define MC_EMEM_ARB_TIMING_RP 0x9c 62#define MC_EMEM_ARB_TIMING_RC 0xa0 63#define MC_EMEM_ARB_TIMING_RAS 0xa4 64#define MC_EMEM_ARB_TIMING_FAW 0xa8 65#define MC_EMEM_ARB_TIMING_RRD 0xac 66#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 67#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 68#define MC_EMEM_ARB_TIMING_R2R 0xb8 69#define MC_EMEM_ARB_TIMING_W2W 0xbc 70#define MC_EMEM_ARB_TIMING_R2W 0xc0 71#define MC_EMEM_ARB_TIMING_W2R 0xc4 72 73#define MC_EMEM_ARB_DA_TURNS 0xd0 74#define MC_EMEM_ARB_DA_COVERS 0xd4 75#define MC_EMEM_ARB_MISC0 0xd8 76#define MC_EMEM_ARB_MISC1 0xdc 77 78#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 79#define MC_EMEM_ARB_OVERRIDE 0xe8 80 81#define MC_TIMING_CONTROL 0xfc 82 83#define MC_CLIENT_ID_MASK 0x7f 84 85#define NUM_MC_REG_BANKS 4 86 87struct tegra30_mc { 88 void __iomem *regs[NUM_MC_REG_BANKS]; 89 struct device *dev; 90 u32 ctx[0]; 91}; 92 93static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs) 94{ 95 u32 val = 0; 96 97 if (offs < 0x10) 98 val = readl(mc->regs[0] + offs); 99 else if (offs < 0x1f0) 100 val = readl(mc->regs[1] + offs - 0x3c); 101 else if (offs < 0x228) 102 val = readl(mc->regs[2] + offs - 0x200); 103 else if (offs < 0x400) 104 val = readl(mc->regs[3] + offs - 0x284); 105 106 return val; 107} 108 109static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs) 110{ 111 if (offs < 0x10) 112 writel(val, mc->regs[0] + offs); 113 else if (offs < 0x1f0) 114 writel(val, mc->regs[1] + offs - 0x3c); 115 else if (offs < 0x228) 116 writel(val, mc->regs[2] + offs - 0x200); 117 else if (offs < 0x400) 118 writel(val, mc->regs[3] + offs - 0x284); 119} 120 121static const char * const tegra30_mc_client[] = { 122 "csr_ptcr", 123 "cbr_display0a", 124 "cbr_display0ab", 125 "cbr_display0b", 126 "cbr_display0bb", 127 "cbr_display0c", 128 "cbr_display0cb", 129 "cbr_display1b", 130 "cbr_display1bb", 131 "cbr_eppup", 132 "cbr_g2pr", 133 "cbr_g2sr", 134 "cbr_mpeunifbr", 135 "cbr_viruv", 136 "csr_afir", 137 "csr_avpcarm7r", 138 "csr_displayhc", 139 "csr_displayhcb", 140 "csr_fdcdrd", 141 "csr_fdcdrd2", 142 "csr_g2dr", 143 "csr_hdar", 144 "csr_host1xdmar", 145 "csr_host1xr", 146 "csr_idxsrd", 147 "csr_idxsrd2", 148 "csr_mpe_ipred", 149 "csr_mpeamemrd", 150 "csr_mpecsrd", 151 "csr_ppcsahbdmar", 152 "csr_ppcsahbslvr", 153 "csr_satar", 154 "csr_texsrd", 155 "csr_texsrd2", 156 "csr_vdebsevr", 157 "csr_vdember", 158 "csr_vdemcer", 159 "csr_vdetper", 160 "csr_mpcorelpr", 161 "csr_mpcorer", 162 "cbw_eppu", 163 "cbw_eppv", 164 "cbw_eppy", 165 "cbw_mpeunifbw", 166 "cbw_viwsb", 167 "cbw_viwu", 168 "cbw_viwv", 169 "cbw_viwy", 170 "ccw_g2dw", 171 "csw_afiw", 172 "csw_avpcarm7w", 173 "csw_fdcdwr", 174 "csw_fdcdwr2", 175 "csw_hdaw", 176 "csw_host1xw", 177 "csw_ispw", 178 "csw_mpcorelpw", 179 "csw_mpcorew", 180 "csw_mpecswr", 181 "csw_ppcsahbdmaw", 182 "csw_ppcsahbslvw", 183 "csw_sataw", 184 "csw_vdebsevw", 185 "csw_vdedbgw", 186 "csw_vdembew", 187 "csw_vdetpmw", 188}; 189 190static void tegra30_mc_decode(struct tegra30_mc *mc, int n) 191{ 192 u32 err, addr; 193 const char * const mc_int_err[] = { 194 "MC_DECERR", 195 "Unknown", 196 "MC_SECURITY_ERR", 197 "MC_ARBITRATION_EMEM", 198 "MC_SMMU_ERR", 199 }; 200 const char * const err_type[] = { 201 "Unknown", 202 "Unknown", 203 "DECERR_EMEM", 204 "SECURITY_TRUSTZONE", 205 "SECURITY_CARVEOUT", 206 "Unknown", 207 "INVALID_SMMU_PAGE", 208 "Unknown", 209 }; 210 char attr[6]; 211 int cid, perm, type, idx; 212 const char *client = "Unknown"; 213 214 idx = n - MC_INT_ERR_SHIFT; 215 if ((idx < 0) || (idx >= ARRAY_SIZE(mc_int_err)) || (idx == 1)) { 216 dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n", 217 BIT(n)); 218 return; 219 } 220 221 err = mc_readl(mc, MC_ERR_STATUS); 222 223 type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT; 224 perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >> 225 MC_ERR_INVALID_SMMU_PAGE_SHIFT; 226 if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE) 227 sprintf(attr, "%c-%c-%c", 228 (perm & BIT(2)) ? 'R' : '-', 229 (perm & BIT(1)) ? 'W' : '-', 230 (perm & BIT(0)) ? 'S' : '-'); 231 else 232 attr[0] = '\0'; 233 234 cid = err & MC_CLIENT_ID_MASK; 235 if (cid < ARRAY_SIZE(tegra30_mc_client)) 236 client = tegra30_mc_client[cid]; 237 238 addr = mc_readl(mc, MC_ERR_ADR); 239 240 dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n", 241 mc_int_err[idx], err, addr, client, 242 (err & MC_ERR_SECURITY) ? "secure" : "non-secure", 243 (err & MC_ERR_RW) ? "write" : "read", 244 err_type[type], attr); 245} 246 247static const u32 tegra30_mc_ctx[] = { 248 MC_EMEM_ARB_CFG, 249 MC_EMEM_ARB_OUTSTANDING_REQ, 250 MC_EMEM_ARB_TIMING_RCD, 251 MC_EMEM_ARB_TIMING_RP, 252 MC_EMEM_ARB_TIMING_RC, 253 MC_EMEM_ARB_TIMING_RAS, 254 MC_EMEM_ARB_TIMING_FAW, 255 MC_EMEM_ARB_TIMING_RRD, 256 MC_EMEM_ARB_TIMING_RAP2PRE, 257 MC_EMEM_ARB_TIMING_WAP2PRE, 258 MC_EMEM_ARB_TIMING_R2R, 259 MC_EMEM_ARB_TIMING_W2W, 260 MC_EMEM_ARB_TIMING_R2W, 261 MC_EMEM_ARB_TIMING_W2R, 262 MC_EMEM_ARB_DA_TURNS, 263 MC_EMEM_ARB_DA_COVERS, 264 MC_EMEM_ARB_MISC0, 265 MC_EMEM_ARB_MISC1, 266 MC_EMEM_ARB_RING3_THROTTLE, 267 MC_EMEM_ARB_OVERRIDE, 268 MC_INTMASK, 269}; 270 271#ifdef CONFIG_PM 272static int tegra30_mc_suspend(struct device *dev) 273{ 274 int i; 275 struct tegra30_mc *mc = dev_get_drvdata(dev); 276 277 for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++) 278 mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]); 279 return 0; 280} 281 282static int tegra30_mc_resume(struct device *dev) 283{ 284 int i; 285 struct tegra30_mc *mc = dev_get_drvdata(dev); 286 287 for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++) 288 mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]); 289 290 mc_writel(mc, 1, MC_TIMING_CONTROL); 291 /* Read-back to ensure that write reached */ 292 mc_readl(mc, MC_TIMING_CONTROL); 293 return 0; 294} 295#endif 296 297static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm, 298 tegra30_mc_suspend, 299 tegra30_mc_resume, NULL); 300 301static const struct of_device_id tegra30_mc_of_match[] = { 302 { .compatible = "nvidia,tegra30-mc", }, 303 {}, 304}; 305 306static irqreturn_t tegra30_mc_isr(int irq, void *data) 307{ 308 u32 stat, mask, bit; 309 struct tegra30_mc *mc = data; 310 311 stat = mc_readl(mc, MC_INTSTATUS); 312 mask = mc_readl(mc, MC_INTMASK); 313 mask &= stat; 314 if (!mask) 315 return IRQ_NONE; 316 while ((bit = ffs(mask)) != 0) { 317 tegra30_mc_decode(mc, bit - 1); 318 mask &= ~BIT(bit - 1); 319 } 320 321 mc_writel(mc, stat, MC_INTSTATUS); 322 return IRQ_HANDLED; 323} 324 325static int tegra30_mc_probe(struct platform_device *pdev) 326{ 327 struct resource *irq; 328 struct tegra30_mc *mc; 329 size_t bytes; 330 int err, i; 331 u32 intmask; 332 333 bytes = sizeof(*mc) + sizeof(u32) * ARRAY_SIZE(tegra30_mc_ctx); 334 mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL); 335 if (!mc) 336 return -ENOMEM; 337 mc->dev = &pdev->dev; 338 339 for (i = 0; i < ARRAY_SIZE(mc->regs); i++) { 340 struct resource *res; 341 342 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 343 mc->regs[i] = devm_ioremap_resource(&pdev->dev, res); 344 if (IS_ERR(mc->regs[i])) 345 return PTR_ERR(mc->regs[i]); 346 } 347 348 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 349 if (!irq) 350 return -ENODEV; 351 err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr, 352 IRQF_SHARED, dev_name(&pdev->dev), mc); 353 if (err) 354 return -ENODEV; 355 356 platform_set_drvdata(pdev, mc); 357 358 intmask = MC_INT_INVALID_SMMU_PAGE | 359 MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION; 360 mc_writel(mc, intmask, MC_INTMASK); 361 return 0; 362} 363 364static struct platform_driver tegra30_mc_driver = { 365 .probe = tegra30_mc_probe, 366 .driver = { 367 .name = DRV_NAME, 368 .owner = THIS_MODULE, 369 .of_match_table = tegra30_mc_of_match, 370 .pm = &tegra30_mc_pm, 371 }, 372}; 373module_platform_driver(tegra30_mc_driver); 374 375MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>"); 376MODULE_DESCRIPTION("Tegra30 MC driver"); 377MODULE_LICENSE("GPL v2"); 378MODULE_ALIAS("platform:" DRV_NAME); 379