1/* 2 * A driver for the Integrated Circuits ICS932S401 3 * Copyright (C) 2008 IBM 4 * 5 * Author: Darrick J. Wong <darrick.wong@oracle.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#include <linux/module.h> 23#include <linux/jiffies.h> 24#include <linux/i2c.h> 25#include <linux/err.h> 26#include <linux/mutex.h> 27#include <linux/delay.h> 28#include <linux/log2.h> 29#include <linux/slab.h> 30 31/* Addresses to scan */ 32static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END }; 33 34/* ICS932S401 registers */ 35#define ICS932S401_REG_CFG2 0x01 36#define ICS932S401_CFG1_SPREAD 0x01 37#define ICS932S401_REG_CFG7 0x06 38#define ICS932S401_FS_MASK 0x07 39#define ICS932S401_REG_VENDOR_REV 0x07 40#define ICS932S401_VENDOR 1 41#define ICS932S401_VENDOR_MASK 0x0F 42#define ICS932S401_REV 4 43#define ICS932S401_REV_SHIFT 4 44#define ICS932S401_REG_DEVICE 0x09 45#define ICS932S401_DEVICE 11 46#define ICS932S401_REG_CTRL 0x0A 47#define ICS932S401_MN_ENABLED 0x80 48#define ICS932S401_CPU_ALT 0x04 49#define ICS932S401_SRC_ALT 0x08 50#define ICS932S401_REG_CPU_M_CTRL 0x0B 51#define ICS932S401_M_MASK 0x3F 52#define ICS932S401_REG_CPU_N_CTRL 0x0C 53#define ICS932S401_REG_CPU_SPREAD1 0x0D 54#define ICS932S401_REG_CPU_SPREAD2 0x0E 55#define ICS932S401_SPREAD_MASK 0x7FFF 56#define ICS932S401_REG_SRC_M_CTRL 0x0F 57#define ICS932S401_REG_SRC_N_CTRL 0x10 58#define ICS932S401_REG_SRC_SPREAD1 0x11 59#define ICS932S401_REG_SRC_SPREAD2 0x12 60#define ICS932S401_REG_CPU_DIVISOR 0x13 61#define ICS932S401_CPU_DIVISOR_SHIFT 4 62#define ICS932S401_REG_PCISRC_DIVISOR 0x14 63#define ICS932S401_SRC_DIVISOR_MASK 0x0F 64#define ICS932S401_PCI_DIVISOR_SHIFT 4 65 66/* Base clock is 14.318MHz */ 67#define BASE_CLOCK 14318 68 69#define NUM_REGS 21 70#define NUM_MIRRORED_REGS 15 71 72static int regs_to_copy[NUM_MIRRORED_REGS] = { 73 ICS932S401_REG_CFG2, 74 ICS932S401_REG_CFG7, 75 ICS932S401_REG_VENDOR_REV, 76 ICS932S401_REG_DEVICE, 77 ICS932S401_REG_CTRL, 78 ICS932S401_REG_CPU_M_CTRL, 79 ICS932S401_REG_CPU_N_CTRL, 80 ICS932S401_REG_CPU_SPREAD1, 81 ICS932S401_REG_CPU_SPREAD2, 82 ICS932S401_REG_SRC_M_CTRL, 83 ICS932S401_REG_SRC_N_CTRL, 84 ICS932S401_REG_SRC_SPREAD1, 85 ICS932S401_REG_SRC_SPREAD2, 86 ICS932S401_REG_CPU_DIVISOR, 87 ICS932S401_REG_PCISRC_DIVISOR, 88}; 89 90/* How often do we reread sensors values? (In jiffies) */ 91#define SENSOR_REFRESH_INTERVAL (2 * HZ) 92 93/* How often do we reread sensor limit values? (In jiffies) */ 94#define LIMIT_REFRESH_INTERVAL (60 * HZ) 95 96struct ics932s401_data { 97 struct attribute_group attrs; 98 struct mutex lock; 99 char sensors_valid; 100 unsigned long sensors_last_updated; /* In jiffies */ 101 102 u8 regs[NUM_REGS]; 103}; 104 105static int ics932s401_probe(struct i2c_client *client, 106 const struct i2c_device_id *id); 107static int ics932s401_detect(struct i2c_client *client, 108 struct i2c_board_info *info); 109static int ics932s401_remove(struct i2c_client *client); 110 111static const struct i2c_device_id ics932s401_id[] = { 112 { "ics932s401", 0 }, 113 { } 114}; 115MODULE_DEVICE_TABLE(i2c, ics932s401_id); 116 117static struct i2c_driver ics932s401_driver = { 118 .class = I2C_CLASS_HWMON, 119 .driver = { 120 .name = "ics932s401", 121 }, 122 .probe = ics932s401_probe, 123 .remove = ics932s401_remove, 124 .id_table = ics932s401_id, 125 .detect = ics932s401_detect, 126 .address_list = normal_i2c, 127}; 128 129static struct ics932s401_data *ics932s401_update_device(struct device *dev) 130{ 131 struct i2c_client *client = to_i2c_client(dev); 132 struct ics932s401_data *data = i2c_get_clientdata(client); 133 unsigned long local_jiffies = jiffies; 134 int i, temp; 135 136 mutex_lock(&data->lock); 137 if (time_before(local_jiffies, data->sensors_last_updated + 138 SENSOR_REFRESH_INTERVAL) 139 && data->sensors_valid) 140 goto out; 141 142 /* 143 * Each register must be read as a word and then right shifted 8 bits. 144 * Not really sure why this is; setting the "byte count programming" 145 * register to 1 does not fix this problem. 146 */ 147 for (i = 0; i < NUM_MIRRORED_REGS; i++) { 148 temp = i2c_smbus_read_word_data(client, regs_to_copy[i]); 149 data->regs[regs_to_copy[i]] = temp >> 8; 150 } 151 152 data->sensors_last_updated = local_jiffies; 153 data->sensors_valid = 1; 154 155out: 156 mutex_unlock(&data->lock); 157 return data; 158} 159 160static ssize_t show_spread_enabled(struct device *dev, 161 struct device_attribute *devattr, 162 char *buf) 163{ 164 struct ics932s401_data *data = ics932s401_update_device(dev); 165 166 if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD) 167 return sprintf(buf, "1\n"); 168 169 return sprintf(buf, "0\n"); 170} 171 172/* bit to cpu khz map */ 173static const int fs_speeds[] = { 174 266666, 175 133333, 176 200000, 177 166666, 178 333333, 179 100000, 180 400000, 181 0, 182}; 183 184/* clock divisor map */ 185static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16, 186 24, 40, 120}; 187 188/* Calculate CPU frequency from the M/N registers. */ 189static int calculate_cpu_freq(struct ics932s401_data *data) 190{ 191 int m, n, freq; 192 193 m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK; 194 n = data->regs[ICS932S401_REG_CPU_N_CTRL]; 195 196 /* Pull in bits 8 & 9 from the M register */ 197 n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1; 198 n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3; 199 200 freq = BASE_CLOCK * (n + 8) / (m + 2); 201 freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >> 202 ICS932S401_CPU_DIVISOR_SHIFT]; 203 204 return freq; 205} 206 207static ssize_t show_cpu_clock(struct device *dev, 208 struct device_attribute *devattr, 209 char *buf) 210{ 211 struct ics932s401_data *data = ics932s401_update_device(dev); 212 213 return sprintf(buf, "%d\n", calculate_cpu_freq(data)); 214} 215 216static ssize_t show_cpu_clock_sel(struct device *dev, 217 struct device_attribute *devattr, 218 char *buf) 219{ 220 struct ics932s401_data *data = ics932s401_update_device(dev); 221 int freq; 222 223 if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED) 224 freq = calculate_cpu_freq(data); 225 else { 226 /* Freq is neatly wrapped up for us */ 227 int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK; 228 freq = fs_speeds[fid]; 229 if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) { 230 switch (freq) { 231 case 166666: 232 freq = 160000; 233 break; 234 case 333333: 235 freq = 320000; 236 break; 237 } 238 } 239 } 240 241 return sprintf(buf, "%d\n", freq); 242} 243 244/* Calculate SRC frequency from the M/N registers. */ 245static int calculate_src_freq(struct ics932s401_data *data) 246{ 247 int m, n, freq; 248 249 m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK; 250 n = data->regs[ICS932S401_REG_SRC_N_CTRL]; 251 252 /* Pull in bits 8 & 9 from the M register */ 253 n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1; 254 n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3; 255 256 freq = BASE_CLOCK * (n + 8) / (m + 2); 257 freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] & 258 ICS932S401_SRC_DIVISOR_MASK]; 259 260 return freq; 261} 262 263static ssize_t show_src_clock(struct device *dev, 264 struct device_attribute *devattr, 265 char *buf) 266{ 267 struct ics932s401_data *data = ics932s401_update_device(dev); 268 269 return sprintf(buf, "%d\n", calculate_src_freq(data)); 270} 271 272static ssize_t show_src_clock_sel(struct device *dev, 273 struct device_attribute *devattr, 274 char *buf) 275{ 276 struct ics932s401_data *data = ics932s401_update_device(dev); 277 int freq; 278 279 if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED) 280 freq = calculate_src_freq(data); 281 else 282 /* Freq is neatly wrapped up for us */ 283 if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT && 284 data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT) 285 freq = 96000; 286 else 287 freq = 100000; 288 289 return sprintf(buf, "%d\n", freq); 290} 291 292/* Calculate PCI frequency from the SRC M/N registers. */ 293static int calculate_pci_freq(struct ics932s401_data *data) 294{ 295 int m, n, freq; 296 297 m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK; 298 n = data->regs[ICS932S401_REG_SRC_N_CTRL]; 299 300 /* Pull in bits 8 & 9 from the M register */ 301 n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1; 302 n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3; 303 304 freq = BASE_CLOCK * (n + 8) / (m + 2); 305 freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >> 306 ICS932S401_PCI_DIVISOR_SHIFT]; 307 308 return freq; 309} 310 311static ssize_t show_pci_clock(struct device *dev, 312 struct device_attribute *devattr, 313 char *buf) 314{ 315 struct ics932s401_data *data = ics932s401_update_device(dev); 316 317 return sprintf(buf, "%d\n", calculate_pci_freq(data)); 318} 319 320static ssize_t show_pci_clock_sel(struct device *dev, 321 struct device_attribute *devattr, 322 char *buf) 323{ 324 struct ics932s401_data *data = ics932s401_update_device(dev); 325 int freq; 326 327 if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED) 328 freq = calculate_pci_freq(data); 329 else 330 freq = 33333; 331 332 return sprintf(buf, "%d\n", freq); 333} 334 335static ssize_t show_value(struct device *dev, 336 struct device_attribute *devattr, 337 char *buf); 338 339static ssize_t show_spread(struct device *dev, 340 struct device_attribute *devattr, 341 char *buf); 342 343static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL); 344static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL); 345static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL); 346static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL); 347static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL); 348static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL); 349static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL); 350static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL); 351static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL); 352static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL); 353static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL); 354 355static struct attribute *ics932s401_attr[] = 356{ 357 &dev_attr_spread_enabled.attr, 358 &dev_attr_cpu_clock_selection.attr, 359 &dev_attr_cpu_clock.attr, 360 &dev_attr_src_clock_selection.attr, 361 &dev_attr_src_clock.attr, 362 &dev_attr_pci_clock_selection.attr, 363 &dev_attr_pci_clock.attr, 364 &dev_attr_usb_clock.attr, 365 &dev_attr_ref_clock.attr, 366 &dev_attr_cpu_spread.attr, 367 &dev_attr_src_spread.attr, 368 NULL 369}; 370 371static ssize_t show_value(struct device *dev, 372 struct device_attribute *devattr, 373 char *buf) 374{ 375 int x; 376 377 if (devattr == &dev_attr_usb_clock) 378 x = 48000; 379 else if (devattr == &dev_attr_ref_clock) 380 x = BASE_CLOCK; 381 else 382 BUG(); 383 384 return sprintf(buf, "%d\n", x); 385} 386 387static ssize_t show_spread(struct device *dev, 388 struct device_attribute *devattr, 389 char *buf) 390{ 391 struct ics932s401_data *data = ics932s401_update_device(dev); 392 int reg; 393 unsigned long val; 394 395 if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)) 396 return sprintf(buf, "0%%\n"); 397 398 if (devattr == &dev_attr_src_spread) 399 reg = ICS932S401_REG_SRC_SPREAD1; 400 else if (devattr == &dev_attr_cpu_spread) 401 reg = ICS932S401_REG_CPU_SPREAD1; 402 else 403 BUG(); 404 405 val = data->regs[reg] | (data->regs[reg + 1] << 8); 406 val &= ICS932S401_SPREAD_MASK; 407 408 /* Scale 0..2^14 to -0.5. */ 409 val = 500000 * val / 16384; 410 return sprintf(buf, "-0.%lu%%\n", val); 411} 412 413/* Return 0 if detection is successful, -ENODEV otherwise */ 414static int ics932s401_detect(struct i2c_client *client, 415 struct i2c_board_info *info) 416{ 417 struct i2c_adapter *adapter = client->adapter; 418 int vendor, device, revision; 419 420 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 421 return -ENODEV; 422 423 vendor = i2c_smbus_read_word_data(client, ICS932S401_REG_VENDOR_REV); 424 vendor >>= 8; 425 revision = vendor >> ICS932S401_REV_SHIFT; 426 vendor &= ICS932S401_VENDOR_MASK; 427 if (vendor != ICS932S401_VENDOR) 428 return -ENODEV; 429 430 device = i2c_smbus_read_word_data(client, ICS932S401_REG_DEVICE); 431 device >>= 8; 432 if (device != ICS932S401_DEVICE) 433 return -ENODEV; 434 435 if (revision != ICS932S401_REV) 436 dev_info(&adapter->dev, "Unknown revision %d\n", revision); 437 438 strlcpy(info->type, "ics932s401", I2C_NAME_SIZE); 439 440 return 0; 441} 442 443static int ics932s401_probe(struct i2c_client *client, 444 const struct i2c_device_id *id) 445{ 446 struct ics932s401_data *data; 447 int err; 448 449 data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL); 450 if (!data) { 451 err = -ENOMEM; 452 goto exit; 453 } 454 455 i2c_set_clientdata(client, data); 456 mutex_init(&data->lock); 457 458 dev_info(&client->dev, "%s chip found\n", client->name); 459 460 /* Register sysfs hooks */ 461 data->attrs.attrs = ics932s401_attr; 462 err = sysfs_create_group(&client->dev.kobj, &data->attrs); 463 if (err) 464 goto exit_free; 465 466 return 0; 467 468exit_free: 469 kfree(data); 470exit: 471 return err; 472} 473 474static int ics932s401_remove(struct i2c_client *client) 475{ 476 struct ics932s401_data *data = i2c_get_clientdata(client); 477 478 sysfs_remove_group(&client->dev.kobj, &data->attrs); 479 kfree(data); 480 return 0; 481} 482 483module_i2c_driver(ics932s401_driver); 484 485MODULE_AUTHOR("Darrick J. Wong <darrick.wong@oracle.com>"); 486MODULE_DESCRIPTION("ICS932S401 driver"); 487MODULE_LICENSE("GPL"); 488 489/* IBM IntelliStation Z30 */ 490MODULE_ALIAS("dmi:bvnIBM:*:rn9228:*"); 491MODULE_ALIAS("dmi:bvnIBM:*:rn9232:*"); 492 493/* IBM x3650/x3550 */ 494MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650*"); 495MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550*"); 496