altera_tse.h revision bbd2190ce96d8fce031f0526c1f970b68adc9d1a
1bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* Altera Triple-Speed Ethernet MAC driver 2bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 3bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * 4bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Contributors: 5bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Dalon Westergreen 6bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Thomas Chou 7bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Ian Abbott 8bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Yuriy Kozlov 9bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Tobias Klauser 10bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Andriy Smolskyy 11bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Roman Bulgakov 12bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Dmytro Mytarchuk 13bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Matthew Gerlach 14bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * 15bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Original driver contributed by SLS. 16bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Major updates contributed by GlobalLogic 17bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * 18bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * This program is free software; you can redistribute it and/or modify it 19bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * under the terms and conditions of the GNU General Public License, 20bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * version 2, as published by the Free Software Foundation. 21bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * 22bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * This program is distributed in the hope it will be useful, but WITHOUT 23bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * more details. 26bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * 27bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * You should have received a copy of the GNU General Public License along with 28bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * this program. If not, see <http://www.gnu.org/licenses/>. 29bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 30bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 31bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#ifndef __ALTERA_TSE_H__ 32bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define __ALTERA_TSE_H__ 33bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 34bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_RESOURCE_NAME "altera_tse" 35bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 36bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#include <linux/bitops.h> 37bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#include <linux/if_vlan.h> 38bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#include <linux/list.h> 39bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#include <linux/netdevice.h> 40bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#include <linux/phy.h> 41bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 42bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000 43bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in 44bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * bytes 45bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 46bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* Rx FIFO default settings */ 47bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_RX_SECTION_EMPTY 16 48bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_RX_SECTION_FULL 0 49bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_RX_ALMOST_EMPTY 8 50bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_RX_ALMOST_FULL 8 51bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 52bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* Tx FIFO default settings */ 53bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_SECTION_EMPTY 16 54bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_SECTION_FULL 0 55bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_ALMOST_EMPTY 8 56bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_ALMOST_FULL 3 57bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 58bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* MAC function configuration default settings */ 59bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_IPG_LENGTH 12 60bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 61bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) 62bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 63bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* MAC Command_Config Register Bit Definitions 64bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 65bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_TX_ENA BIT(0) 66bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_RX_ENA BIT(1) 67bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_XON_GEN BIT(2) 68bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_ETH_SPEED BIT(3) 69bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PROMIS_EN BIT(4) 70bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PAD_EN BIT(5) 71bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_CRC_FWD BIT(6) 72bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PAUSE_FWD BIT(7) 73bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PAUSE_IGNORE BIT(8) 74bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_TX_ADDR_INS BIT(9) 75bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_HD_ENA BIT(10) 76bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_EXCESS_COL BIT(11) 77bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_LATE_COL BIT(12) 78bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_SW_RESET BIT(13) 79bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_MHASH_SEL BIT(14) 80bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_LOOP_ENA BIT(15) 81bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) 82bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_MAGIC_ENA BIT(19) 83bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_SLEEP BIT(20) 84bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_WAKEUP BIT(21) 85bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_XOFF_GEN BIT(22) 86bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_CNTL_FRM_ENA BIT(23) 87bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_NO_LGTH_CHECK BIT(24) 88bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_ENA_10 BIT(25) 89bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_RX_ERR_DISC BIT(26) 90bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27) 91bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_CNT_RESET BIT(31) 92bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 93bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) 94bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) 95bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) 96bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) 97bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) 98bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) 99bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) 100bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7) 101bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8) 102bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9) 103bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10) 104bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11) 105bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12) 106bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13) 107bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14) 108bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15) 109bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7) 110bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19) 111bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20) 112bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21) 113bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22) 114bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23) 115bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24) 116bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25) 117bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26) 118bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27) 119bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31) 120bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 121bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* MDIO registers within MAC register Space 122bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 123bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersstruct altera_tse_mdio { 124bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 control; /* PHY device operation control register */ 125bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 status; /* PHY device operation status register */ 126bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 phy_id1; /* Bits 31:16 of PHY identifier */ 127bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 phy_id2; /* Bits 15:0 of PHY identifier */ 128bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 auto_negotiation_advertisement; /* Auto-negotiation 129bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * advertisement 130bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * register 131bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 132bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 remote_partner_base_page_ability; 133bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 134bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg6; 135bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg7; 136bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg8; 137bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg9; 138bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rega; 139bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 regb; 140bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 regc; 141bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 regd; 142bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rege; 143bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 regf; 144bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg10; 145bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg11; 146bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg12; 147bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg13; 148bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg14; 149bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg15; 150bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg16; 151bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg17; 152bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg18; 153bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg19; 154bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg1a; 155bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg1b; 156bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg1c; 157bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg1d; 158bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg1e; 159bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reg1f; 160bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers}; 161bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 162bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* MAC register Space. Note that some of these registers may or may not be 163bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * present depending upon options chosen by the user when the core was 164bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * configured and built. Please consult the Altera Triple Speed Ethernet User 165bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Guide for details. 166bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 167bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersstruct altera_tse_mac { 168bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer 169bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * specific revision 170bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 171bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 megacore_revision; 172bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Provides a memory location for user applications to test the device 173bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * memory operation. 174bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 175bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 scratch_pad; 176bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* The host processor uses this register to control and configure the 177bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * MAC block 178bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 179bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 command_config; 180bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary 181bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * MAC address 182bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 183bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 mac_addr_0; 184bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary 185bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * MAC address 186bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 187bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 mac_addr_1; 188bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 14-bit maximum frame length. The MAC receive logic */ 189bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 frm_length; 190bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* The pause quanta is used in each pause frame sent to a remote 191bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * Ethernet device, in increments of 512 Ethernet bit times 192bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 193bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 pause_quanta; 194bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit receive FIFO section-empty threshold */ 195bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_section_empty; 196bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit receive FIFO section-full threshold */ 197bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_section_full; 198bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit transmit FIFO section-empty threshold */ 199bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_section_empty; 200bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit transmit FIFO section-full threshold */ 201bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_section_full; 202bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit receive FIFO almost-empty threshold */ 203bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_almost_empty; 204bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit receive FIFO almost-full threshold */ 205bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_almost_full; 206bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit transmit FIFO almost-empty threshold */ 207bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_almost_empty; 208bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 12-bit transmit FIFO almost-full threshold */ 209bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_almost_full; 210bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */ 211bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 mdio_phy0_addr; 212bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */ 213bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 mdio_phy1_addr; 214bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 215bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Bit[15:0]—16-bit holdoff quanta */ 216bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 holdoff_quant; 217bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 218bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* only if 100/1000 BaseX PCS, reserved otherwise */ 219bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reserved1[5]; 220bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 221bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Minimum IPG between consecutive transmit frame in terms of bytes */ 222bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_ipg_length; 223bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 224bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* IEEE 802.3 oEntity Managed Object Support */ 225bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 226bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* The MAC addresses */ 227bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 mac_id_1; 228bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 mac_id_2; 229bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 230bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of frames transmitted without error including pause frames */ 231bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 frames_transmitted_ok; 232bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of frames received without error including pause frames */ 233bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 frames_received_ok; 234bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of frames received with a CRC error */ 235bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 frames_check_sequence_errors; 236bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Frame received with an alignment error */ 237bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 alignment_errors; 238bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Sum of payload and padding octets of frames transmitted without 239bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * error 240bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 241bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 octets_transmitted_ok; 242bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Sum of payload and padding octets of frames received without error */ 243bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 octets_received_ok; 244bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 245bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* IEEE 802.3 oPausedEntity Managed Object Support */ 246bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 247bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of transmitted pause frames */ 248bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_pause_mac_ctrl_frames; 249bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of Received pause frames */ 250bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_pause_mac_ctrl_frames; 251bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 252bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* IETF MIB (MIB-II) Object Support */ 253bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 254bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of frames received with error */ 255bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_in_errors; 256bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of frames transmitted with error */ 257bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_out_errors; 258bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of valid received unicast frames */ 259bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_in_ucast_pkts; 260bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of valid received multicasts frames (without pause) */ 261bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_in_multicast_pkts; 262bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of valid received broadcast frames */ 263bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_in_broadcast_pkts; 264bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_out_discards; 265bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* The number of valid unicast frames transmitted */ 266bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_out_ucast_pkts; 267bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* The number of valid multicast frames transmitted, 268bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * excluding pause frames 269bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 270bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_out_multicast_pkts; 271bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 if_out_broadcast_pkts; 272bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 273bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* IETF RMON MIB Object Support */ 274bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 275bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Counts the number of dropped packets due to internal errors 276bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * of the MAC client. 277bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 278bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_drop_events; 279bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Total number of bytes received. Good and bad frames. */ 280bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_octets; 281bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Total number of packets received. Counts good and bad packets. */ 282bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts; 283bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of packets received with less than 64 bytes. */ 284bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_undersize_pkts; 285bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* The number of frames received that are longer than the 286bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * value configured in the frm_length register 287bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 288bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_oversize_pkts; 289bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Number of received packet with 64 bytes */ 290bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_64_octets; 291bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Frames (good and bad) with 65 to 127 bytes */ 292bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_65to127_octets; 293bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Frames (good and bad) with 128 to 255 bytes */ 294bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_128to255_octets; 295bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Frames (good and bad) with 256 to 511 bytes */ 296bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_256to511_octets; 297bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Frames (good and bad) with 512 to 1023 bytes */ 298bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_512to1023_octets; 299bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Frames (good and bad) with 1024 to 1518 bytes */ 300bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_1024to1518_octets; 301bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 302bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Any frame length from 1519 to the maximum length configured in the 303bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * frm_length register, if it is greater than 1518 304bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 305bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_pkts_1519tox_octets; 306bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Too long frames with CRC error */ 307bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_jabbers; 308bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Too short frames with CRC error */ 309bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 ether_stats_fragments; 310bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 311bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reserved2; 312bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 313bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* FIFO control register */ 314bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_cmd_stat; 315bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_cmd_stat; 316bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 317bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Extended Statistics Counters */ 318bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 msb_octets_transmitted_ok; 319bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 msb_octets_received_ok; 320bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 msb_ether_stats_octets; 321bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 322bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reserved3; 323bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 324bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Multicast address resolution table, mapped in the controller address 325bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * space 326bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 327bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 hash_table[64]; 328bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 329bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY 330bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * management interface 331bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 332bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct altera_tse_mdio mdio_phy0; 333bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct altera_tse_mdio mdio_phy1; 334bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 335bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* 4 Supplemental MAC Addresses */ 336bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_0_0; 337bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_0_1; 338bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_1_0; 339bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_1_1; 340bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_2_0; 341bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_2_1; 342bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_3_0; 343bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 supp_mac_addr_3_1; 344bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 345bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reserved4[8]; 346bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 347bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* IEEE 1588v2 Feature */ 348bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_period; 349bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_adjust_fns; 350bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_adjust_ns; 351bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_period; 352bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_adjust_fns; 353bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_adjust_ns; 354bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 355bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 reserved5[42]; 356bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers}; 357bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 358bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* Transmit and Receive Command Registers Bit Definitions 359bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 360bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) 361bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18) 362bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25) 363bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 364bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* Wrapper around a pointer to a socket buffer, 365bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers * so a DMA handle can be stored along with the buffer 366bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 367bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersstruct tse_buffer { 368bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct list_head lh; 369bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct sk_buff *skb; 370bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers dma_addr_t dma_addr; 371bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 len; 372bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int mapped_as_page; 373bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers}; 374bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 375bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersstruct altera_tse_private; 376bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 377bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_DTYPE_SGDMA 1 378bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#define ALTERA_DTYPE_MSGDMA 2 379bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 380bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* standard DMA interface for SGDMA and MSGDMA */ 381bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersstruct altera_dmaops { 382bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int altera_dtype; 383bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int dmamask; 384bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*reset_dma)(struct altera_tse_private *); 385bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*enable_txirq)(struct altera_tse_private *); 386bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*enable_rxirq)(struct altera_tse_private *); 387bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*disable_txirq)(struct altera_tse_private *); 388bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*disable_rxirq)(struct altera_tse_private *); 389bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*clear_txirq)(struct altera_tse_private *); 390bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*clear_rxirq)(struct altera_tse_private *); 391bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *); 392bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 (*tx_completions)(struct altera_tse_private *); 393bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *); 394bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 (*get_rx_status)(struct altera_tse_private *); 395bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int (*init_dma)(struct altera_tse_private *); 396bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void (*uninit_dma)(struct altera_tse_private *); 397bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers}; 398bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 399bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* This structure is private to each device. 400bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 401bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersstruct altera_tse_private { 402bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct net_device *dev; 403bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct device *device; 404bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct napi_struct napi; 405bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 406bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* MAC address space */ 407bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct altera_tse_mac __iomem *mac_dev; 408bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 409bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* TSE Revision */ 410bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 revision; 411bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 412bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* mSGDMA Rx Dispatcher address space */ 413bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void __iomem *rx_dma_csr; 414bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void __iomem *rx_dma_desc; 415bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void __iomem *rx_dma_resp; 416bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 417bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* mSGDMA Tx Dispatcher address space */ 418bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void __iomem *tx_dma_csr; 419bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers void __iomem *tx_dma_desc; 420bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 421bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Rx buffers queue */ 422bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct tse_buffer *rx_ring; 423bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_cons; 424bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_prod; 425bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_ring_size; 426bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_dma_buf_sz; 427bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 428bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Tx ring buffer */ 429bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct tse_buffer *tx_ring; 430bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_prod; 431bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_cons; 432bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_ring_size; 433bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 434bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Interrupts */ 435bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_irq; 436bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_irq; 437bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 438bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* RX/TX MAC FIFO configs */ 439bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 tx_fifo_depth; 440bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rx_fifo_depth; 441bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 max_mtu; 442bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 443bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Hash filter settings */ 444bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 hash_filter; 445bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 added_unicast; 446bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 447bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Descriptor memory info for managing SGDMA */ 448bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 txdescmem; 449bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rxdescmem; 450bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers dma_addr_t rxdescmem_busaddr; 451bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers dma_addr_t txdescmem_busaddr; 452bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 txctrlreg; 453bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 rxctrlreg; 454bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers dma_addr_t rxdescphys; 455bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers dma_addr_t txdescphys; 456bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 457bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct list_head txlisthd; 458bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct list_head rxlisthd; 459bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 460bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* MAC command_config register protection */ 461bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers spinlock_t mac_cfg_lock; 462bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Tx path protection */ 463bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers spinlock_t tx_lock; 464bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* Rx DMA & interrupt control protection */ 465bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers spinlock_t rxdma_irq_lock; 466bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 467bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* PHY */ 468bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int phy_addr; /* PHY's MDIO address, -1 for autodetection */ 469bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers phy_interface_t phy_iface; 470bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct mii_bus *mdio; 471bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct phy_device *phydev; 472bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int oldspeed; 473bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int oldduplex; 474bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers int oldlink; 475bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 476bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers /* ethtool msglvl option */ 477bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers u32 msg_enable; 478bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 479bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers struct altera_dmaops *dmaops; 480bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers}; 481bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 482bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers/* Function prototypes 483bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers */ 484bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgersvoid altera_tse_set_ethtool_ops(struct net_device *); 485bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers 486bbd2190ce96d8fce031f0526c1f970b68adc9d1aVince Bridgers#endif /* __ALTERA_TSE_H__ */ 487