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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program.  If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_FCOE_H_
28#define _I40E_FCOE_H_
29
30/* FCoE HW context helper macros */
31#define I40E_DDP_CONTEXT_DESC(R, i)     \
32	(&(((struct i40e_fcoe_ddp_context_desc *)((R)->desc))[i]))
33
34#define I40E_QUEUE_CONTEXT_DESC(R, i)   \
35	(&(((struct i40e_fcoe_queue_context_desc *)((R)->desc))[i]))
36
37#define I40E_FILTER_CONTEXT_DESC(R, i)  \
38	(&(((struct i40e_fcoe_filter_context_desc *)((R)->desc))[i]))
39
40
41/* receive queue descriptor filter status for FCoE */
42#define I40E_RX_DESC_FLTSTAT_FCMASK	0x3
43#define I40E_RX_DESC_FLTSTAT_NOMTCH	0x0	/* no ddp context match */
44#define I40E_RX_DESC_FLTSTAT_NODDP	0x1	/* no ddp due to error */
45#define I40E_RX_DESC_FLTSTAT_DDP	0x2	/* DDPed payload, post header */
46#define I40E_RX_DESC_FLTSTAT_FCPRSP	0x3	/* FCP_RSP */
47
48/* receive queue descriptor error codes for FCoE */
49#define I40E_RX_DESC_FCOE_ERROR_MASK		\
50	(I40E_RX_DESC_ERROR_L3L4E_PROT |	\
51	 I40E_RX_DESC_ERROR_L3L4E_FC |		\
52	 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR |	\
53	 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN)
54
55/* receive queue descriptor programming error */
56#define I40E_RX_PROG_FCOE_ERROR_TBL_FULL(e)	\
57	(((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT) & 0x1)
58
59#define I40E_RX_PROG_FCOE_ERROR_CONFLICT(e)	\
60	(((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT) & 0x1)
61
62#define I40E_RX_PROG_FCOE_ERROR_TBL_FULL_BIT	\
63	(1 << I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT)
64#define I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT	\
65	(1 << I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT)
66
67#define I40E_RX_PROG_FCOE_ERROR_INVLFAIL(e)	\
68	I40E_RX_PROG_FCOE_ERROR_CONFLICT(e)
69#define I40E_RX_PROG_FCOE_ERROR_INVLFAIL_BIT	\
70	I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT
71
72/* FCoE DDP related definitions */
73#define I40E_FCOE_MIN_XID	0x0000  /* the min xid supported by fcoe_sw */
74#define I40E_FCOE_MAX_XID	0x0FFF  /* the max xid supported by fcoe_sw */
75#define I40E_FCOE_DDP_BUFFCNT_MAX	512	/* 9 bits bufcnt */
76#define I40E_FCOE_DDP_PTR_ALIGN		16
77#define I40E_FCOE_DDP_PTR_MAX	(I40E_FCOE_DDP_BUFFCNT_MAX * sizeof(dma_addr_t))
78#define I40E_FCOE_DDP_BUF_MIN	4096
79#define I40E_FCOE_DDP_MAX	2048
80#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT	8
81
82/* supported netdev features for FCoE */
83#define I40E_FCOE_NETIF_FEATURES (NETIF_F_ALL_FCOE | \
84	NETIF_F_HW_VLAN_CTAG_TX | \
85	NETIF_F_HW_VLAN_CTAG_RX | \
86	NETIF_F_HW_VLAN_CTAG_FILTER)
87
88/* DDP context flags */
89enum i40e_fcoe_ddp_flags {
90	__I40E_FCOE_DDP_NONE = 1,
91	__I40E_FCOE_DDP_TARGET,
92	__I40E_FCOE_DDP_INITALIZED,
93	__I40E_FCOE_DDP_PROGRAMMED,
94	__I40E_FCOE_DDP_DONE,
95	__I40E_FCOE_DDP_ABORTED,
96	__I40E_FCOE_DDP_UNMAPPED,
97};
98
99/* DDP SW context struct */
100struct i40e_fcoe_ddp {
101	int len;
102	u16 xid;
103	u16 firstoff;
104	u16 lastsize;
105	u16 list_len;
106	u8 fcerr;
107	u8 prerr;
108	unsigned long flags;
109	unsigned int sgc;
110	struct scatterlist *sgl;
111	dma_addr_t udp;
112	u64 *udl;
113	struct dma_pool *pool;
114
115};
116
117struct i40e_fcoe_ddp_pool {
118	struct dma_pool *pool;
119};
120
121struct i40e_fcoe {
122	unsigned long mode;
123	atomic_t refcnt;
124	struct i40e_fcoe_ddp_pool __percpu *ddp_pool;
125	struct i40e_fcoe_ddp ddp[I40E_FCOE_DDP_MAX];
126};
127
128#endif /* _I40E_FCOE_H_ */
129