1 2/********************************************************************* 3 * 4 * vlsi_ir.h: VLSI82C147 PCI IrDA controller driver for Linux 5 * 6 * Version: 0.5 7 * 8 * Copyright (c) 2001-2003 Martin Diehl 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 ********************************************************************/ 24 25#ifndef IRDA_VLSI_FIR_H 26#define IRDA_VLSI_FIR_H 27 28/* ================================================================ 29 * compatibility stuff 30 */ 31 32/* definitions not present in pci_ids.h */ 33 34#ifndef PCI_CLASS_WIRELESS_IRDA 35#define PCI_CLASS_WIRELESS_IRDA 0x0d00 36#endif 37 38#ifndef PCI_CLASS_SUBCLASS_MASK 39#define PCI_CLASS_SUBCLASS_MASK 0xffff 40#endif 41 42/* ================================================================ */ 43 44/* non-standard PCI registers */ 45 46enum vlsi_pci_regs { 47 VLSI_PCI_CLKCTL = 0x40, /* chip clock input control */ 48 VLSI_PCI_MSTRPAGE = 0x41, /* addr [31:24] for all busmaster cycles */ 49 VLSI_PCI_IRMISC = 0x42 /* mainly legacy UART related */ 50}; 51 52/* ------------------------------------------ */ 53 54/* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */ 55 56/* Three possible clock sources: either on-chip 48MHz PLL or 57 * external clock applied to EXTCLK pin. External clock may 58 * be either 48MHz or 40MHz, which is indicated by XCKSEL. 59 * CLKSTP controls whether the selected clock source gets 60 * connected to the IrDA block. 61 * 62 * On my HP OB-800 the BIOS sets external 40MHz clock as source 63 * when IrDA enabled and I've never detected any PLL lock success. 64 * Apparently the 14.3...MHz OSC input required for the PLL to work 65 * is not connected and the 40MHz EXTCLK is provided externally. 66 * At least this is what makes the driver working for me. 67 */ 68 69enum vlsi_pci_clkctl { 70 71 /* PLL control */ 72 73 CLKCTL_PD_INV = 0x04, /* PD#: inverted power down signal, 74 * i.e. PLL is powered, if PD_INV set */ 75 CLKCTL_LOCK = 0x40, /* (ro) set, if PLL is locked */ 76 77 /* clock source selection */ 78 79 CLKCTL_EXTCLK = 0x20, /* set to select external clock input, not PLL */ 80 CLKCTL_XCKSEL = 0x10, /* set to indicate EXTCLK is 40MHz, not 48MHz */ 81 82 /* IrDA block control */ 83 84 CLKCTL_CLKSTP = 0x80, /* set to disconnect from selected clock source */ 85 CLKCTL_WAKE = 0x08 /* set to enable wakeup feature: whenever IR activity 86 * is detected, PD_INV gets set(?) and CLKSTP cleared */ 87}; 88 89/* ------------------------------------------ */ 90 91/* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */ 92 93#define DMA_MASK_USED_BY_HW 0xffffffff 94#define DMA_MASK_MSTRPAGE 0x00ffffff 95#define MSTRPAGE_VALUE (DMA_MASK_MSTRPAGE >> 24) 96 97 /* PCI busmastering is somewhat special for this guy - in short: 98 * 99 * We select to operate using fixed MSTRPAGE=0, use ISA DMA 100 * address restrictions to make the PCI BM api aware of this, 101 * but ensure the hardware is dealing with real 32bit access. 102 * 103 * In detail: 104 * The chip executes normal 32bit busmaster cycles, i.e. 105 * drives all 32 address lines. These addresses however are 106 * composed of [0:23] taken from various busaddr-pointers 107 * and [24:31] taken from the MSTRPAGE register in the VLSI82C147 108 * config space. Therefore _all_ busmastering must be 109 * targeted to/from one single 16MB (busaddr-) superpage! 110 * The point is to make sure all the allocations for memory 111 * locations with busmaster access (ring descriptors, buffers) 112 * are indeed bus-mappable to the same 16MB range (for x86 this 113 * means they must reside in the same 16MB physical memory address 114 * range). The only constraint we have which supports "several objects 115 * mappable to common 16MB range" paradigma, is the old ISA DMA 116 * restriction to the first 16MB of physical address range. 117 * Hence the approach here is to enable PCI busmaster support using 118 * the correct 32bit dma-mask used by the chip. Afterwards the device's 119 * dma-mask gets restricted to 24bit, which must be honoured somehow by 120 * all allocations for memory areas to be exposed to the chip ... 121 * 122 * Note: 123 * Don't be surprised to get "Setting latency timer..." messages every 124 * time when PCI busmastering is enabled for the chip. 125 * The chip has its PCI latency timer RO fixed at 0 - which is not a 126 * problem here, because it is never requesting _burst_ transactions. 127 */ 128 129/* ------------------------------------------ */ 130 131/* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */ 132 133/* legacy UART emulation - not used by this driver - would require: 134 * (see below for some register-value definitions) 135 * 136 * - IRMISC_UARTEN must be set to enable UART address decoding 137 * - IRMISC_UARTSEL configured 138 * - IRCFG_MASTER must be cleared 139 * - IRCFG_SIR must be set 140 * - IRENABLE_PHYANDCLOCK must be asserted 0->1 (and hence IRENABLE_SIR_ON) 141 */ 142 143enum vlsi_pci_irmisc { 144 145 /* IR transceiver control */ 146 147 IRMISC_IRRAIL = 0x40, /* (ro?) IR rail power indication (and control?) 148 * 0=3.3V / 1=5V. Probably set during power-on? 149 * unclear - not touched by driver */ 150 IRMISC_IRPD = 0x08, /* transceiver power down, if set */ 151 152 /* legacy UART control */ 153 154 IRMISC_UARTTST = 0x80, /* UART test mode - "always write 0" */ 155 IRMISC_UARTEN = 0x04, /* enable UART address decoding */ 156 157 /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */ 158 159 IRMISC_UARTSEL_3f8 = 0x00, 160 IRMISC_UARTSEL_2f8 = 0x01, 161 IRMISC_UARTSEL_3e8 = 0x02, 162 IRMISC_UARTSEL_2e8 = 0x03 163}; 164 165/* ================================================================ */ 166 167/* registers mapped to 32 byte PCI IO space */ 168 169/* note: better access all registers at the indicated u8/u16 size 170 * although some of them contain only 1 byte of information. 171 * some of them (particaluarly PROMPT and IRCFG) ignore 172 * access when using the wrong addressing mode! 173 */ 174 175enum vlsi_pio_regs { 176 VLSI_PIO_IRINTR = 0x00, /* interrupt enable/request (u8, rw) */ 177 VLSI_PIO_RINGPTR = 0x02, /* rx/tx ring pointer (u16, ro) */ 178 VLSI_PIO_RINGBASE = 0x04, /* [23:10] of ring address (u16, rw) */ 179 VLSI_PIO_RINGSIZE = 0x06, /* rx/tx ring size (u16, rw) */ 180 VLSI_PIO_PROMPT = 0x08, /* triggers ring processing (u16, wo) */ 181 /* 0x0a-0x0f: reserved / duplicated UART regs */ 182 VLSI_PIO_IRCFG = 0x10, /* configuration select (u16, rw) */ 183 VLSI_PIO_SIRFLAG = 0x12, /* BOF/EOF for filtered SIR (u16, ro) */ 184 VLSI_PIO_IRENABLE = 0x14, /* enable and status register (u16, rw/ro) */ 185 VLSI_PIO_PHYCTL = 0x16, /* physical layer current status (u16, ro) */ 186 VLSI_PIO_NPHYCTL = 0x18, /* next physical layer select (u16, rw) */ 187 VLSI_PIO_MAXPKT = 0x1a, /* [11:0] max len for packet receive (u16, rw) */ 188 VLSI_PIO_RCVBCNT = 0x1c /* current receive-FIFO byte count (u16, ro) */ 189 /* 0x1e-0x1f: reserved / duplicated UART regs */ 190}; 191 192/* ------------------------------------------ */ 193 194/* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */ 195 196/* enable-bits: 197 * 1 = enable / 0 = disable 198 * interrupt condition bits: 199 * set according to corresponding interrupt source 200 * (regardless of the state of the enable bits) 201 * enable bit status indicates whether interrupt gets raised 202 * write-to-clear 203 * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-) 204 */ 205 206enum vlsi_pio_irintr { 207 IRINTR_ACTEN = 0x80, /* activity interrupt enable */ 208 IRINTR_ACTIVITY = 0x40, /* activity monitor (traffic detected) */ 209 IRINTR_RPKTEN = 0x20, /* receive packet interrupt enable*/ 210 IRINTR_RPKTINT = 0x10, /* rx-packet transferred from fifo to memory finished */ 211 IRINTR_TPKTEN = 0x08, /* transmit packet interrupt enable */ 212 IRINTR_TPKTINT = 0x04, /* last bit of tx-packet+crc shifted to ir-pulser */ 213 IRINTR_OE_EN = 0x02, /* UART rx fifo overrun error interrupt enable */ 214 IRINTR_OE_INT = 0x01 /* UART rx fifo overrun error (read LSR to clear) */ 215}; 216 217/* we use this mask to check whether the (shared PCI) interrupt is ours */ 218 219#define IRINTR_INT_MASK (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT) 220 221/* ------------------------------------------ */ 222 223/* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */ 224 225/* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring! 226 * i.e. the referenced descriptor is located 227 * at RINGBASE + PTR * sizeof(descr) for rx and tx 228 * therefore, the tx-pointer has offset MAX_RING_DESCR 229 */ 230 231#define MAX_RING_DESCR 64 /* tx, rx rings may contain up to 64 descr each */ 232 233#define RINGPTR_RX_MASK (MAX_RING_DESCR-1) 234#define RINGPTR_TX_MASK ((MAX_RING_DESCR-1)<<8) 235 236#define RINGPTR_GET_RX(p) ((p)&RINGPTR_RX_MASK) 237#define RINGPTR_GET_TX(p) (((p)&RINGPTR_TX_MASK)>>8) 238 239/* ------------------------------------------ */ 240 241/* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */ 242 243/* Contains [23:10] part of the ring base (bus-) address 244 * which must be 1k-alinged. [31:24] is taken from 245 * VLSI_PCI_MSTRPAGE above. 246 * The controller initiates non-burst PCI BM cycles to 247 * fetch and update the descriptors in the ring. 248 * Once fetched, the descriptor remains cached onchip 249 * until it gets closed and updated due to the ring 250 * processing state machine. 251 * The entire ring area is split in rx and tx areas with each 252 * area consisting of 64 descriptors of 8 bytes each. 253 * The rx(tx) ring is located at ringbase+0 (ringbase+64*8). 254 */ 255 256#define BUS_TO_RINGBASE(p) (((p)>>10)&0x3fff) 257 258/* ------------------------------------------ */ 259 260/* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */ 261 262/* bit mask to indicate the ring size to be used for rx and tx. 263 * possible values encoded bits 264 * 4 0000 265 * 8 0001 266 * 16 0011 267 * 32 0111 268 * 64 1111 269 * located at [15:12] for tx and [11:8] for rx ([7:0] unused) 270 * 271 * note: probably a good idea to have IRCFG_MSTR cleared when writing 272 * this so the state machines are stopped and the RINGPTR is reset! 273 */ 274 275#define SIZE_TO_BITS(num) ((((num)-1)>>2)&0x0f) 276#define TX_RX_TO_RINGSIZE(tx,rx) ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8)) 277#define RINGSIZE_TO_RXSIZE(rs) ((((rs)&0x0f00)>>6)+4) 278#define RINGSIZE_TO_TXSIZE(rs) ((((rs)&0xf000)>>10)+4) 279 280 281/* ------------------------------------------ */ 282 283/* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */ 284 285/* writing any value kicks the ring processing state machines 286 * for both tx, rx rings as follows: 287 * - active rings (currently owning an active descriptor) 288 * ignore the prompt and continue 289 * - idle rings fetch the next descr from the ring and start 290 * their processing 291 */ 292 293/* ------------------------------------------ */ 294 295/* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */ 296 297/* notes: 298 * - not more than one SIR/MIR/FIR bit must be set at any time 299 * - SIR, MIR, FIR and CRC16 select the configuration which will 300 * be applied on next 0->1 transition of IRENABLE_PHYANDCLOCK (see below). 301 * - besides allowing the PCI interface to execute busmaster cycles 302 * and therefore the ring SM to operate, the MSTR bit has side-effects: 303 * when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode 304 * (in contrast to busmaster access mode) gets enabled. 305 * - clearing ENRX or setting ENTX while data is received may stall the 306 * receive fifo until ENRX reenabled _and_ another packet arrives 307 * - SIRFILT means the chip performs the required unwrapping of hardware 308 * headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction. 309 * Only the resulting IrLAP payload is copied to the receive buffers - 310 * but with the 16bit FCS still encluded. Question remains, whether it 311 * was already checked or we should do it before passing the packet to IrLAP? 312 */ 313 314enum vlsi_pio_ircfg { 315 IRCFG_LOOP = 0x4000, /* enable loopback test mode */ 316 IRCFG_ENTX = 0x1000, /* transmit enable */ 317 IRCFG_ENRX = 0x0800, /* receive enable */ 318 IRCFG_MSTR = 0x0400, /* master enable */ 319 IRCFG_RXANY = 0x0200, /* receive any packet */ 320 IRCFG_CRC16 = 0x0080, /* 16bit (not 32bit) CRC select for MIR/FIR */ 321 IRCFG_FIR = 0x0040, /* FIR 4PPM encoding mode enable */ 322 IRCFG_MIR = 0x0020, /* MIR HDLC encoding mode enable */ 323 IRCFG_SIR = 0x0010, /* SIR encoding mode enable */ 324 IRCFG_SIRFILT = 0x0008, /* enable SIR decode filter (receiver unwrapping) */ 325 IRCFG_SIRTEST = 0x0004, /* allow SIR decode filter when not in SIR mode */ 326 IRCFG_TXPOL = 0x0002, /* invert tx polarity when set */ 327 IRCFG_RXPOL = 0x0001 /* invert rx polarity when set */ 328}; 329 330/* ------------------------------------------ */ 331 332/* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */ 333 334/* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8] 335 * which is used for unwrapping received frames in SIR decode-filter mode 336 */ 337 338/* ------------------------------------------ */ 339 340/* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */ 341 342/* notes: 343 * - IREN acts as gate for latching the configured IR mode information 344 * from IRCFG and IRPHYCTL when IREN=reset and applying them when 345 * IREN gets set afterwards. 346 * - ENTXST reflects IRCFG_ENTX 347 * - ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP) 348 */ 349 350enum vlsi_pio_irenable { 351 IRENABLE_PHYANDCLOCK = 0x8000, /* enable IR phy and gate the mode config (rw) */ 352 IRENABLE_CFGER = 0x4000, /* mode configuration error (ro) */ 353 IRENABLE_FIR_ON = 0x2000, /* FIR on status (ro) */ 354 IRENABLE_MIR_ON = 0x1000, /* MIR on status (ro) */ 355 IRENABLE_SIR_ON = 0x0800, /* SIR on status (ro) */ 356 IRENABLE_ENTXST = 0x0400, /* transmit enable status (ro) */ 357 IRENABLE_ENRXST = 0x0200, /* Receive enable status (ro) */ 358 IRENABLE_CRC16_ON = 0x0100 /* 16bit (not 32bit) CRC enabled status (ro) */ 359}; 360 361#define IRENABLE_MASK 0xff00 /* Read mask */ 362 363/* ------------------------------------------ */ 364 365/* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */ 366 367/* read-back of the currently applied physical layer status. 368 * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_PHYANDCLOCK 369 * contents identical to VLSI_PIO_NPHYCTL (see below) 370 */ 371 372/* ------------------------------------------ */ 373 374/* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */ 375 376/* latched during IRENABLE_PHYANDCLOCK=0 and applied at 0-1 transition 377 * 378 * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows: 379 * 380 * SIR-mode: BAUD = (115.2kHz / baudrate) - 1 381 * PLSWID = (pulsetime * freq / (BAUD+1)) - 1 382 * where pulsetime is the requested IrPHY pulse width 383 * and freq is 8(16)MHz for 40(48)MHz primary input clock 384 * PREAMB: don't care for SIR 385 * 386 * The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12 387 * fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz). 388 * IrPHY also allows shorter pulses down to the nominal pulse duration 389 * at 115.2kbaud (minus some tolerance) which is 1.41 usec. 390 * Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by two for 48MHz) 391 * we get the minimum acceptable PLSWID values according to the VLSI 392 * specification, which provides 1.5 usec pulse width for all speeds (except 393 * for 2.4kbaud getting 6usec). This is fine with IrPHY v1.3 specs and 394 * reduces the transceiver power which drains the battery. At 9.6kbaud for 395 * example this amounts to more than 90% battery power saving! 396 * 397 * MIR-mode: BAUD = 0 398 * PLSWID = 9(10) for 40(48) MHz input clock 399 * to get nominal MIR pulse width 400 * PREAMB = 1 401 * 402 * FIR-mode: BAUD = 0 403 * PLSWID: don't care 404 * PREAMB = 15 405 */ 406 407#define PHYCTL_BAUD_SHIFT 10 408#define PHYCTL_BAUD_MASK 0xfc00 409#define PHYCTL_PLSWID_SHIFT 5 410#define PHYCTL_PLSWID_MASK 0x03e0 411#define PHYCTL_PREAMB_SHIFT 0 412#define PHYCTL_PREAMB_MASK 0x001f 413 414#define PHYCTL_TO_BAUD(bwp) (((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT) 415#define PHYCTL_TO_PLSWID(bwp) (((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT) 416#define PHYCTL_TO_PREAMB(bwp) (((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT) 417 418#define BWP_TO_PHYCTL(b,w,p) ((((b)<<PHYCTL_BAUD_SHIFT)&PHYCTL_BAUD_MASK) \ 419 | (((w)<<PHYCTL_PLSWID_SHIFT)&PHYCTL_PLSWID_MASK) \ 420 | (((p)<<PHYCTL_PREAMB_SHIFT)&PHYCTL_PREAMB_MASK)) 421 422#define BAUD_BITS(br) ((115200/(br))-1) 423 424static inline unsigned 425calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect) 426{ 427 unsigned tmp; 428 429 if (widthselect) /* nominal 3/16 puls width */ 430 return (clockselect) ? 12 : 24; 431 432 tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1); 433 434 /* intermediate result of integer division needed here */ 435 436 return (tmp>0) ? (tmp-1) : 0; 437} 438 439#define PHYCTL_SIR(br,ws,cs) BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0) 440#define PHYCTL_MIR(cs) BWP_TO_PHYCTL(0,((cs)?9:10),1) 441#define PHYCTL_FIR BWP_TO_PHYCTL(0,0,15) 442 443/* quite ugly, I know. But implementing these calculations here avoids 444 * having magic numbers in the code and allows some playing with pulsewidths 445 * without risk to violate the standards. 446 * FWIW, here is the table for reference: 447 * 448 * baudrate BAUD min-PLSWID nom-PLSWID PREAMB 449 * 2400 47 0(0) 12(24) 0 450 * 9600 11 0(0) 12(24) 0 451 * 19200 5 1(2) 12(24) 0 452 * 38400 2 3(6) 12(24) 0 453 * 57600 1 5(10) 12(24) 0 454 * 115200 0 11(22) 12(24) 0 455 * MIR 0 - 9(10) 1 456 * FIR 0 - 0 15 457 * 458 * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock 459 */ 460 461/* ------------------------------------------ */ 462 463 464/* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */ 465 466/* maximum acceptable length for received packets */ 467 468/* hw imposed limitation - register uses only [11:0] */ 469#define MAX_PACKET_LENGTH 0x0fff 470 471/* IrLAP I-field (apparently not defined elsewhere) */ 472#define IRDA_MTU 2048 473 474/* complete packet consists of A(1)+C(1)+I(<=IRDA_MTU) */ 475#define IRLAP_SKB_ALLOCSIZE (1+1+IRDA_MTU) 476 477/* the buffers we use to exchange frames with the hardware need to be 478 * larger than IRLAP_SKB_ALLOCSIZE because we may have up to 4 bytes FCS 479 * appended and, in SIR mode, a lot of frame wrapping bytes. The worst 480 * case appears to be a SIR packet with I-size==IRDA_MTU and all bytes 481 * requiring to be escaped to provide transparency. Furthermore, the peer 482 * might ask for quite a number of additional XBOFs: 483 * up to 115+48 XBOFS 163 484 * regular BOF 1 485 * A-field 1 486 * C-field 1 487 * I-field, IRDA_MTU, all escaped 4096 488 * FCS (16 bit at SIR, escaped) 4 489 * EOF 1 490 * AFAICS nothing in IrLAP guarantees A/C field not to need escaping 491 * (f.e. 0xc0/0xc1 - i.e. BOF/EOF - are legal values there) so in the 492 * worst case we have 4269 bytes total frame size. 493 * However, the VLSI uses 12 bits only for all buffer length values, 494 * which limits the maximum useable buffer size <= 4095. 495 * Note this is not a limitation in the receive case because we use 496 * the SIR filtering mode where the hw unwraps the frame and only the 497 * bare packet+fcs is stored into the buffer - in contrast to the SIR 498 * tx case where we have to pass frame-wrapped packets to the hw. 499 * If this would ever become an issue in real life, the only workaround 500 * I see would be using the legacy UART emulation in SIR mode. 501 */ 502 503#define XFER_BUF_SIZE MAX_PACKET_LENGTH 504 505/* ------------------------------------------ */ 506 507/* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */ 508 509/* receive packet counter gets incremented on every non-filtered 510 * byte which was put in the receive fifo and reset for each 511 * new packet. Used to decide whether we are just in the middle 512 * of receiving 513 */ 514 515/* better apply the [11:0] mask when reading, as some docs say the 516 * reserved [15:12] would return 1 when reading - which is wrong AFAICS 517 */ 518#define RCVBCNT_MASK 0x0fff 519 520/******************************************************************/ 521 522/* descriptors for rx/tx ring 523 * 524 * accessed by hardware - don't change! 525 * 526 * the descriptor is owned by hardware, when the ACTIVE status bit 527 * is set and nothing (besides reading status to test the bit) 528 * shall be done. The bit gets cleared by hw, when the descriptor 529 * gets closed. Premature reaping of descriptors owned be the chip 530 * can be achieved by disabling IRCFG_MSTR 531 * 532 * Attention: Writing addr overwrites status! 533 * 534 * ### FIXME: depends on endianess (but there ain't no non-i586 ob800 ;-) 535 */ 536 537struct ring_descr_hw { 538 volatile __le16 rd_count; /* tx/rx count [11:0] */ 539 __le16 reserved; 540 union { 541 __le32 addr; /* [23:0] of the buffer's busaddress */ 542 struct { 543 u8 addr_res[3]; 544 volatile u8 status; /* descriptor status */ 545 } __packed rd_s; 546 } __packed rd_u; 547} __packed; 548 549#define rd_addr rd_u.addr 550#define rd_status rd_u.rd_s.status 551 552/* ring descriptor status bits */ 553 554#define RD_ACTIVE 0x80 /* descriptor owned by hw (both TX,RX) */ 555 556/* TX ring descriptor status */ 557 558#define RD_TX_DISCRC 0x40 /* do not send CRC (for SIR) */ 559#define RD_TX_BADCRC 0x20 /* force a bad CRC */ 560#define RD_TX_PULSE 0x10 /* send indication pulse after this frame (MIR/FIR) */ 561#define RD_TX_FRCEUND 0x08 /* force underrun */ 562#define RD_TX_CLRENTX 0x04 /* clear ENTX after this frame */ 563#define RD_TX_UNDRN 0x01 /* TX fifo underrun (probably PCI problem) */ 564 565/* RX ring descriptor status */ 566 567#define RD_RX_PHYERR 0x40 /* physical encoding error */ 568#define RD_RX_CRCERR 0x20 /* CRC error (MIR/FIR) */ 569#define RD_RX_LENGTH 0x10 /* frame exceeds buffer length */ 570#define RD_RX_OVER 0x08 /* RX fifo overrun (probably PCI problem) */ 571#define RD_RX_SIRBAD 0x04 /* EOF missing: BOF follows BOF (SIR, filtered) */ 572 573#define RD_RX_ERROR 0x7c /* any error in received frame */ 574 575/* the memory required to hold the 2 descriptor rings */ 576#define HW_RING_AREA_SIZE (2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw)) 577 578/******************************************************************/ 579 580/* sw-ring descriptors consists of a bus-mapped transfer buffer with 581 * associated skb and a pointer to the hw entry descriptor 582 */ 583 584struct ring_descr { 585 struct ring_descr_hw *hw; 586 struct sk_buff *skb; 587 void *buf; 588}; 589 590/* wrappers for operations on hw-exposed ring descriptors 591 * access to the hw-part of the descriptors must use these. 592 */ 593 594static inline int rd_is_active(struct ring_descr *rd) 595{ 596 return (rd->hw->rd_status & RD_ACTIVE) != 0; 597} 598 599static inline void rd_activate(struct ring_descr *rd) 600{ 601 rd->hw->rd_status |= RD_ACTIVE; 602} 603 604static inline void rd_set_status(struct ring_descr *rd, u8 s) 605{ 606 rd->hw->rd_status = s; /* may pass ownership to the hardware */ 607} 608 609static inline void rd_set_addr_status(struct ring_descr *rd, dma_addr_t a, u8 s) 610{ 611 /* order is important for two reasons: 612 * - overlayed: writing addr overwrites status 613 * - we want to write status last so we have valid address in 614 * case status has RD_ACTIVE set 615 */ 616 617 if ((a & ~DMA_MASK_MSTRPAGE)>>24 != MSTRPAGE_VALUE) { 618 IRDA_ERROR("%s: pci busaddr inconsistency!\n", __func__); 619 dump_stack(); 620 return; 621 } 622 623 a &= DMA_MASK_MSTRPAGE; /* clear highbyte to make sure we won't write 624 * to status - just in case MSTRPAGE_VALUE!=0 625 */ 626 rd->hw->rd_addr = cpu_to_le32(a); 627 wmb(); 628 rd_set_status(rd, s); /* may pass ownership to the hardware */ 629} 630 631static inline void rd_set_count(struct ring_descr *rd, u16 c) 632{ 633 rd->hw->rd_count = cpu_to_le16(c); 634} 635 636static inline u8 rd_get_status(struct ring_descr *rd) 637{ 638 return rd->hw->rd_status; 639} 640 641static inline dma_addr_t rd_get_addr(struct ring_descr *rd) 642{ 643 dma_addr_t a; 644 645 a = le32_to_cpu(rd->hw->rd_addr); 646 return (a & DMA_MASK_MSTRPAGE) | (MSTRPAGE_VALUE << 24); 647} 648 649static inline u16 rd_get_count(struct ring_descr *rd) 650{ 651 return le16_to_cpu(rd->hw->rd_count); 652} 653 654/******************************************************************/ 655 656/* sw descriptor rings for rx, tx: 657 * 658 * operations follow producer-consumer paradigm, with the hw 659 * in the middle doing the processing. 660 * ring size must be power of two. 661 * 662 * producer advances r->tail after inserting for processing 663 * consumer advances r->head after removing processed rd 664 * ring is empty if head==tail / full if (tail+1)==head 665 */ 666 667struct vlsi_ring { 668 struct pci_dev *pdev; 669 int dir; 670 unsigned len; 671 unsigned size; 672 unsigned mask; 673 atomic_t head, tail; 674 struct ring_descr *rd; 675}; 676 677/* ring processing helpers */ 678 679static inline struct ring_descr *ring_last(struct vlsi_ring *r) 680{ 681 int t; 682 683 t = atomic_read(&r->tail) & r->mask; 684 return (((t+1) & r->mask) == (atomic_read(&r->head) & r->mask)) ? NULL : &r->rd[t]; 685} 686 687static inline struct ring_descr *ring_put(struct vlsi_ring *r) 688{ 689 atomic_inc(&r->tail); 690 return ring_last(r); 691} 692 693static inline struct ring_descr *ring_first(struct vlsi_ring *r) 694{ 695 int h; 696 697 h = atomic_read(&r->head) & r->mask; 698 return (h == (atomic_read(&r->tail) & r->mask)) ? NULL : &r->rd[h]; 699} 700 701static inline struct ring_descr *ring_get(struct vlsi_ring *r) 702{ 703 atomic_inc(&r->head); 704 return ring_first(r); 705} 706 707/******************************************************************/ 708 709/* our private compound VLSI-PCI-IRDA device information */ 710 711typedef struct vlsi_irda_dev { 712 struct pci_dev *pdev; 713 714 struct irlap_cb *irlap; 715 716 struct qos_info qos; 717 718 unsigned mode; 719 int baud, new_baud; 720 721 dma_addr_t busaddr; 722 void *virtaddr; 723 struct vlsi_ring *tx_ring, *rx_ring; 724 725 struct timeval last_rx; 726 727 spinlock_t lock; 728 struct mutex mtx; 729 730 u8 resume_ok; 731 struct proc_dir_entry *proc_entry; 732 733} vlsi_irda_dev_t; 734 735/********************************************************/ 736 737/* the remapped error flags we use for returning from frame 738 * post-processing in vlsi_process_tx/rx() after it was completed 739 * by the hardware. These functions either return the >=0 number 740 * of transferred bytes in case of success or the negative (-) 741 * of the or'ed error flags. 742 */ 743 744#define VLSI_TX_DROP 0x0001 745#define VLSI_TX_FIFO 0x0002 746 747#define VLSI_RX_DROP 0x0100 748#define VLSI_RX_OVER 0x0200 749#define VLSI_RX_LENGTH 0x0400 750#define VLSI_RX_FRAME 0x0800 751#define VLSI_RX_CRC 0x1000 752 753/********************************************************/ 754 755#endif /* IRDA_VLSI_FIR_H */ 756 757