1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL92C_REG_H__ 27#define __RTL92C_REG_H__ 28 29#define TXPKT_BUF_SELECT 0x69 30#define RXPKT_BUF_SELECT 0xA5 31#define DISABLE_TRXPKT_BUF_ACCESS 0x0 32 33#define REG_SYS_ISO_CTRL 0x0000 34#define REG_SYS_FUNC_EN 0x0002 35#define REG_APS_FSMCO 0x0004 36#define REG_SYS_CLKR 0x0008 37#define REG_9346CR 0x000A 38#define REG_EE_VPD 0x000C 39#define REG_AFE_MISC 0x0010 40#define REG_SPS0_CTRL 0x0011 41#define REG_SPS_OCP_CFG 0x0018 42#define REG_RSV_CTRL 0x001C 43#define REG_RF_CTRL 0x001F 44#define REG_LDOA15_CTRL 0x0020 45#define REG_LDOV12D_CTRL 0x0021 46#define REG_LDOHCI12_CTRL 0x0022 47#define REG_LPLDO_CTRL 0x0023 48#define REG_AFE_XTAL_CTRL 0x0024 49/* 1.5v for 8188EE test chip, 1.4v for MP chip */ 50#define REG_AFE_LDO_CTRL 0x0027 51#define REG_AFE_PLL_CTRL 0x0028 52#define REG_EFUSE_CTRL 0x0030 53#define REG_EFUSE_TEST 0x0034 54#define REG_PWR_DATA 0x0038 55#define REG_CAL_TIMER 0x003C 56#define REG_ACLK_MON 0x003E 57#define REG_GPIO_MUXCFG 0x0040 58#define REG_GPIO_IO_SEL 0x0042 59#define REG_MAC_PINMUX_CFG 0x0043 60#define REG_GPIO_PIN_CTRL 0x0044 61#define REG_GPIO_INTM 0x0048 62#define REG_LEDCFG0 0x004C 63#define REG_LEDCFG1 0x004D 64#define REG_LEDCFG2 0x004E 65#define REG_LEDCFG3 0x004F 66#define REG_FSIMR 0x0050 67#define REG_FSISR 0x0054 68#define REG_HSIMR 0x0058 69#define REG_HSISR 0x005c 70#define REG_GPIO_PIN_CTRL_2 0x0060 71#define REG_GPIO_IO_SEL_2 0x0062 72#define REG_GPIO_OUTPUT 0x006c 73#define REG_AFE_XTAL_CTRL_EXT 0x0078 74#define REG_XCK_OUT_CTRL 0x007c 75#define REG_MCUFWDL 0x0080 76#define REG_WOL_EVENT 0x0081 77#define REG_MCUTSTCFG 0x0084 78 79#define REG_HIMR 0x00B0 80#define REG_HISR 0x00B4 81#define REG_HIMRE 0x00B8 82#define REG_HISRE 0x00BC 83 84#define REG_EFUSE_ACCESS 0x00CF 85 86#define REG_BIST_SCAN 0x00D0 87#define REG_BIST_RPT 0x00D4 88#define REG_BIST_ROM_RPT 0x00D8 89#define REG_USB_SIE_INTF 0x00E0 90#define REG_PCIE_MIO_INTF 0x00E4 91#define REG_PCIE_MIO_INTD 0x00E8 92#define REG_HPON_FSM 0x00EC 93#define REG_SYS_CFG 0x00F0 94 95#define REG_CR 0x0100 96#define REG_PBP 0x0104 97#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 98#define REG_TRXDMA_CTRL 0x010C 99#define REG_TRXFF_BNDY 0x0114 100#define REG_TRXFF_STATUS 0x0118 101#define REG_RXFF_PTR 0x011C 102 103#define REG_CPWM 0x012F 104#define REG_FWIMR 0x0130 105#define REG_FWISR 0x0134 106#define REG_PKTBUF_DBG_CTRL 0x0140 107#define REG_PKTBUF_DBG_DATA_L 0x0144 108#define REG_PKTBUF_DBG_DATA_H 0x0148 109#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 110 111#define REG_TC0_CTRL 0x0150 112#define REG_TC1_CTRL 0x0154 113#define REG_TC2_CTRL 0x0158 114#define REG_TC3_CTRL 0x015C 115#define REG_TC4_CTRL 0x0160 116#define REG_TCUNIT_BASE 0x0164 117#define REG_MBIST_START 0x0174 118#define REG_MBIST_DONE 0x0178 119#define REG_MBIST_FAIL 0x017C 120#define REG_32K_CTRL 0x0194 121#define REG_C2HEVT_MSG_NORMAL 0x01A0 122#define REG_C2HEVT_CLEAR 0x01AF 123#define REG_C2HEVT_MSG_TEST 0x01B8 124#define REG_MCUTST_1 0x01c0 125#define REG_FMETHR 0x01C8 126#define REG_HMETFR 0x01CC 127#define REG_HMEBOX_0 0x01D0 128#define REG_HMEBOX_1 0x01D4 129#define REG_HMEBOX_2 0x01D8 130#define REG_HMEBOX_3 0x01DC 131 132#define REG_LLT_INIT 0x01E0 133#define REG_BB_ACCEESS_CTRL 0x01E8 134#define REG_BB_ACCESS_DATA 0x01EC 135 136#define REG_HMEBOX_EXT_0 0x01F0 137#define REG_HMEBOX_EXT_1 0x01F4 138#define REG_HMEBOX_EXT_2 0x01F8 139#define REG_HMEBOX_EXT_3 0x01FC 140 141#define REG_RQPN 0x0200 142#define REG_FIFOPAGE 0x0204 143#define REG_TDECTRL 0x0208 144#define REG_TXDMA_OFFSET_CHK 0x020C 145#define REG_TXDMA_STATUS 0x0210 146#define REG_RQPN_NPQ 0x0214 147 148#define REG_RXDMA_AGG_PG_TH 0x0280 149/* FW shall update this register before 150 * FW write RXPKT_RELEASE_POLL to 1 151 */ 152#define REG_FW_UPD_RDPTR 0x0284 153/* Control the RX DMA.*/ 154#define REG_RXDMA_CONTROL 0x0286 155/* The number of packets in RXPKTBUF. */ 156#define REG_RXPKT_NUM 0x0287 157 158#define REG_PCIE_CTRL_REG 0x0300 159#define REG_INT_MIG 0x0304 160#define REG_BCNQ_DESA 0x0308 161#define REG_HQ_DESA 0x0310 162#define REG_MGQ_DESA 0x0318 163#define REG_VOQ_DESA 0x0320 164#define REG_VIQ_DESA 0x0328 165#define REG_BEQ_DESA 0x0330 166#define REG_BKQ_DESA 0x0338 167#define REG_RX_DESA 0x0340 168 169#define REG_DBI 0x0348 170#define REG_MDIO 0x0354 171#define REG_DBG_SEL 0x0360 172#define REG_PCIE_HRPWM 0x0361 173#define REG_PCIE_HCPWM 0x0363 174#define REG_UART_CTRL 0x0364 175#define REG_WATCH_DOG 0x0368 176#define REG_UART_TX_DESA 0x0370 177#define REG_UART_RX_DESA 0x0378 178 179#define REG_HDAQ_DESA_NODEF 0x0000 180#define REG_CMDQ_DESA_NODEF 0x0000 181 182#define REG_VOQ_INFORMATION 0x0400 183#define REG_VIQ_INFORMATION 0x0404 184#define REG_BEQ_INFORMATION 0x0408 185#define REG_BKQ_INFORMATION 0x040C 186#define REG_MGQ_INFORMATION 0x0410 187#define REG_HGQ_INFORMATION 0x0414 188#define REG_BCNQ_INFORMATION 0x0418 189#define REG_TXPKT_EMPTY 0x041A 190 191#define REG_CPU_MGQ_INFORMATION 0x041C 192#define REG_FWHW_TXQ_CTRL 0x0420 193#define REG_HWSEQ_CTRL 0x0423 194#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 195#define REG_TXPKTBUF_MGQ_BDNY 0x0425 196#define REG_MULTI_BCNQ_EN 0x0426 197#define REG_MULTI_BCNQ_OFFSET 0x0427 198#define REG_SPEC_SIFS 0x0428 199#define REG_RL 0x042A 200#define REG_DARFRC 0x0430 201#define REG_RARFRC 0x0438 202#define REG_RRSR 0x0440 203#define REG_ARFR0 0x0444 204#define REG_ARFR1 0x0448 205#define REG_ARFR2 0x044C 206#define REG_ARFR3 0x0450 207#define REG_AGGLEN_LMT 0x0458 208#define REG_AMPDU_MIN_SPACE 0x045C 209#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 210#define REG_FAST_EDCA_CTRL 0x0460 211#define REG_RD_RESP_PKT_TH 0x0463 212#define REG_INIRTS_RATE_SEL 0x0480 213#define REG_INIDATA_RATE_SEL 0x0484 214#define REG_POWER_STATUS 0x04A4 215#define REG_POWER_STAGE1 0x04B4 216#define REG_POWER_STAGE2 0x04B8 217#define REG_PKT_LIFE_TIME 0x04C0 218#define REG_STBC_SETTING 0x04C4 219#define REG_PROT_MODE_CTRL 0x04C8 220#define REG_BAR_MODE_CTRL 0x04CC 221#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 222#define REG_EARLY_MODE_CONTROL 0x04D0 223#define REG_NQOS_SEQ 0x04DC 224#define REG_QOS_SEQ 0x04DE 225#define REG_NEED_CPU_HANDLE 0x04E0 226#define REG_PKT_LOSE_RPT 0x04E1 227#define REG_PTCL_ERR_STATUS 0x04E2 228#define REG_TX_RPT_CTRL 0x04EC 229#define REG_TX_RPT_TIME 0x04F0 230#define REG_DUMMY 0x04FC 231 232#define REG_EDCA_VO_PARAM 0x0500 233#define REG_EDCA_VI_PARAM 0x0504 234#define REG_EDCA_BE_PARAM 0x0508 235#define REG_EDCA_BK_PARAM 0x050C 236#define REG_BCNTCFG 0x0510 237#define REG_PIFS 0x0512 238#define REG_RDG_PIFS 0x0513 239#define REG_SIFS_CTX 0x0514 240#define REG_SIFS_TRX 0x0516 241#define REG_AGGR_BREAK_TIME 0x051A 242#define REG_SLOT 0x051B 243#define REG_TX_PTCL_CTRL 0x0520 244#define REG_TXPAUSE 0x0522 245#define REG_DIS_TXREQ_CLR 0x0523 246#define REG_RD_CTRL 0x0524 247#define REG_TBTT_PROHIBIT 0x0540 248#define REG_RD_NAV_NXT 0x0544 249#define REG_NAV_PROT_LEN 0x0546 250#define REG_BCN_CTRL 0x0550 251#define REG_USTIME_TSF 0x0551 252#define REG_MBID_NUM 0x0552 253#define REG_DUAL_TSF_RST 0x0553 254#define REG_BCN_INTERVAL 0x0554 255#define REG_MBSSID_BCN_SPACE 0x0554 256#define REG_DRVERLYINT 0x0558 257#define REG_BCNDMATIM 0x0559 258#define REG_ATIMWND 0x055A 259#define REG_BCN_MAX_ERR 0x055D 260#define REG_RXTSF_OFFSET_CCK 0x055E 261#define REG_RXTSF_OFFSET_OFDM 0x055F 262#define REG_TSFTR 0x0560 263#define REG_INIT_TSFTR 0x0564 264#define REG_PSTIMER 0x0580 265#define REG_TIMER0 0x0584 266#define REG_TIMER1 0x0588 267#define REG_ACMHWCTRL 0x05C0 268#define REG_ACMRSTCTRL 0x05C1 269#define REG_ACMAVG 0x05C2 270#define REG_VO_ADMTIME 0x05C4 271#define REG_VI_ADMTIME 0x05C6 272#define REG_BE_ADMTIME 0x05C8 273#define REG_EDCA_RANDOM_GEN 0x05CC 274#define REG_SCH_TXCMD 0x05D0 275 276#define REG_APSD_CTRL 0x0600 277#define REG_BWOPMODE 0x0603 278#define REG_TCR 0x0604 279#define REG_RCR 0x0608 280#define REG_RX_PKT_LIMIT 0x060C 281#define REG_RX_DLK_TIME 0x060D 282#define REG_RX_DRVINFO_SZ 0x060F 283 284#define REG_MACID 0x0610 285#define REG_BSSID 0x0618 286#define REG_MAR 0x0620 287#define REG_MBIDCAMCFG 0x0628 288 289#define REG_USTIME_EDCA 0x0638 290#define REG_MAC_SPEC_SIFS 0x063A 291#define REG_RESP_SIFS_CCK 0x063C 292#define REG_RESP_SIFS_OFDM 0x063E 293#define REG_ACKTO 0x0640 294#define REG_CTS2TO 0x0641 295#define REG_EIFS 0x0642 296 297#define REG_NAV_CTRL 0x0650 298#define REG_BACAMCMD 0x0654 299#define REG_BACAMCONTENT 0x0658 300#define REG_LBDLY 0x0660 301#define REG_FWDLY 0x0661 302#define REG_RXERR_RPT 0x0664 303#define REG_TRXPTCL_CTL 0x0668 304 305#define REG_CAMCMD 0x0670 306#define REG_CAMWRITE 0x0674 307#define REG_CAMREAD 0x0678 308#define REG_CAMDBG 0x067C 309#define REG_SECCFG 0x0680 310 311#define REG_WOW_CTRL 0x0690 312#define REG_PSSTATUS 0x0691 313#define REG_PS_RX_INFO 0x0692 314#define REG_UAPSD_TID 0x0693 315#define REG_LPNAV_CTRL 0x0694 316#define REG_WKFMCAM_NUM 0x0698 317#define REG_WKFMCAM_RWD 0x069C 318#define REG_RXFLTMAP0 0x06A0 319#define REG_RXFLTMAP1 0x06A2 320#define REG_RXFLTMAP2 0x06A4 321#define REG_BCN_PSR_RPT 0x06A8 322#define REG_CALB32K_CTRL 0x06AC 323#define REG_PKT_MON_CTRL 0x06B4 324#define REG_BT_COEX_TABLE 0x06C0 325#define REG_WMAC_RESP_TXINFO 0x06D8 326 327#define REG_USB_INFO 0xFE17 328#define REG_USB_SPECIAL_OPTION 0xFE55 329#define REG_USB_DMA_AGG_TO 0xFE5B 330#define REG_USB_AGG_TO 0xFE5C 331#define REG_USB_AGG_TH 0xFE5D 332 333#define REG_TEST_USB_TXQS 0xFE48 334#define REG_TEST_SIE_VID 0xFE60 335#define REG_TEST_SIE_PID 0xFE62 336#define REG_TEST_SIE_OPTIONAL 0xFE64 337#define REG_TEST_SIE_CHIRP_K 0xFE65 338#define REG_TEST_SIE_PHY 0xFE66 339#define REG_TEST_SIE_MAC_ADDR 0xFE70 340#define REG_TEST_SIE_STRING 0xFE80 341 342#define REG_NORMAL_SIE_VID 0xFE60 343#define REG_NORMAL_SIE_PID 0xFE62 344#define REG_NORMAL_SIE_OPTIONAL 0xFE64 345#define REG_NORMAL_SIE_EP 0xFE65 346#define REG_NORMAL_SIE_PHY 0xFE68 347#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 348#define REG_NORMAL_SIE_STRING 0xFE80 349 350#define CR9346 REG_9346CR 351#define MSR (REG_CR + 2) 352#define ISR REG_HISR 353#define TSFR REG_TSFTR 354 355#define MACIDR0 REG_MACID 356#define MACIDR4 (REG_MACID + 4) 357 358#define PBP REG_PBP 359 360#define IDR0 MACIDR0 361#define IDR4 MACIDR4 362 363#define UNUSED_REGISTER 0x1BF 364#define DCAM UNUSED_REGISTER 365#define PSR UNUSED_REGISTER 366#define BBADDR UNUSED_REGISTER 367#define PHYDATAR UNUSED_REGISTER 368 369#define INVALID_BBRF_VALUE 0x12345678 370 371#define MAX_MSS_DENSITY_2T 0x13 372#define MAX_MSS_DENSITY_1T 0x0A 373 374#define CMDEEPROM_EN BIT(5) 375#define CMDEEPROM_SEL BIT(4) 376#define CMD9346CR_9356SEL BIT(4) 377#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 378#define AUTOLOAD_EFUSE CMDEEPROM_EN 379 380#define GPIOSEL_GPIO 0 381#define GPIOSEL_ENBT BIT(5) 382 383#define GPIO_IN REG_GPIO_PIN_CTRL 384#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 385#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 386#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 387 388/*8723/8188E Host System Interrupt 389 *Mask Register (offset 0x58, 32 byte) 390 */ 391#define HSIMR_GPIO12_0_INT_EN BIT(0) 392#define HSIMR_SPS_OCP_INT_EN BIT(5) 393#define HSIMR_RON_INT_EN BIT(6) 394#define HSIMR_PDN_INT_EN BIT(7) 395#define HSIMR_GPIO9_INT_EN BIT(25) 396 397/* 8723/8188E Host System Interrupt 398 * Status Register (offset 0x5C, 32 byte) 399 */ 400#define HSISR_GPIO12_0_INT BIT(0) 401#define HSISR_SPS_OCP_INT BIT(5) 402#define HSISR_RON_INT_EN BIT(6) 403#define HSISR_PDNINT BIT(7) 404#define HSISR_GPIO9_INT BIT(25) 405 406#define MSR_NOLINK 0x00 407#define MSR_ADHOC 0x01 408#define MSR_INFRA 0x02 409#define MSR_AP 0x03 410 411#define RRSR_RSC_OFFSET 21 412#define RRSR_SHORT_OFFSET 23 413#define RRSR_RSC_BW_40M 0x600000 414#define RRSR_RSC_UPSUBCHNL 0x400000 415#define RRSR_RSC_LOWSUBCHNL 0x200000 416#define RRSR_SHORT 0x800000 417#define RRSR_1M BIT(0) 418#define RRSR_2M BIT(1) 419#define RRSR_5_5M BIT(2) 420#define RRSR_11M BIT(3) 421#define RRSR_6M BIT(4) 422#define RRSR_9M BIT(5) 423#define RRSR_12M BIT(6) 424#define RRSR_18M BIT(7) 425#define RRSR_24M BIT(8) 426#define RRSR_36M BIT(9) 427#define RRSR_48M BIT(10) 428#define RRSR_54M BIT(11) 429#define RRSR_MCS0 BIT(12) 430#define RRSR_MCS1 BIT(13) 431#define RRSR_MCS2 BIT(14) 432#define RRSR_MCS3 BIT(15) 433#define RRSR_MCS4 BIT(16) 434#define RRSR_MCS5 BIT(17) 435#define RRSR_MCS6 BIT(18) 436#define RRSR_MCS7 BIT(19) 437#define BRSR_ACKSHORTPMB BIT(23) 438 439#define RATR_1M 0x00000001 440#define RATR_2M 0x00000002 441#define RATR_55M 0x00000004 442#define RATR_11M 0x00000008 443#define RATR_6M 0x00000010 444#define RATR_9M 0x00000020 445#define RATR_12M 0x00000040 446#define RATR_18M 0x00000080 447#define RATR_24M 0x00000100 448#define RATR_36M 0x00000200 449#define RATR_48M 0x00000400 450#define RATR_54M 0x00000800 451#define RATR_MCS0 0x00001000 452#define RATR_MCS1 0x00002000 453#define RATR_MCS2 0x00004000 454#define RATR_MCS3 0x00008000 455#define RATR_MCS4 0x00010000 456#define RATR_MCS5 0x00020000 457#define RATR_MCS6 0x00040000 458#define RATR_MCS7 0x00080000 459#define RATR_MCS8 0x00100000 460#define RATR_MCS9 0x00200000 461#define RATR_MCS10 0x00400000 462#define RATR_MCS11 0x00800000 463#define RATR_MCS12 0x01000000 464#define RATR_MCS13 0x02000000 465#define RATR_MCS14 0x04000000 466#define RATR_MCS15 0x08000000 467 468#define RATE_1M BIT(0) 469#define RATE_2M BIT(1) 470#define RATE_5_5M BIT(2) 471#define RATE_11M BIT(3) 472#define RATE_6M BIT(4) 473#define RATE_9M BIT(5) 474#define RATE_12M BIT(6) 475#define RATE_18M BIT(7) 476#define RATE_24M BIT(8) 477#define RATE_36M BIT(9) 478#define RATE_48M BIT(10) 479#define RATE_54M BIT(11) 480#define RATE_MCS0 BIT(12) 481#define RATE_MCS1 BIT(13) 482#define RATE_MCS2 BIT(14) 483#define RATE_MCS3 BIT(15) 484#define RATE_MCS4 BIT(16) 485#define RATE_MCS5 BIT(17) 486#define RATE_MCS6 BIT(18) 487#define RATE_MCS7 BIT(19) 488#define RATE_MCS8 BIT(20) 489#define RATE_MCS9 BIT(21) 490#define RATE_MCS10 BIT(22) 491#define RATE_MCS11 BIT(23) 492#define RATE_MCS12 BIT(24) 493#define RATE_MCS13 BIT(25) 494#define RATE_MCS14 BIT(26) 495#define RATE_MCS15 BIT(27) 496 497#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 498#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 499 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 500#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 501 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 502 RATR_MCS6 | RATR_MCS7) 503#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 504 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 505 RATR_MCS14 | RATR_MCS15) 506 507#define BW_OPMODE_20MHZ BIT(2) 508#define BW_OPMODE_5G BIT(1) 509#define BW_OPMODE_11J BIT(0) 510 511#define CAM_VALID BIT(15) 512#define CAM_NOTVALID 0x0000 513#define CAM_USEDK BIT(5) 514 515#define CAM_NONE 0x0 516#define CAM_WEP40 0x01 517#define CAM_TKIP 0x02 518#define CAM_AES 0x04 519#define CAM_WEP104 0x05 520 521#define TOTAL_CAM_ENTRY 32 522#define HALF_CAM_ENTRY 16 523 524#define CAM_WRITE BIT(16) 525#define CAM_READ 0x00000000 526#define CAM_POLLINIG BIT(31) 527 528#define SCR_USEDK 0x01 529#define SCR_TXSEC_ENABLE 0x02 530#define SCR_RXSEC_ENABLE 0x04 531 532#define WOW_PMEN BIT(0) 533#define WOW_WOMEN BIT(1) 534#define WOW_MAGIC BIT(2) 535#define WOW_UWF BIT(3) 536 537/********************************************* 538* 8188 IMR/ISR bits 539**********************************************/ 540#define IMR_DISABLED 0x0 541/* IMR DW0(0x0060-0063) Bit 0-31 */ 542/* TXRPT interrupt when CCX bit of the packet is set */ 543#define IMR_TXCCK BIT(30) 544/* Power Save Time Out Interrupt */ 545#define IMR_PSTIMEOUT BIT(29) 546/* When GTIMER4 expires, this bit is set to 1 */ 547#define IMR_GTINT4 BIT(28) 548/* When GTIMER3 expires, this bit is set to 1 */ 549#define IMR_GTINT3 BIT(27) 550/* Transmit Beacon0 Error */ 551#define IMR_TBDER BIT(26) 552/* Transmit Beacon0 OK */ 553#define IMR_TBDOK BIT(25) 554/* TSF Timer BIT32 toggle indication interrupt */ 555#define IMR_TSF_BIT32_TOGGLE BIT(24) 556/* Beacon DMA Interrupt 0 */ 557#define IMR_BCNDMAINT0 BIT(20) 558/* Beacon Queue DMA OK0 */ 559#define IMR_BCNDOK0 BIT(16) 560/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 561#define IMR_HSISR_IND_ON_INT BIT(15) 562/* Beacon DMA Interrupt Extension for Win7 */ 563#define IMR_BCNDMAINT_E BIT(14) 564/* CTWidnow End or ATIM Window End */ 565#define IMR_ATIMEND BIT(12) 566/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/ 567#define IMR_HISR1_IND_INT BIT(11) 568/* CPU to Host Command INT Status, Write 1 clear */ 569#define IMR_C2HCMD BIT(10) 570/* CPU power Mode exchange INT Status, Write 1 clear */ 571#define IMR_CPWM2 BIT(9) 572/* CPU power Mode exchange INT Status, Write 1 clear */ 573#define IMR_CPWM BIT(8) 574/* High Queue DMA OK */ 575#define IMR_HIGHDOK BIT(7) 576/* Management Queue DMA OK */ 577#define IMR_MGNTDOK BIT(6) 578/* AC_BK DMA OK */ 579#define IMR_BKDOK BIT(5) 580/* AC_BE DMA OK */ 581#define IMR_BEDOK BIT(4) 582/* AC_VI DMA OK */ 583#define IMR_VIDOK BIT(3) 584/* AC_VO DMA OK */ 585#define IMR_VODOK BIT(2) 586/* Rx Descriptor Unavailable */ 587#define IMR_RDU BIT(1) 588/* Receive DMA OK */ 589#define IMR_ROK BIT(0) 590 591/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 592/* Beacon DMA Interrupt 7 */ 593#define IMR_BCNDMAINT7 BIT(27) 594/* Beacon DMA Interrupt 6 */ 595#define IMR_BCNDMAINT6 BIT(26) 596/* Beacon DMA Interrupt 5 */ 597#define IMR_BCNDMAINT5 BIT(25) 598/* Beacon DMA Interrupt 4 */ 599#define IMR_BCNDMAINT4 BIT(24) 600/* Beacon DMA Interrupt 3 */ 601#define IMR_BCNDMAINT3 BIT(23) 602/* Beacon DMA Interrupt 2 */ 603#define IMR_BCNDMAINT2 BIT(22) 604/* Beacon DMA Interrupt 1 */ 605#define IMR_BCNDMAINT1 BIT(21) 606/* Beacon Queue DMA OK Interrup 7 */ 607#define IMR_BCNDOK7 BIT(20) 608/* Beacon Queue DMA OK Interrup 6 */ 609#define IMR_BCNDOK6 BIT(19) 610/* Beacon Queue DMA OK Interrup 5 */ 611#define IMR_BCNDOK5 BIT(18) 612/* Beacon Queue DMA OK Interrup 4 */ 613#define IMR_BCNDOK4 BIT(17) 614/* Beacon Queue DMA OK Interrup 3 */ 615#define IMR_BCNDOK3 BIT(16) 616/* Beacon Queue DMA OK Interrup 2 */ 617#define IMR_BCNDOK2 BIT(15) 618/* Beacon Queue DMA OK Interrup 1 */ 619#define IMR_BCNDOK1 BIT(14) 620/* ATIM Window End Extension for Win7 */ 621#define IMR_ATIMEND_E BIT(13) 622/* Tx Error Flag Interrupt Status, write 1 clear. */ 623#define IMR_TXERR BIT(11) 624/* Rx Error Flag INT Status, Write 1 clear */ 625#define IMR_RXERR BIT(10) 626/* Transmit FIFO Overflow */ 627#define IMR_TXFOVW BIT(9) 628/* Receive FIFO Overflow */ 629#define IMR_RXFOVW BIT(8) 630 631#define HWSET_MAX_SIZE 512 632#define EFUSE_MAX_SECTION 64 633#define EFUSE_REAL_CONTENT_LEN 256 634/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/ 635#define EFUSE_OOB_PROTECT_BYTES 18 636 637#define EEPROM_DEFAULT_TSSI 0x0 638#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 639#define EEPROM_DEFAULT_CRYSTALCAP 0x5 640#define EEPROM_DEFAULT_BOARDTYPE 0x02 641#define EEPROM_DEFAULT_TXPOWER 0x1010 642#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 643 644#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 645#define EEPROM_DEFAULT_THERMALMETER 0x18 646#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 647#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 648#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 649#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 650#define EEPROM_DEFAULT_HT20_DIFF 2 651#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 652#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 653#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 654 655#define RF_OPTION1 0x79 656#define RF_OPTION2 0x7A 657#define RF_OPTION3 0x7B 658#define RF_OPTION4 0x7C 659 660#define EEPROM_DEFAULT_PID 0x1234 661#define EEPROM_DEFAULT_VID 0x5678 662#define EEPROM_DEFAULT_CUSTOMERID 0xAB 663#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 664#define EEPROM_DEFAULT_VERSION 0 665 666#define EEPROM_CHANNEL_PLAN_FCC 0x0 667#define EEPROM_CHANNEL_PLAN_IC 0x1 668#define EEPROM_CHANNEL_PLAN_ETSI 0x2 669#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 670#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 671#define EEPROM_CHANNEL_PLAN_MKK 0x5 672#define EEPROM_CHANNEL_PLAN_MKK1 0x6 673#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 674#define EEPROM_CHANNEL_PLAN_TELEC 0x8 675#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 676#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 677#define EEPROM_CHANNEL_PLAN_NCC 0xB 678#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 679 680#define EEPROM_CID_DEFAULT 0x0 681#define EEPROM_CID_TOSHIBA 0x4 682#define EEPROM_CID_CCX 0x10 683#define EEPROM_CID_QMI 0x0D 684#define EEPROM_CID_WHQL 0xFE 685 686#define RTL8188E_EEPROM_ID 0x8129 687 688#define EEPROM_HPON 0x02 689#define EEPROM_CLK 0x06 690#define EEPROM_TESTR 0x08 691 692#define EEPROM_TXPOWERCCK 0x10 693#define EEPROM_TXPOWERHT40_1S 0x16 694#define EEPROM_TXPOWERHT20DIFF 0x1B 695#define EEPROM_TXPOWER_OFDMDIFF 0x1B 696 697#define EEPROM_TX_PWR_INX 0x10 698 699#define EEPROM_CHANNELPLAN 0xB8 700#define EEPROM_XTAL_88E 0xB9 701#define EEPROM_THERMAL_METER_88E 0xBA 702#define EEPROM_IQK_LCK_88E 0xBB 703 704#define EEPROM_RF_BOARD_OPTION_88E 0xC1 705#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 706#define EEPROM_RF_BT_SETTING_88E 0xC3 707#define EEPROM_VERSION 0xC4 708#define EEPROM_CUSTOMER_ID 0xC5 709#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 710 711#define EEPROM_MAC_ADDR 0xD0 712#define EEPROM_VID 0xD6 713#define EEPROM_DID 0xD8 714#define EEPROM_SVID 0xDA 715#define EEPROM_SMID 0xDC 716 717#define STOPBECON BIT(6) 718#define STOPHIGHT BIT(5) 719#define STOPMGT BIT(4) 720#define STOPVO BIT(3) 721#define STOPVI BIT(2) 722#define STOPBE BIT(1) 723#define STOPBK BIT(0) 724 725#define RCR_APPFCS BIT(31) 726#define RCR_APP_MIC BIT(30) 727#define RCR_APP_ICV BIT(29) 728#define RCR_APP_PHYST_RXFF BIT(28) 729#define RCR_APP_BA_SSN BIT(27) 730#define RCR_ENMBID BIT(24) 731#define RCR_LSIGEN BIT(23) 732#define RCR_MFBEN BIT(22) 733#define RCR_HTC_LOC_CTRL BIT(14) 734#define RCR_AMF BIT(13) 735#define RCR_ACF BIT(12) 736#define RCR_ADF BIT(11) 737#define RCR_AICV BIT(9) 738#define RCR_ACRC32 BIT(8) 739#define RCR_CBSSID_BCN BIT(7) 740#define RCR_CBSSID_DATA BIT(6) 741#define RCR_CBSSID RCR_CBSSID_DATA 742#define RCR_APWRMGT BIT(5) 743#define RCR_ADD3 BIT(4) 744#define RCR_AB BIT(3) 745#define RCR_AM BIT(2) 746#define RCR_APM BIT(1) 747#define RCR_AAP BIT(0) 748#define RCR_MXDMA_OFFSET 8 749#define RCR_FIFO_OFFSET 13 750 751#define RSV_CTRL 0x001C 752#define RD_CTRL 0x0524 753 754#define REG_USB_INFO 0xFE17 755#define REG_USB_SPECIAL_OPTION 0xFE55 756#define REG_USB_DMA_AGG_TO 0xFE5B 757#define REG_USB_AGG_TO 0xFE5C 758#define REG_USB_AGG_TH 0xFE5D 759 760#define REG_USB_VID 0xFE60 761#define REG_USB_PID 0xFE62 762#define REG_USB_OPTIONAL 0xFE64 763#define REG_USB_CHIRP_K 0xFE65 764#define REG_USB_PHY 0xFE66 765#define REG_USB_MAC_ADDR 0xFE70 766#define REG_USB_HRPWM 0xFE58 767#define REG_USB_HCPWM 0xFE57 768 769#define SW18_FPWM BIT(3) 770 771#define ISO_MD2PP BIT(0) 772#define ISO_UA2USB BIT(1) 773#define ISO_UD2CORE BIT(2) 774#define ISO_PA2PCIE BIT(3) 775#define ISO_PD2CORE BIT(4) 776#define ISO_IP2MAC BIT(5) 777#define ISO_DIOP BIT(6) 778#define ISO_DIOE BIT(7) 779#define ISO_EB2CORE BIT(8) 780#define ISO_DIOR BIT(9) 781 782#define PWC_EV25V BIT(14) 783#define PWC_EV12V BIT(15) 784 785#define FEN_BBRSTB BIT(0) 786#define FEN_BB_GLB_RSTN BIT(1) 787#define FEN_USBA BIT(2) 788#define FEN_UPLL BIT(3) 789#define FEN_USBD BIT(4) 790#define FEN_DIO_PCIE BIT(5) 791#define FEN_PCIEA BIT(6) 792#define FEN_PPLL BIT(7) 793#define FEN_PCIED BIT(8) 794#define FEN_DIOE BIT(9) 795#define FEN_CPUEN BIT(10) 796#define FEN_DCORE BIT(11) 797#define FEN_ELDR BIT(12) 798#define FEN_DIO_RF BIT(13) 799#define FEN_HWPDN BIT(14) 800#define FEN_MREGEN BIT(15) 801 802#define PFM_LDALL BIT(0) 803#define PFM_ALDN BIT(1) 804#define PFM_LDKP BIT(2) 805#define PFM_WOWL BIT(3) 806#define ENPDN BIT(4) 807#define PDN_PL BIT(5) 808#define APFM_ONMAC BIT(8) 809#define APFM_OFF BIT(9) 810#define APFM_RSM BIT(10) 811#define AFSM_HSUS BIT(11) 812#define AFSM_PCIE BIT(12) 813#define APDM_MAC BIT(13) 814#define APDM_HOST BIT(14) 815#define APDM_HPDN BIT(15) 816#define RDY_MACON BIT(16) 817#define SUS_HOST BIT(17) 818#define ROP_ALD BIT(20) 819#define ROP_PWR BIT(21) 820#define ROP_SPS BIT(22) 821#define SOP_MRST BIT(25) 822#define SOP_FUSE BIT(26) 823#define SOP_ABG BIT(27) 824#define SOP_AMB BIT(28) 825#define SOP_RCK BIT(29) 826#define SOP_A8M BIT(30) 827#define XOP_BTCK BIT(31) 828 829#define ANAD16V_EN BIT(0) 830#define ANA8M BIT(1) 831#define MACSLP BIT(4) 832#define LOADER_CLK_EN BIT(5) 833#define _80M_SSC_DIS BIT(7) 834#define _80M_SSC_EN_HO BIT(8) 835#define PHY_SSC_RSTB BIT(9) 836#define SEC_CLK_EN BIT(10) 837#define MAC_CLK_EN BIT(11) 838#define SYS_CLK_EN BIT(12) 839#define RING_CLK_EN BIT(13) 840 841#define BOOT_FROM_EEPROM BIT(4) 842#define EEPROM_EN BIT(5) 843 844#define AFE_BGEN BIT(0) 845#define AFE_MBEN BIT(1) 846#define MAC_ID_EN BIT(7) 847 848#define WLOCK_ALL BIT(0) 849#define WLOCK_00 BIT(1) 850#define WLOCK_04 BIT(2) 851#define WLOCK_08 BIT(3) 852#define WLOCK_40 BIT(4) 853#define R_DIS_PRST_0 BIT(5) 854#define R_DIS_PRST_1 BIT(6) 855#define LOCK_ALL_EN BIT(7) 856 857#define RF_EN BIT(0) 858#define RF_RSTB BIT(1) 859#define RF_SDMRSTB BIT(2) 860 861#define LDA15_EN BIT(0) 862#define LDA15_STBY BIT(1) 863#define LDA15_OBUF BIT(2) 864#define LDA15_REG_VOS BIT(3) 865#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 866 867#define LDV12_EN BIT(0) 868#define LDV12_SDBY BIT(1) 869#define LPLDO_HSM BIT(2) 870#define LPLDO_LSM_DIS BIT(3) 871#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 872 873#define XTAL_EN BIT(0) 874#define XTAL_BSEL BIT(1) 875#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 876#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 877#define XTAL_GATE_USB BIT(8) 878#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 879#define XTAL_GATE_AFE BIT(11) 880#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 881#define XTAL_RF_GATE BIT(14) 882#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 883#define XTAL_GATE_DIG BIT(17) 884#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 885#define XTAL_BT_GATE BIT(20) 886#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 887#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 888 889#define CKDLY_AFE BIT(26) 890#define CKDLY_USB BIT(27) 891#define CKDLY_DIG BIT(28) 892#define CKDLY_BT BIT(29) 893 894#define APLL_EN BIT(0) 895#define APLL_320_EN BIT(1) 896#define APLL_FREF_SEL BIT(2) 897#define APLL_EDGE_SEL BIT(3) 898#define APLL_WDOGB BIT(4) 899#define APLL_LPFEN BIT(5) 900 901#define APLL_REF_CLK_13MHZ 0x1 902#define APLL_REF_CLK_19_2MHZ 0x2 903#define APLL_REF_CLK_20MHZ 0x3 904#define APLL_REF_CLK_25MHZ 0x4 905#define APLL_REF_CLK_26MHZ 0x5 906#define APLL_REF_CLK_38_4MHZ 0x6 907#define APLL_REF_CLK_40MHZ 0x7 908 909#define APLL_320EN BIT(14) 910#define APLL_80EN BIT(15) 911#define APLL_1MEN BIT(24) 912 913#define ALD_EN BIT(18) 914#define EF_PD BIT(19) 915#define EF_FLAG BIT(31) 916 917#define EF_TRPT BIT(7) 918#define LDOE25_EN BIT(31) 919 920#define RSM_EN BIT(0) 921#define TIMER_EN BIT(4) 922 923#define TRSW0EN BIT(2) 924#define TRSW1EN BIT(3) 925#define EROM_EN BIT(4) 926#define ENBT BIT(5) 927#define ENUART BIT(8) 928#define UART_910 BIT(9) 929#define ENPMAC BIT(10) 930#define SIC_SWRST BIT(11) 931#define ENSIC BIT(12) 932#define SIC_23 BIT(13) 933#define ENHDP BIT(14) 934#define SIC_LBK BIT(15) 935 936#define LED0PL BIT(4) 937#define LED1PL BIT(12) 938#define LED0DIS BIT(7) 939 940#define MCUFWDL_EN BIT(0) 941#define MCUFWDL_RDY BIT(1) 942#define FWDL_CHKSUM_RPT BIT(2) 943#define MACINI_RDY BIT(3) 944#define BBINI_RDY BIT(4) 945#define RFINI_RDY BIT(5) 946#define WINTINI_RDY BIT(6) 947#define CPRST BIT(23) 948 949#define XCLK_VLD BIT(0) 950#define ACLK_VLD BIT(1) 951#define UCLK_VLD BIT(2) 952#define PCLK_VLD BIT(3) 953#define PCIRSTB BIT(4) 954#define V15_VLD BIT(5) 955#define TRP_B15V_EN BIT(7) 956#define SIC_IDLE BIT(8) 957#define BD_MAC2 BIT(9) 958#define BD_MAC1 BIT(10) 959#define IC_MACPHY_MODE BIT(11) 960#define VENDOR_ID BIT(19) 961#define PAD_HWPD_IDN BIT(22) 962#define TRP_VAUX_EN BIT(23) 963#define TRP_BT_EN BIT(24) 964#define BD_PKG_SEL BIT(25) 965#define BD_HCI_SEL BIT(26) 966#define TYPE_ID BIT(27) 967 968#define CHIP_VER_RTL_MASK 0xF000 969#define CHIP_VER_RTL_SHIFT 12 970 971#define REG_LBMODE (REG_CR + 3) 972 973#define HCI_TXDMA_EN BIT(0) 974#define HCI_RXDMA_EN BIT(1) 975#define TXDMA_EN BIT(2) 976#define RXDMA_EN BIT(3) 977#define PROTOCOL_EN BIT(4) 978#define SCHEDULE_EN BIT(5) 979#define MACTXEN BIT(6) 980#define MACRXEN BIT(7) 981#define ENSWBCN BIT(8) 982#define ENSEC BIT(9) 983 984#define _NETTYPE(x) (((x) & 0x3) << 16) 985#define MASK_NETTYPE 0x30000 986#define NT_NO_LINK 0x0 987#define NT_LINK_AD_HOC 0x1 988#define NT_LINK_AP 0x2 989#define NT_AS_AP 0x3 990 991#define _LBMODE(x) (((x) & 0xF) << 24) 992#define MASK_LBMODE 0xF000000 993#define LOOPBACK_NORMAL 0x0 994#define LOOPBACK_IMMEDIATELY 0xB 995#define LOOPBACK_MAC_DELAY 0x3 996#define LOOPBACK_PHY 0x1 997#define LOOPBACK_DMA 0x7 998 999#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 1000#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 1001#define _PSRX_MASK 0xF 1002#define _PSTX_MASK 0xF0 1003#define _PSRX(x) (x) 1004#define _PSTX(x) ((x) << 4) 1005 1006#define PBP_64 0x0 1007#define PBP_128 0x1 1008#define PBP_256 0x2 1009#define PBP_512 0x3 1010#define PBP_1024 0x4 1011 1012#define RXDMA_ARBBW_EN BIT(0) 1013#define RXSHFT_EN BIT(1) 1014#define RXDMA_AGG_EN BIT(2) 1015#define QS_VO_QUEUE BIT(8) 1016#define QS_VI_QUEUE BIT(9) 1017#define QS_BE_QUEUE BIT(10) 1018#define QS_BK_QUEUE BIT(11) 1019#define QS_MANAGER_QUEUE BIT(12) 1020#define QS_HIGH_QUEUE BIT(13) 1021 1022#define HQSEL_VOQ BIT(0) 1023#define HQSEL_VIQ BIT(1) 1024#define HQSEL_BEQ BIT(2) 1025#define HQSEL_BKQ BIT(3) 1026#define HQSEL_MGTQ BIT(4) 1027#define HQSEL_HIQ BIT(5) 1028 1029#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 1030#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 1031#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 1032#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 1033#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 1034#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 1035 1036#define QUEUE_LOW 1 1037#define QUEUE_NORMAL 2 1038#define QUEUE_HIGH 3 1039 1040#define _LLT_NO_ACTIVE 0x0 1041#define _LLT_WRITE_ACCESS 0x1 1042#define _LLT_READ_ACCESS 0x2 1043 1044#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1045#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1046#define _LLT_OP(x) (((x) & 0x3) << 30) 1047#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1048 1049#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1050#define BB_WRITE_EN BIT(30) 1051#define BB_READ_EN BIT(31) 1052 1053#define _HPQ(x) ((x) & 0xFF) 1054#define _LPQ(x) (((x) & 0xFF) << 8) 1055#define _PUBQ(x) (((x) & 0xFF) << 16) 1056#define _NPQ(x) ((x) & 0xFF) 1057 1058#define HPQ_PUBLIC_DIS BIT(24) 1059#define LPQ_PUBLIC_DIS BIT(25) 1060#define LD_RQPN BIT(31) 1061 1062#define BCN_VALID BIT(16) 1063#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1064#define BCN_HEAD_MASK 0xFF00 1065 1066#define BLK_DESC_NUM_SHIFT 4 1067#define BLK_DESC_NUM_MASK 0xF 1068 1069#define DROP_DATA_EN BIT(9) 1070 1071#define EN_AMPDU_RTY_NEW BIT(7) 1072 1073#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1074 1075#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1076#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1077 1078#define RATE_REG_BITMAP_ALL 0xFFFFF 1079 1080#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1081 1082#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1083#define RRSR_RSC_RESERVED 0x0 1084#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1085#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1086#define RRSR_RSC_DUPLICATE_MODE 0x3 1087 1088#define USE_SHORT_G1 BIT(20) 1089 1090#define _AGGLMT_MCS0(x) ((x) & 0xF) 1091#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1092#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1093#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1094#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1095#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1096#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1097#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1098 1099#define RETRY_LIMIT_SHORT_SHIFT 8 1100#define RETRY_LIMIT_LONG_SHIFT 0 1101 1102#define _DARF_RC1(x) ((x) & 0x1F) 1103#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1104#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1105#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1106#define _DARF_RC5(x) ((x) & 0x1F) 1107#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1108#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1109#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1110 1111#define _RARF_RC1(x) ((x) & 0x1F) 1112#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1113#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1114#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1115#define _RARF_RC5(x) ((x) & 0x1F) 1116#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1117#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1118#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1119 1120#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1121#define AC_PARAM_ECW_MAX_OFFSET 12 1122#define AC_PARAM_ECW_MIN_OFFSET 8 1123#define AC_PARAM_AIFS_OFFSET 0 1124 1125#define _AIFS(x) (x) 1126#define _ECW_MAX_MIN(x) ((x) << 8) 1127#define _TXOP_LIMIT(x) ((x) << 16) 1128 1129#define _BCNIFS(x) ((x) & 0xFF) 1130#define _BCNECW(x) ((((x) & 0xF)) << 8) 1131 1132#define _LRL(x) ((x) & 0x3F) 1133#define _SRL(x) (((x) & 0x3F) << 8) 1134 1135#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1136#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); 1137 1138#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1139#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); 1140 1141#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1142 1143#define DIS_EDCA_CNT_DWN BIT(11) 1144 1145#define EN_MBSSID BIT(1) 1146#define EN_TXBCN_RPT BIT(2) 1147#define EN_BCN_FUNCTION BIT(3) 1148 1149#define TSFTR_RST BIT(0) 1150#define TSFTR1_RST BIT(1) 1151 1152#define STOP_BCNQ BIT(6) 1153 1154#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1155#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1156 1157#define ACMHW_HWEN BIT(0) 1158#define ACMHW_BEQEN BIT(1) 1159#define ACMHW_VIQEN BIT(2) 1160#define ACMHW_VOQEN BIT(3) 1161#define ACMHW_BEQSTATUS BIT(4) 1162#define ACMHW_VIQSTATUS BIT(5) 1163#define ACMHW_VOQSTATUS BIT(6) 1164 1165#define APSDOFF BIT(6) 1166#define APSDOFF_STATUS BIT(7) 1167 1168#define BW_20MHZ BIT(2) 1169 1170#define RATE_BITMAP_ALL 0xFFFFF 1171 1172#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1173 1174#define TSFRST BIT(0) 1175#define DIS_GCLK BIT(1) 1176#define PAD_SEL BIT(2) 1177#define PWR_ST BIT(6) 1178#define PWRBIT_OW_EN BIT(7) 1179#define ACRC BIT(8) 1180#define CFENDFORM BIT(9) 1181#define ICV BIT(10) 1182 1183#define AAP BIT(0) 1184#define APM BIT(1) 1185#define AM BIT(2) 1186#define AB BIT(3) 1187#define ADD3 BIT(4) 1188#define APWRMGT BIT(5) 1189#define CBSSID BIT(6) 1190#define CBSSID_DATA BIT(6) 1191#define CBSSID_BCN BIT(7) 1192#define ACRC32 BIT(8) 1193#define AICV BIT(9) 1194#define ADF BIT(11) 1195#define ACF BIT(12) 1196#define AMF BIT(13) 1197#define HTC_LOC_CTRL BIT(14) 1198#define UC_DATA_EN BIT(16) 1199#define BM_DATA_EN BIT(17) 1200#define MFBEN BIT(22) 1201#define LSIGEN BIT(23) 1202#define ENMBID BIT(24) 1203#define APP_BASSN BIT(27) 1204#define APP_PHYSTS BIT(28) 1205#define APP_ICV BIT(29) 1206#define APP_MIC BIT(30) 1207#define APP_FCS BIT(31) 1208 1209#define _MIN_SPACE(x) ((x) & 0x7) 1210#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1211 1212#define RXERR_TYPE_OFDM_PPDU 0 1213#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1214#define RXERR_TYPE_OFDM_MPDU_OK 2 1215#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1216#define RXERR_TYPE_CCK_PPDU 4 1217#define RXERR_TYPE_CCK_FALSE_ALARM 5 1218#define RXERR_TYPE_CCK_MPDU_OK 6 1219#define RXERR_TYPE_CCK_MPDU_FAIL 7 1220#define RXERR_TYPE_HT_PPDU 8 1221#define RXERR_TYPE_HT_FALSE_ALARM 9 1222#define RXERR_TYPE_HT_MPDU_TOTAL 10 1223#define RXERR_TYPE_HT_MPDU_OK 11 1224#define RXERR_TYPE_HT_MPDU_FAIL 12 1225#define RXERR_TYPE_RX_FULL_DROP 15 1226 1227#define RXERR_COUNTER_MASK 0xFFFFF 1228#define RXERR_RPT_RST BIT(27) 1229#define _RXERR_RPT_SEL(type) ((type) << 28) 1230 1231#define SCR_TXUSEDK BIT(0) 1232#define SCR_RXUSEDK BIT(1) 1233#define SCR_TXENCENABLE BIT(2) 1234#define SCR_RXDECENABLE BIT(3) 1235#define SCR_SKBYA2 BIT(4) 1236#define SCR_NOSKMC BIT(5) 1237#define SCR_TXBCUSEDK BIT(6) 1238#define SCR_RXBCUSEDK BIT(7) 1239 1240#define USB_IS_HIGH_SPEED 0 1241#define USB_IS_FULL_SPEED 1 1242#define USB_SPEED_MASK BIT(5) 1243 1244#define USB_NORMAL_SIE_EP_MASK 0xF 1245#define USB_NORMAL_SIE_EP_SHIFT 4 1246 1247#define USB_TEST_EP_MASK 0x30 1248#define USB_TEST_EP_SHIFT 4 1249 1250#define USB_AGG_EN BIT(3) 1251 1252#define MAC_ADDR_LEN 6 1253#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/ 1254 1255#define POLLING_LLT_THRESHOLD 20 1256#define POLLING_READY_TIMEOUT_COUNT 3000 1257 1258#define MAX_MSS_DENSITY_2T 0x13 1259#define MAX_MSS_DENSITY_1T 0x0A 1260 1261#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1262#define EPROM_CMD_CONFIG 0x3 1263#define EPROM_CMD_LOAD 1 1264 1265#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1266 1267#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1268 1269#define RPMAC_RESET 0x100 1270#define RPMAC_TXSTART 0x104 1271#define RPMAC_TXLEGACYSIG 0x108 1272#define RPMAC_TXHTSIG1 0x10c 1273#define RPMAC_TXHTSIG2 0x110 1274#define RPMAC_PHYDEBUG 0x114 1275#define RPMAC_TXPACKETNUM 0x118 1276#define RPMAC_TXIDLE 0x11c 1277#define RPMAC_TXMACHEADER0 0x120 1278#define RPMAC_TXMACHEADER1 0x124 1279#define RPMAC_TXMACHEADER2 0x128 1280#define RPMAC_TXMACHEADER3 0x12c 1281#define RPMAC_TXMACHEADER4 0x130 1282#define RPMAC_TXMACHEADER5 0x134 1283#define RPMAC_TXDADATYPE 0x138 1284#define RPMAC_TXRANDOMSEED 0x13c 1285#define RPMAC_CCKPLCPPREAMBLE 0x140 1286#define RPMAC_CCKPLCPHEADER 0x144 1287#define RPMAC_CCKCRC16 0x148 1288#define RPMAC_OFDMRXCRC32OK 0x170 1289#define RPMAC_OFDMRXCRC32ER 0x174 1290#define RPMAC_OFDMRXPARITYER 0x178 1291#define RPMAC_OFDMRXCRC8ER 0x17c 1292#define RPMAC_CCKCRXRC16ER 0x180 1293#define RPMAC_CCKCRXRC32ER 0x184 1294#define RPMAC_CCKCRXRC32OK 0x188 1295#define RPMAC_TXSTATUS 0x18c 1296 1297#define RFPGA0_RFMOD 0x800 1298 1299#define RFPGA0_TXINFO 0x804 1300#define RFPGA0_PSDFUNCTION 0x808 1301 1302#define RFPGA0_TXGAINSTAGE 0x80c 1303 1304#define RFPGA0_RFTIMING1 0x810 1305#define RFPGA0_RFTIMING2 0x814 1306 1307#define RFPGA0_XA_HSSIPARAMETER1 0x820 1308#define RFPGA0_XA_HSSIPARAMETER2 0x824 1309#define RFPGA0_XB_HSSIPARAMETER1 0x828 1310#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1311 1312#define RFPGA0_XA_LSSIPARAMETER 0x840 1313#define RFPGA0_XB_LSSIPARAMETER 0x844 1314 1315#define RFPGA0_RFWAKEUPPARAMETER 0x850 1316#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1317 1318#define RFPGA0_XAB_SWITCHCONTROL 0x858 1319#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1320 1321#define RFPGA0_XA_RFINTERFACEOE 0x860 1322#define RFPGA0_XB_RFINTERFACEOE 0x864 1323 1324#define RFPGA0_XAB_RFINTERFACESW 0x870 1325#define RFPGA0_XCD_RFINTERFACESW 0x874 1326 1327#define RFPGA0_XAB_RFPARAMETER 0x878 1328#define RFPGA0_XCD_RFPARAMETER 0x87c 1329 1330#define RFPGA0_ANALOGPARAMETER1 0x880 1331#define RFPGA0_ANALOGPARAMETER2 0x884 1332#define RFPGA0_ANALOGPARAMETER3 0x888 1333#define RFPGA0_ANALOGPARAMETER4 0x88c 1334 1335#define RFPGA0_XA_LSSIREADBACK 0x8a0 1336#define RFPGA0_XB_LSSIREADBACK 0x8a4 1337#define RFPGA0_XC_LSSIREADBACK 0x8a8 1338#define RFPGA0_XD_LSSIREADBACK 0x8ac 1339 1340#define RFPGA0_PSDREPORT 0x8b4 1341#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1342#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1343#define REG_SC_CNT 0x8c4 1344#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1345#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1346 1347#define RFPGA1_RFMOD 0x900 1348 1349#define RFPGA1_TXBLOCK 0x904 1350#define RFPGA1_DEBUGSELECT 0x908 1351#define RFPGA1_TXINFO 0x90c 1352 1353#define RCCK0_SYSTEM 0xa00 1354 1355#define RCCK0_AFESETTING 0xa04 1356#define RCCK0_CCA 0xa08 1357 1358#define RCCK0_RXAGC1 0xa0c 1359#define RCCK0_RXAGC2 0xa10 1360 1361#define RCCK0_RXHP 0xa14 1362 1363#define RCCK0_DSPPARAMETER1 0xa18 1364#define RCCK0_DSPPARAMETER2 0xa1c 1365 1366#define RCCK0_TXFILTER1 0xa20 1367#define RCCK0_TXFILTER2 0xa24 1368#define RCCK0_DEBUGPORT 0xa28 1369#define RCCK0_FALSEALARMREPORT 0xa2c 1370#define RCCK0_TRSSIREPORT 0xa50 1371#define RCCK0_RXREPORT 0xa54 1372#define RCCK0_FACOUNTERLOWER 0xa5c 1373#define RCCK0_FACOUNTERUPPER 0xa58 1374#define RCCK0_CCA_CNT 0xa60 1375 1376/* PageB(0xB00) */ 1377#define RPDP_ANTA 0xb00 1378#define RPDP_ANTA_4 0xb04 1379#define RPDP_ANTA_8 0xb08 1380#define RPDP_ANTA_C 0xb0c 1381#define RPDP_ANTA_10 0xb10 1382#define RPDP_ANTA_14 0xb14 1383#define RPDP_ANTA_18 0xb18 1384#define RPDP_ANTA_1C 0xb1c 1385#define RPDP_ANTA_20 0xb20 1386#define RPDP_ANTA_24 0xb24 1387 1388#define RCONFIG_PMPD_ANTA 0xb28 1389#define RCONFIG_RAM64x16 0xb2c 1390 1391#define RBNDA 0xb30 1392#define RHSSIPAR 0xb34 1393 1394#define RCONFIG_ANTA 0xb68 1395#define RCONFIG_ANTB 0xb6c 1396 1397#define RPDP_ANTB 0xb70 1398#define RPDP_ANTB_4 0xb74 1399#define RPDP_ANTB_8 0xb78 1400#define RPDP_ANTB_C 0xb7c 1401#define RPDP_ANTB_10 0xb80 1402#define RPDP_ANTB_14 0xb84 1403#define RPDP_ANTB_18 0xb88 1404#define RPDP_ANTB_1C 0xb8c 1405#define RPDP_ANTB_20 0xb90 1406#define RPDP_ANTB_24 0xb94 1407 1408#define RCONFIG_PMPD_ANTB 0xb98 1409 1410#define RBNDB 0xba0 1411 1412#define RAPK 0xbd8 1413#define RPM_RX0_ANTA 0xbdc 1414#define RPM_RX1_ANTA 0xbe0 1415#define RPM_RX2_ANTA 0xbe4 1416#define RPM_RX3_ANTA 0xbe8 1417#define RPM_RX0_ANTB 0xbec 1418#define RPM_RX1_ANTB 0xbf0 1419#define RPM_RX2_ANTB 0xbf4 1420#define RPM_RX3_ANTB 0xbf8 1421 1422/*Page C*/ 1423#define ROFDM0_LSTF 0xc00 1424 1425#define ROFDM0_TRXPATHENABLE 0xc04 1426#define ROFDM0_TRMUXPAR 0xc08 1427#define ROFDM0_TRSWISOLATION 0xc0c 1428 1429#define ROFDM0_XARXAFE 0xc10 1430#define ROFDM0_XARXIQIMBALANCE 0xc14 1431#define ROFDM0_XBRXAFE 0xc18 1432#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1433#define ROFDM0_XCRXAFE 0xc20 1434#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1435#define ROFDM0_XDRXAFE 0xc28 1436#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1437 1438#define ROFDM0_RXDETECTOR1 0xc30 1439#define ROFDM0_RXDETECTOR2 0xc34 1440#define ROFDM0_RXDETECTOR3 0xc38 1441#define ROFDM0_RXDETECTOR4 0xc3c 1442 1443#define ROFDM0_RXDSP 0xc40 1444#define ROFDM0_CFOANDDAGC 0xc44 1445#define ROFDM0_CCADROPTHRESHOLD 0xc48 1446#define ROFDM0_ECCATHRESHOLD 0xc4c 1447 1448#define ROFDM0_XAAGCCORE1 0xc50 1449#define ROFDM0_XAAGCCORE2 0xc54 1450#define ROFDM0_XBAGCCORE1 0xc58 1451#define ROFDM0_XBAGCCORE2 0xc5c 1452#define ROFDM0_XCAGCCORE1 0xc60 1453#define ROFDM0_XCAGCCORE2 0xc64 1454#define ROFDM0_XDAGCCORE1 0xc68 1455#define ROFDM0_XDAGCCORE2 0xc6c 1456 1457#define ROFDM0_AGCPARAMETER1 0xc70 1458#define ROFDM0_AGCPARAMETER2 0xc74 1459#define ROFDM0_AGCRSSITABLE 0xc78 1460#define ROFDM0_HTSTFAGC 0xc7c 1461 1462#define ROFDM0_XATXIQIMBALANCE 0xc80 1463#define ROFDM0_XATXAFE 0xc84 1464#define ROFDM0_XBTXIQIMBALANCE 0xc88 1465#define ROFDM0_XBTXAFE 0xc8c 1466#define ROFDM0_XCTXIQIMBALANCE 0xc90 1467#define ROFDM0_XCTXAFE 0xc94 1468#define ROFDM0_XDTXIQIMBALANCE 0xc98 1469#define ROFDM0_XDTXAFE 0xc9c 1470 1471#define ROFDM0_RXIQEXTANTA 0xca0 1472#define ROFDM0_TXCOEFF1 0xca4 1473#define ROFDM0_TXCOEFF2 0xca8 1474#define ROFDM0_TXCOEFF3 0xcac 1475#define ROFDM0_TXCOEFF4 0xcb0 1476#define ROFDM0_TXCOEFF5 0xcb4 1477#define ROFDM0_TXCOEFF6 0xcb8 1478 1479#define ROFDM0_RXHPPARAMETER 0xce0 1480#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1481#define ROFDM0_FRAMESYNC 0xcf0 1482#define ROFDM0_DFSREPORT 0xcf4 1483 1484#define ROFDM1_LSTF 0xd00 1485#define ROFDM1_TRXPATHENABLE 0xd04 1486 1487#define ROFDM1_CF0 0xd08 1488#define ROFDM1_CSI1 0xd10 1489#define ROFDM1_SBD 0xd14 1490#define ROFDM1_CSI2 0xd18 1491#define ROFDM1_CFOTRACKING 0xd2c 1492#define ROFDM1_TRXMESAURE1 0xd34 1493#define ROFDM1_INTFDET 0xd3c 1494#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1495#define ROFDM1_PSEUDONOISESTATECD 0xd54 1496#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1497 1498#define ROFDM_PHYCOUNTER1 0xda0 1499#define ROFDM_PHYCOUNTER2 0xda4 1500#define ROFDM_PHYCOUNTER3 0xda8 1501 1502#define ROFDM_SHORTCFOAB 0xdac 1503#define ROFDM_SHORTCFOCD 0xdb0 1504#define ROFDM_LONGCFOAB 0xdb4 1505#define ROFDM_LONGCFOCD 0xdb8 1506#define ROFDM_TAILCF0AB 0xdbc 1507#define ROFDM_TAILCF0CD 0xdc0 1508#define ROFDM_PWMEASURE1 0xdc4 1509#define ROFDM_PWMEASURE2 0xdc8 1510#define ROFDM_BWREPORT 0xdcc 1511#define ROFDM_AGCREPORT 0xdd0 1512#define ROFDM_RXSNR 0xdd4 1513#define ROFDM_RXEVMCSI 0xdd8 1514#define ROFDM_SIGREPORT 0xddc 1515 1516#define RTXAGC_A_RATE18_06 0xe00 1517#define RTXAGC_A_RATE54_24 0xe04 1518#define RTXAGC_A_CCK1_MCS32 0xe08 1519#define RTXAGC_A_MCS03_MCS00 0xe10 1520#define RTXAGC_A_MCS07_MCS04 0xe14 1521#define RTXAGC_A_MCS11_MCS08 0xe18 1522#define RTXAGC_A_MCS15_MCS12 0xe1c 1523 1524#define RTXAGC_B_RATE18_06 0x830 1525#define RTXAGC_B_RATE54_24 0x834 1526#define RTXAGC_B_CCK1_55_MCS32 0x838 1527#define RTXAGC_B_MCS03_MCS00 0x83c 1528#define RTXAGC_B_MCS07_MCS04 0x848 1529#define RTXAGC_B_MCS11_MCS08 0x84c 1530#define RTXAGC_B_MCS15_MCS12 0x868 1531#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1532 1533#define RFPGA0_IQK 0xe28 1534#define RTX_IQK_TONE_A 0xe30 1535#define RRX_IQK_TONE_A 0xe34 1536#define RTX_IQK_PI_A 0xe38 1537#define RRX_IQK_PI_A 0xe3c 1538 1539#define RTX_IQK 0xe40 1540#define RRX_IQK 0xe44 1541#define RIQK_AGC_PTS 0xe48 1542#define RIQK_AGC_RSP 0xe4c 1543#define RTX_IQK_TONE_B 0xe50 1544#define RRX_IQK_TONE_B 0xe54 1545#define RTX_IQK_PI_B 0xe58 1546#define RRX_IQK_PI_B 0xe5c 1547#define RIQK_AGC_CONT 0xe60 1548 1549#define RBLUE_TOOTH 0xe6c 1550#define RRX_WAIT_CCA 0xe70 1551#define RTX_CCK_RFON 0xe74 1552#define RTX_CCK_BBON 0xe78 1553#define RTX_OFDM_RFON 0xe7c 1554#define RTX_OFDM_BBON 0xe80 1555#define RTX_TO_RX 0xe84 1556#define RTX_TO_TX 0xe88 1557#define RRX_CCK 0xe8c 1558 1559#define RTX_POWER_BEFORE_IQK_A 0xe94 1560#define RTX_POWER_AFTER_IQK_A 0xe9c 1561 1562#define RRX_POWER_BEFORE_IQK_A 0xea0 1563#define RRX_POWER_BEFORE_IQK_A_2 0xea4 1564#define RRX_POWER_AFTER_IQK_A 0xea8 1565#define RRX_POWER_AFTER_IQK_A_2 0xeac 1566 1567#define RTX_POWER_BEFORE_IQK_B 0xeb4 1568#define RTX_POWER_AFTER_IQK_B 0xebc 1569 1570#define RRX_POWER_BEFORE_IQK_B 0xec0 1571#define RRX_POWER_BEFORE_IQK_B_2 0xec4 1572#define RRX_POWER_AFTER_IQK_B 0xec8 1573#define RRX_POWER_AFTER_IQK_B_2 0xecc 1574 1575#define RRX_OFDM 0xed0 1576#define RRX_WAIT_RIFS 0xed4 1577#define RRX_TO_RX 0xed8 1578#define RSTANDBY 0xedc 1579#define RSLEEP 0xee0 1580#define RPMPD_ANAEN 0xeec 1581 1582#define RZEBRA1_HSSIENABLE 0x0 1583#define RZEBRA1_TRXENABLE1 0x1 1584#define RZEBRA1_TRXENABLE2 0x2 1585#define RZEBRA1_AGC 0x4 1586#define RZEBRA1_CHARGEPUMP 0x5 1587#define RZEBRA1_CHANNEL 0x7 1588 1589#define RZEBRA1_TXGAIN 0x8 1590#define RZEBRA1_TXLPF 0x9 1591#define RZEBRA1_RXLPF 0xb 1592#define RZEBRA1_RXHPFCORNER 0xc 1593 1594#define RGLOBALCTRL 0 1595#define RRTL8256_TXLPF 19 1596#define RRTL8256_RXLPF 11 1597#define RRTL8258_TXLPF 0x11 1598#define RRTL8258_RXLPF 0x13 1599#define RRTL8258_RSSILPF 0xa 1600 1601#define RF_AC 0x00 1602 1603#define RF_IQADJ_G1 0x01 1604#define RF_IQADJ_G2 0x02 1605#define RF_POW_TRSW 0x05 1606 1607#define RF_GAIN_RX 0x06 1608#define RF_GAIN_TX 0x07 1609 1610#define RF_TXM_IDAC 0x08 1611#define RF_BS_IQGEN 0x0F 1612 1613#define RF_MODE1 0x10 1614#define RF_MODE2 0x11 1615 1616#define RF_RX_AGC_HP 0x12 1617#define RF_TX_AGC 0x13 1618#define RF_BIAS 0x14 1619#define RF_IPA 0x15 1620#define RF_POW_ABILITY 0x17 1621#define RF_MODE_AG 0x18 1622#define RRFCHANNEL 0x18 1623#define RF_CHNLBW 0x18 1624#define RF_TOP 0x19 1625 1626#define RF_RX_G1 0x1A 1627#define RF_RX_G2 0x1B 1628 1629#define RF_RX_BB2 0x1C 1630#define RF_RX_BB1 0x1D 1631 1632#define RF_RCK1 0x1E 1633#define RF_RCK2 0x1F 1634 1635#define RF_TX_G1 0x20 1636#define RF_TX_G2 0x21 1637#define RF_TX_G3 0x22 1638 1639#define RF_TX_BB1 0x23 1640#define RF_T_METER 0x42 1641 1642#define RF_SYN_G1 0x25 1643#define RF_SYN_G2 0x26 1644#define RF_SYN_G3 0x27 1645#define RF_SYN_G4 0x28 1646#define RF_SYN_G5 0x29 1647#define RF_SYN_G6 0x2A 1648#define RF_SYN_G7 0x2B 1649#define RF_SYN_G8 0x2C 1650 1651#define RF_RCK_OS 0x30 1652#define RF_TXPA_G1 0x31 1653#define RF_TXPA_G2 0x32 1654#define RF_TXPA_G3 0x33 1655 1656#define RF_TX_BIAS_A 0x35 1657#define RF_TX_BIAS_D 0x36 1658#define RF_LOBF_9 0x38 1659#define RF_RXRF_A3 0x3C 1660#define RF_TRSW 0x3F 1661 1662#define RF_TXRF_A2 0x41 1663#define RF_TXPA_G4 0x46 1664#define RF_TXPA_A4 0x4B 1665 1666#define RF_WE_LUT 0xEF 1667 1668#define BBBRESETB 0x100 1669#define BGLOBALRESETB 0x200 1670#define BOFDMTXSTART 0x4 1671#define BCCKTXSTART 0x8 1672#define BCRC32DEBUG 0x100 1673#define BPMACLOOPBACK 0x10 1674#define BTXLSIG 0xffffff 1675#define BOFDMTXRATE 0xf 1676#define BOFDMTXRESERVED 0x10 1677#define BOFDMTXLENGTH 0x1ffe0 1678#define BOFDMTXPARITY 0x20000 1679#define BTXHTSIG1 0xffffff 1680#define BTXHTMCSRATE 0x7f 1681#define BTXHTBW 0x80 1682#define BTXHTLENGTH 0xffff00 1683#define BTXHTSIG2 0xffffff 1684#define BTXHTSMOOTHING 0x1 1685#define BTXHTSOUNDING 0x2 1686#define BTXHTRESERVED 0x4 1687#define BTXHTAGGREATION 0x8 1688#define BTXHTSTBC 0x30 1689#define BTXHTADVANCECODING 0x40 1690#define BTXHTSHORTGI 0x80 1691#define BTXHTNUMBERHT_LTF 0x300 1692#define BTXHTCRC8 0x3fc00 1693#define BCOUNTERRESET 0x10000 1694#define BNUMOFOFDMTX 0xffff 1695#define BNUMOFCCKTX 0xffff0000 1696#define BTXIDLEINTERVAL 0xffff 1697#define BOFDMSERVICE 0xffff0000 1698#define BTXMACHEADER 0xffffffff 1699#define BTXDATAINIT 0xff 1700#define BTXHTMODE 0x100 1701#define BTXDATATYPE 0x30000 1702#define BTXRANDOMSEED 0xffffffff 1703#define BCCKTXPREAMBLE 0x1 1704#define BCCKTXSFD 0xffff0000 1705#define BCCKTXSIG 0xff 1706#define BCCKTXSERVICE 0xff00 1707#define BCCKLENGTHEXT 0x8000 1708#define BCCKTXLENGHT 0xffff0000 1709#define BCCKTXCRC16 0xffff 1710#define BCCKTXSTATUS 0x1 1711#define BOFDMTXSTATUS 0x2 1712#define IS_BB_REG_OFFSET_92S(_offset) \ 1713 ((_offset >= 0x800) && (_offset <= 0xfff)) 1714 1715#define BRFMOD 0x1 1716#define BJAPANMODE 0x2 1717#define BCCKTXSC 0x30 1718#define BCCKEN 0x1000000 1719#define BOFDMEN 0x2000000 1720 1721#define BOFDMRXADCPHASE 0x10000 1722#define BOFDMTXDACPHASE 0x40000 1723#define BXATXAGC 0x3f 1724 1725#define BXBTXAGC 0xf00 1726#define BXCTXAGC 0xf000 1727#define BXDTXAGC 0xf0000 1728 1729#define BPASTART 0xf0000000 1730#define BTRSTART 0x00f00000 1731#define BRFSTART 0x0000f000 1732#define BBBSTART 0x000000f0 1733#define BBBCCKSTART 0x0000000f 1734#define BPAEND 0xf 1735#define BTREND 0x0f000000 1736#define BRFEND 0x000f0000 1737#define BCCAMASK 0x000000f0 1738#define BR2RCCAMASK 0x00000f00 1739#define BHSSI_R2TDELAY 0xf8000000 1740#define BHSSI_T2RDELAY 0xf80000 1741#define BCONTXHSSI 0x400 1742#define BIGFROMCCK 0x200 1743#define BAGCADDRESS 0x3f 1744#define BRXHPTX 0x7000 1745#define BRXHP2RX 0x38000 1746#define BRXHPCCKINI 0xc0000 1747#define BAGCTXCODE 0xc00000 1748#define BAGCRXCODE 0x300000 1749 1750#define B3WIREDATALENGTH 0x800 1751#define B3WIREADDREAALENGTH 0x400 1752 1753#define B3WIRERFPOWERDOWN 0x1 1754#define B5GPAPEPOLARITY 0x40000000 1755#define B2GPAPEPOLARITY 0x80000000 1756#define BRFSW_TXDEFAULTANT 0x3 1757#define BRFSW_TXOPTIONANT 0x30 1758#define BRFSW_RXDEFAULTANT 0x300 1759#define BRFSW_RXOPTIONANT 0x3000 1760#define BRFSI_3WIREDATA 0x1 1761#define BRFSI_3WIRECLOCK 0x2 1762#define BRFSI_3WIRELOAD 0x4 1763#define BRFSI_3WIRERW 0x8 1764#define BRFSI_3WIRE 0xf 1765 1766#define BRFSI_RFENV 0x10 1767 1768#define BRFSI_TRSW 0x20 1769#define BRFSI_TRSWB 0x40 1770#define BRFSI_ANTSW 0x100 1771#define BRFSI_ANTSWB 0x200 1772#define BRFSI_PAPE 0x400 1773#define BRFSI_PAPE5G 0x800 1774#define BBANDSELECT 0x1 1775#define BHTSIG2_GI 0x80 1776#define BHTSIG2_SMOOTHING 0x01 1777#define BHTSIG2_SOUNDING 0x02 1778#define BHTSIG2_AGGREATON 0x08 1779#define BHTSIG2_STBC 0x30 1780#define BHTSIG2_ADVCODING 0x40 1781#define BHTSIG2_NUMOFHTLTF 0x300 1782#define BHTSIG2_CRC8 0x3fc 1783#define BHTSIG1_MCS 0x7f 1784#define BHTSIG1_BANDWIDTH 0x80 1785#define BHTSIG1_HTLENGTH 0xffff 1786#define BLSIG_RATE 0xf 1787#define BLSIG_RESERVED 0x10 1788#define BLSIG_LENGTH 0x1fffe 1789#define BLSIG_PARITY 0x20 1790#define BCCKRXPHASE 0x4 1791 1792#define BLSSIREADADDRESS 0x7f800000 1793#define BLSSIREADEDGE 0x80000000 1794 1795#define BLSSIREADBACKDATA 0xfffff 1796 1797#define BLSSIREADOKFLAG 0x1000 1798#define BCCKSAMPLERATE 0x8 1799#define BREGULATOR0STANDBY 0x1 1800#define BREGULATORPLLSTANDBY 0x2 1801#define BREGULATOR1STANDBY 0x4 1802#define BPLLPOWERUP 0x8 1803#define BDPLLPOWERUP 0x10 1804#define BDA10POWERUP 0x20 1805#define BAD7POWERUP 0x200 1806#define BDA6POWERUP 0x2000 1807#define BXTALPOWERUP 0x4000 1808#define B40MDCLKPOWERUP 0x8000 1809#define BDA6DEBUGMODE 0x20000 1810#define BDA6SWING 0x380000 1811 1812#define BADCLKPHASE 0x4000000 1813#define B80MCLKDELAY 0x18000000 1814#define BAFEWATCHDOGENABLE 0x20000000 1815 1816#define BXTALCAP01 0xc0000000 1817#define BXTALCAP23 0x3 1818#define BXTALCAP92X 0x0f000000 1819#define BXTALCAP 0x0f000000 1820 1821#define BINTDIFCLKENABLE 0x400 1822#define BEXTSIGCLKENABLE 0x800 1823#define BBANDGAP_MBIAS_POWERUP 0x10000 1824#define BAD11SH_GAIN 0xc0000 1825#define BAD11NPUT_RANGE 0x700000 1826#define BAD110P_CURRENT 0x3800000 1827#define BLPATH_LOOPBACK 0x4000000 1828#define BQPATH_LOOPBACK 0x8000000 1829#define BAFE_LOOPBACK 0x10000000 1830#define BDA10_SWING 0x7e0 1831#define BDA10_REVERSE 0x800 1832#define BDA_CLK_SOURCE 0x1000 1833#define BDA7INPUT_RANGE 0x6000 1834#define BDA7_GAIN 0x38000 1835#define BDA7OUTPUT_CM_MODE 0x40000 1836#define BDA7INPUT_CM_MODE 0x380000 1837#define BDA7CURRENT 0xc00000 1838#define BREGULATOR_ADJUST 0x7000000 1839#define BAD11POWERUP_ATTX 0x1 1840#define BDA10PS_ATTX 0x10 1841#define BAD11POWERUP_ATRX 0x100 1842#define BDA10PS_ATRX 0x1000 1843#define BCCKRX_AGC_FORMAT 0x200 1844#define BPSDFFT_SAMPLE_POINT 0xc000 1845#define BPSD_AVERAGE_NUM 0x3000 1846#define BIQPATH_CONTROL 0xc00 1847#define BPSD_FREQ 0x3ff 1848#define BPSD_ANTENNA_PATH 0x30 1849#define BPSD_IQ_SWITCH 0x40 1850#define BPSD_RX_TRIGGER 0x400000 1851#define BPSD_TX_TRIGGER 0x80000000 1852#define BPSD_SINE_TONE_SCALE 0x7f000000 1853#define BPSD_REPORT 0xffff 1854 1855#define BOFDM_TXSC 0x30000000 1856#define BCCK_TXON 0x1 1857#define BOFDM_TXON 0x2 1858#define BDEBUG_PAGE 0xfff 1859#define BDEBUG_ITEM 0xff 1860#define BANTL 0x10 1861#define BANT_NONHT 0x100 1862#define BANT_HT1 0x1000 1863#define BANT_HT2 0x10000 1864#define BANT_HT1S1 0x100000 1865#define BANT_NONHTS1 0x1000000 1866 1867#define BCCK_BBMODE 0x3 1868#define BCCK_TXPOWERSAVING 0x80 1869#define BCCK_RXPOWERSAVING 0x40 1870 1871#define BCCK_SIDEBAND 0x10 1872 1873#define BCCK_SCRAMBLE 0x8 1874#define BCCK_ANTDIVERSITY 0x8000 1875#define BCCK_CARRIER_RECOVERY 0x4000 1876#define BCCK_TXRATE 0x3000 1877#define BCCK_DCCANCEL 0x0800 1878#define BCCK_ISICANCEL 0x0400 1879#define BCCK_MATCH_FILTER 0x0200 1880#define BCCK_EQUALIZER 0x0100 1881#define BCCK_PREAMBLE_DETECT 0x800000 1882#define BCCK_FAST_FALSECCA 0x400000 1883#define BCCK_CH_ESTSTART 0x300000 1884#define BCCK_CCA_COUNT 0x080000 1885#define BCCK_CS_LIM 0x070000 1886#define BCCK_BIST_MODE 0x80000000 1887#define BCCK_CCAMASK 0x40000000 1888#define BCCK_TX_DAC_PHASE 0x4 1889#define BCCK_RX_ADC_PHASE 0x20000000 1890#define BCCKR_CP_MODE 0x0100 1891#define BCCK_TXDC_OFFSET 0xf0 1892#define BCCK_RXDC_OFFSET 0xf 1893#define BCCK_CCA_MODE 0xc000 1894#define BCCK_FALSECS_LIM 0x3f00 1895#define BCCK_CS_RATIO 0xc00000 1896#define BCCK_CORGBIT_SEL 0x300000 1897#define BCCK_PD_LIM 0x0f0000 1898#define BCCK_NEWCCA 0x80000000 1899#define BCCK_RXHP_OF_IG 0x8000 1900#define BCCK_RXIG 0x7f00 1901#define BCCK_LNA_POLARITY 0x800000 1902#define BCCK_RX1ST_BAIN 0x7f0000 1903#define BCCK_RF_EXTEND 0x20000000 1904#define BCCK_RXAGC_SATLEVEL 0x1f000000 1905#define BCCK_RXAGC_SATCOUNT 0xe0 1906#define BCCKRXRFSETTLE 0x1f 1907#define BCCK_FIXED_RXAGC 0x8000 1908#define BCCK_ANTENNA_POLARITY 0x2000 1909#define BCCK_TXFILTER_TYPE 0x0c00 1910#define BCCK_RXAGC_REPORTTYPE 0x0300 1911#define BCCK_RXDAGC_EN 0x80000000 1912#define BCCK_RXDAGC_PERIOD 0x20000000 1913#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1914#define BCCK_TIMING_RECOVERY 0x800000 1915#define BCCK_TXC0 0x3f0000 1916#define BCCK_TXC1 0x3f000000 1917#define BCCK_TXC2 0x3f 1918#define BCCK_TXC3 0x3f00 1919#define BCCK_TXC4 0x3f0000 1920#define BCCK_TXC5 0x3f000000 1921#define BCCK_TXC6 0x3f 1922#define BCCK_TXC7 0x3f00 1923#define BCCK_DEBUGPORT 0xff0000 1924#define BCCK_DAC_DEBUG 0x0f000000 1925#define BCCK_FALSEALARM_ENABLE 0x8000 1926#define BCCK_FALSEALARM_READ 0x4000 1927#define BCCK_TRSSI 0x7f 1928#define BCCK_RXAGC_REPORT 0xfe 1929#define BCCK_RXREPORT_ANTSEL 0x80000000 1930#define BCCK_RXREPORT_MFOFF 0x40000000 1931#define BCCK_RXREPORT_SQLOSS 0x20000000 1932#define BCCK_RXREPORT_PKTLOSS 0x10000000 1933#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1934#define BCCK_RXREPORT_RATEERROR 0x04000000 1935#define BCCK_RXREPORT_RXRATE 0x03000000 1936#define BCCK_RXFA_COUNTER_LOWER 0xff 1937#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1938#define BCCK_RXHPAGC_START 0xe000 1939#define BCCK_RXHPAGC_FINAL 0x1c00 1940#define BCCK_RXFALSEALARM_ENABLE 0x8000 1941#define BCCK_FACOUNTER_FREEZE 0x4000 1942#define BCCK_TXPATH_SEL 0x10000000 1943#define BCCK_DEFAULT_RXPATH 0xc000000 1944#define BCCK_OPTION_RXPATH 0x3000000 1945 1946#define BNUM_OFSTF 0x3 1947#define BSHIFT_L 0xc0 1948#define BGI_TH 0xc 1949#define BRXPATH_A 0x1 1950#define BRXPATH_B 0x2 1951#define BRXPATH_C 0x4 1952#define BRXPATH_D 0x8 1953#define BTXPATH_A 0x1 1954#define BTXPATH_B 0x2 1955#define BTXPATH_C 0x4 1956#define BTXPATH_D 0x8 1957#define BTRSSI_FREQ 0x200 1958#define BADC_BACKOFF 0x3000 1959#define BDFIR_BACKOFF 0xc000 1960#define BTRSSI_LATCH_PHASE 0x10000 1961#define BRX_LDC_OFFSET 0xff 1962#define BRX_QDC_OFFSET 0xff00 1963#define BRX_DFIR_MODE 0x1800000 1964#define BRX_DCNF_TYPE 0xe000000 1965#define BRXIQIMB_A 0x3ff 1966#define BRXIQIMB_B 0xfc00 1967#define BRXIQIMB_C 0x3f0000 1968#define BRXIQIMB_D 0xffc00000 1969#define BDC_DC_NOTCH 0x60000 1970#define BRXNB_NOTCH 0x1f000000 1971#define BPD_TH 0xf 1972#define BPD_TH_OPT2 0xc000 1973#define BPWED_TH 0x700 1974#define BIFMF_WIN_L 0x800 1975#define BPD_OPTION 0x1000 1976#define BMF_WIN_L 0xe000 1977#define BBW_SEARCH_L 0x30000 1978#define BWIN_ENH_L 0xc0000 1979#define BBW_TH 0x700000 1980#define BED_TH2 0x3800000 1981#define BBW_OPTION 0x4000000 1982#define BRADIO_TH 0x18000000 1983#define BWINDOW_L 0xe0000000 1984#define BSBD_OPTION 0x1 1985#define BFRAME_TH 0x1c 1986#define BFS_OPTION 0x60 1987#define BDC_SLOPE_CHECK 0x80 1988#define BFGUARD_COUNTER_DC_L 0xe00 1989#define BFRAME_WEIGHT_SHORT 0x7000 1990#define BSUB_TUNE 0xe00000 1991#define BFRAME_DC_LENGTH 0xe000000 1992#define BSBD_START_OFFSET 0x30000000 1993#define BFRAME_TH_2 0x7 1994#define BFRAME_GI2_TH 0x38 1995#define BGI2_SYNC_EN 0x40 1996#define BSARCH_SHORT_EARLY 0x300 1997#define BSARCH_SHORT_LATE 0xc00 1998#define BSARCH_GI2_LATE 0x70000 1999#define BCFOANTSUM 0x1 2000#define BCFOACC 0x2 2001#define BCFOSTARTOFFSET 0xc 2002#define BCFOLOOPBACK 0x70 2003#define BCFOSUMWEIGHT 0x80 2004#define BDAGCENABLE 0x10000 2005#define BTXIQIMB_A 0x3ff 2006#define BTXIQIMB_b 0xfc00 2007#define BTXIQIMB_C 0x3f0000 2008#define BTXIQIMB_D 0xffc00000 2009#define BTXIDCOFFSET 0xff 2010#define BTXIQDCOFFSET 0xff00 2011#define BTXDFIRMODE 0x10000 2012#define BTXPESUDO_NOISEON 0x4000000 2013#define BTXPESUDO_NOISE_A 0xff 2014#define BTXPESUDO_NOISE_B 0xff00 2015#define BTXPESUDO_NOISE_C 0xff0000 2016#define BTXPESUDO_NOISE_D 0xff000000 2017#define BCCA_DROPOPTION 0x20000 2018#define BCCA_DROPTHRES 0xfff00000 2019#define BEDCCA_H 0xf 2020#define BEDCCA_L 0xf0 2021#define BLAMBDA_ED 0x300 2022#define BRX_INITIALGAIN 0x7f 2023#define BRX_ANTDIV_EN 0x80 2024#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 2025#define BRX_HIGHPOWER_FLOW 0x8000 2026#define BRX_AGC_FREEZE_THRES 0xc0000 2027#define BRX_FREEZESTEP_AGC1 0x300000 2028#define BRX_FREEZESTEP_AGC2 0xc00000 2029#define BRX_FREEZESTEP_AGC3 0x3000000 2030#define BRX_FREEZESTEP_AGC0 0xc000000 2031#define BRXRSSI_CMP_EN 0x10000000 2032#define BRXQUICK_AGCEN 0x20000000 2033#define BRXAGC_FREEZE_THRES_MODE 0x40000000 2034#define BRX_OVERFLOW_CHECKTYPE 0x80000000 2035#define BRX_AGCSHIFT 0x7f 2036#define BTRSW_TRI_ONLY 0x80 2037#define BPOWER_THRES 0x300 2038#define BRXAGC_EN 0x1 2039#define BRXAGC_TOGETHER_EN 0x2 2040#define BRXAGC_MIN 0x4 2041#define BRXHP_INI 0x7 2042#define BRXHP_TRLNA 0x70 2043#define BRXHP_RSSI 0x700 2044#define BRXHP_BBP1 0x7000 2045#define BRXHP_BBP2 0x70000 2046#define BRXHP_BBP3 0x700000 2047#define BRSSI_H 0x7f0000 2048#define BRSSI_GEN 0x7f000000 2049#define BRXSETTLE_TRSW 0x7 2050#define BRXSETTLE_LNA 0x38 2051#define BRXSETTLE_RSSI 0x1c0 2052#define BRXSETTLE_BBP 0xe00 2053#define BRXSETTLE_RXHP 0x7000 2054#define BRXSETTLE_ANTSW_RSSI 0x38000 2055#define BRXSETTLE_ANTSW 0xc0000 2056#define BRXPROCESS_TIME_DAGC 0x300000 2057#define BRXSETTLE_HSSI 0x400000 2058#define BRXPROCESS_TIME_BBPPW 0x800000 2059#define BRXANTENNA_POWER_SHIFT 0x3000000 2060#define BRSSI_TABLE_SELECT 0xc000000 2061#define BRXHP_FINAL 0x7000000 2062#define BRXHPSETTLE_BBP 0x7 2063#define BRXHTSETTLE_HSSI 0x8 2064#define BRXHTSETTLE_RXHP 0x70 2065#define BRXHTSETTLE_BBPPW 0x80 2066#define BRXHTSETTLE_IDLE 0x300 2067#define BRXHTSETTLE_RESERVED 0x1c00 2068#define BRXHT_RXHP_EN 0x8000 2069#define BRXAGC_FREEZE_THRES 0x30000 2070#define BRXAGC_TOGETHEREN 0x40000 2071#define BRXHTAGC_MIN 0x80000 2072#define BRXHTAGC_EN 0x100000 2073#define BRXHTDAGC_EN 0x200000 2074#define BRXHT_RXHP_BBP 0x1c00000 2075#define BRXHT_RXHP_FINAL 0xe0000000 2076#define BRXPW_RADIO_TH 0x3 2077#define BRXPW_RADIO_EN 0x4 2078#define BRXMF_HOLD 0x3800 2079#define BRXPD_DELAY_TH1 0x38 2080#define BRXPD_DELAY_TH2 0x1c0 2081#define BRXPD_DC_COUNT_MAX 0x600 2082#define BRXPD_DELAY_TH 0x8000 2083#define BRXPROCESS_DELAY 0xf0000 2084#define BRXSEARCHRANGE_GI2_EARLY 0x700000 2085#define BRXFRAME_FUARD_COUNTER_L 0x3800000 2086#define BRXSGI_GUARD_L 0xc000000 2087#define BRXSGI_SEARCH_L 0x30000000 2088#define BRXSGI_TH 0xc0000000 2089#define BDFSCNT0 0xff 2090#define BDFSCNT1 0xff00 2091#define BDFSFLAG 0xf0000 2092#define BMF_WEIGHT_SUM 0x300000 2093#define BMINIDX_TH 0x7f000000 2094#define BDAFORMAT 0x40000 2095#define BTXCH_EMU_ENABLE 0x01000000 2096#define BTRSW_ISOLATION_A 0x7f 2097#define BTRSW_ISOLATION_B 0x7f00 2098#define BTRSW_ISOLATION_C 0x7f0000 2099#define BTRSW_ISOLATION_D 0x7f000000 2100#define BEXT_LNA_GAIN 0x7c00 2101 2102#define BSTBC_EN 0x4 2103#define BANTENNA_MAPPING 0x10 2104#define BNSS 0x20 2105#define BCFO_ANTSUM_ID 0x200 2106#define BPHY_COUNTER_RESET 0x8000000 2107#define BCFO_REPORT_GET 0x4000000 2108#define BOFDM_CONTINUE_TX 0x10000000 2109#define BOFDM_SINGLE_CARRIER 0x20000000 2110#define BOFDM_SINGLE_TONE 0x40000000 2111#define BHT_DETECT 0x100 2112#define BCFOEN 0x10000 2113#define BCFOVALUE 0xfff00000 2114#define BSIGTONE_RE 0x3f 2115#define BSIGTONE_IM 0x7f00 2116#define BCOUNTER_CCA 0xffff 2117#define BCOUNTER_PARITYFAIL 0xffff0000 2118#define BCOUNTER_RATEILLEGAL 0xffff 2119#define BCOUNTER_CRC8FAIL 0xffff0000 2120#define BCOUNTER_MCSNOSUPPORT 0xffff 2121#define BCOUNTER_FASTSYNC 0xffff 2122#define BSHORTCFO 0xfff 2123#define BSHORTCFOT_LENGTH 12 2124#define BSHORTCFOF_LENGTH 11 2125#define BLONGCFO 0x7ff 2126#define BLONGCFOT_LENGTH 11 2127#define BLONGCFOF_LENGTH 11 2128#define BTAILCFO 0x1fff 2129#define BTAILCFOT_LENGTH 13 2130#define BTAILCFOF_LENGTH 12 2131#define BNOISE_EN_PWDB 0xffff 2132#define BCC_POWER_DB 0xffff0000 2133#define BMOISE_PWDB 0xffff 2134#define BPOWERMEAST_LENGTH 10 2135#define BPOWERMEASF_LENGTH 3 2136#define BRX_HT_BW 0x1 2137#define BRXSC 0x6 2138#define BRX_HT 0x8 2139#define BNB_INTF_DET_ON 0x1 2140#define BINTF_WIN_LEN_CFG 0x30 2141#define BNB_INTF_TH_CFG 0x1c0 2142#define BRFGAIN 0x3f 2143#define BTABLESEL 0x40 2144#define BTRSW 0x80 2145#define BRXSNR_A 0xff 2146#define BRXSNR_B 0xff00 2147#define BRXSNR_C 0xff0000 2148#define BRXSNR_D 0xff000000 2149#define BSNR_EVMT_LENGTH 8 2150#define BSNR_EVMF_LENGTH 1 2151#define BCSI1ST 0xff 2152#define BCSI2ND 0xff00 2153#define BRXEVM1ST 0xff0000 2154#define BRXEVM2ND 0xff000000 2155#define BSIGEVM 0xff 2156#define BPWDB 0xff00 2157#define BSGIEN 0x10000 2158 2159#define BSFACTOR_QMA1 0xf 2160#define BSFACTOR_QMA2 0xf0 2161#define BSFACTOR_QMA3 0xf00 2162#define BSFACTOR_QMA4 0xf000 2163#define BSFACTOR_QMA5 0xf0000 2164#define BSFACTOR_QMA6 0xf0000 2165#define BSFACTOR_QMA7 0xf00000 2166#define BSFACTOR_QMA8 0xf000000 2167#define BSFACTOR_QMA9 0xf0000000 2168#define BCSI_SCHEME 0x100000 2169 2170#define BNOISE_LVL_TOP_SET 0x3 2171#define BCHSMOOTH 0x4 2172#define BCHSMOOTH_CFG1 0x38 2173#define BCHSMOOTH_CFG2 0x1c0 2174#define BCHSMOOTH_CFG3 0xe00 2175#define BCHSMOOTH_CFG4 0x7000 2176#define BMRCMODE 0x800000 2177#define BTHEVMCFG 0x7000000 2178 2179#define BLOOP_FIT_TYPE 0x1 2180#define BUPD_CFO 0x40 2181#define BUPD_CFO_OFFDATA 0x80 2182#define BADV_UPD_CFO 0x100 2183#define BADV_TIME_CTRL 0x800 2184#define BUPD_CLKO 0x1000 2185#define BFC 0x6000 2186#define BTRACKING_MODE 0x8000 2187#define BPHCMP_ENABLE 0x10000 2188#define BUPD_CLKO_LTF 0x20000 2189#define BCOM_CH_CFO 0x40000 2190#define BCSI_ESTI_MODE 0x80000 2191#define BADV_UPD_EQZ 0x100000 2192#define BUCHCFG 0x7000000 2193#define BUPDEQZ 0x8000000 2194 2195#define BRX_PESUDO_NOISE_ON 0x20000000 2196#define BRX_PESUDO_NOISE_A 0xff 2197#define BRX_PESUDO_NOISE_B 0xff00 2198#define BRX_PESUDO_NOISE_C 0xff0000 2199#define BRX_PESUDO_NOISE_D 0xff000000 2200#define BRX_PESUDO_NOISESTATE_A 0xffff 2201#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2202#define BRX_PESUDO_NOISESTATE_C 0xffff 2203#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2204 2205#define BZEBRA1_HSSIENABLE 0x8 2206#define BZEBRA1_TRXCONTROL 0xc00 2207#define BZEBRA1_TRXGAINSETTING 0x07f 2208#define BZEBRA1_RXCOUNTER 0xc00 2209#define BZEBRA1_TXCHANGEPUMP 0x38 2210#define BZEBRA1_RXCHANGEPUMP 0x7 2211#define BZEBRA1_CHANNEL_NUM 0xf80 2212#define BZEBRA1_TXLPFBW 0x400 2213#define BZEBRA1_RXLPFBW 0x600 2214 2215#define BRTL8256REG_MODE_CTRL1 0x100 2216#define BRTL8256REG_MODE_CTRL0 0x40 2217#define BRTL8256REG_TXLPFBW 0x18 2218#define BRTL8256REG_RXLPFBW 0x600 2219 2220#define BRTL8258_TXLPFBW 0xc 2221#define BRTL8258_RXLPFBW 0xc00 2222#define BRTL8258_RSSILPFBW 0xc0 2223 2224#define BBYTE0 0x1 2225#define BBYTE1 0x2 2226#define BBYTE2 0x4 2227#define BBYTE3 0x8 2228#define BWORD0 0x3 2229#define BWORD1 0xc 2230#define BWORD 0xf 2231 2232#define MASKBYTE0 0xff 2233#define MASKBYTE1 0xff00 2234#define MASKBYTE2 0xff0000 2235#define MASKBYTE3 0xff000000 2236#define MASKHWORD 0xffff0000 2237#define MASKLWORD 0x0000ffff 2238#define MASKDWORD 0xffffffff 2239#define MASK12BITS 0xfff 2240#define MASKH4BITS 0xf0000000 2241#define MASKOFDM_D 0xffc00000 2242#define MASKCCK 0x3f3f3f3f 2243 2244#define MASK4BITS 0x0f 2245#define MASK20BITS 0xfffff 2246#define RFREG_OFFSET_MASK 0xfffff 2247 2248#define BENABLE 0x1 2249#define BDISABLE 0x0 2250 2251#define LEFT_ANTENNA 0x0 2252#define RIGHT_ANTENNA 0x1 2253 2254#define TCHECK_TXSTATUS 500 2255#define TUPDATE_RXCOUNTER 100 2256 2257#define REG_UN_used_register 0x01bf 2258 2259/* WOL bit information */ 2260#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) 2261#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) 2262#define HAL92C_WOL_DISASSOC_EVENT BIT(2) 2263#define HAL92C_WOL_DEAUTH_EVENT BIT(3) 2264#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) 2265 2266#define WOL_REASON_PTK_UPDATE BIT(0) 2267#define WOL_REASON_GTK_UPDATE BIT(1) 2268#define WOL_REASON_DISASSOC BIT(2) 2269#define WOL_REASON_DEAUTH BIT(3) 2270#define WOL_REASON_FW_DISCONNECT BIT(4) 2271#endif 2272