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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012  Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8723E_DEF_H__
27#define __RTL8723E_DEF_H__
28
29#define HAL_RETRY_LIMIT_INFRA				48
30#define HAL_RETRY_LIMIT_AP_ADHOC			7
31
32#define RESET_DELAY_8185					20
33
34#define RT_IBSS_INT_MASKS	(IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
35#define RT_AC_INT_MASKS		(IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
36
37#define NUM_OF_FIRMWARE_QUEUE				10
38#define NUM_OF_PAGES_IN_FW					0x100
39#define NUM_OF_PAGE_IN_FW_QUEUE_BK			0x07
40#define NUM_OF_PAGE_IN_FW_QUEUE_BE			0x07
41#define NUM_OF_PAGE_IN_FW_QUEUE_VI			0x07
42#define NUM_OF_PAGE_IN_FW_QUEUE_VO			0x07
43#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA		0x0
44#define NUM_OF_PAGE_IN_FW_QUEUE_CMD			0x0
45#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT		0x02
46#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH		0x02
47#define NUM_OF_PAGE_IN_FW_QUEUE_BCN			0x2
48#define NUM_OF_PAGE_IN_FW_QUEUE_PUB			0xA1
49
50#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM		0x026
51#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM		0x048
52#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM		0x048
53#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM		0x026
54#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM		0x00
55
56#define MAX_LINES_HWCONFIG_TXT				1000
57#define MAX_BYTES_LINE_HWCONFIG_TXT			256
58
59#define SW_THREE_WIRE						0
60#define HW_THREE_WIRE						2
61
62#define BT_DEMO_BOARD						0
63#define BT_QA_BOARD							1
64#define BT_FPGA								2
65
66#define HAL_PRIME_CHNL_OFFSET_DONT_CARE		0
67#define HAL_PRIME_CHNL_OFFSET_LOWER			1
68#define HAL_PRIME_CHNL_OFFSET_UPPER			2
69
70#define MAX_H2C_QUEUE_NUM					10
71
72#define RX_MPDU_QUEUE						0
73#define RX_CMD_QUEUE						1
74#define RX_MAX_QUEUE						2
75#define AC2QUEUEID(_AC)						(_AC)
76
77#define	C2H_RX_CMD_HDR_LEN					8
78#define	GET_C2H_CMD_CMD_LEN(__prxhdr)		\
79	LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
80#define	GET_C2H_CMD_ELEMENT_ID(__prxhdr)	\
81	LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
82#define	GET_C2H_CMD_CMD_SEQ(__prxhdr)		\
83	LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
84#define	GET_C2H_CMD_CONTINUE(__prxhdr)		\
85	LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
86#define	GET_C2H_CMD_CONTENT(__prxhdr)		\
87	((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
88
89#define	GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)	\
90	LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
91#define	GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)		\
92	LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
93#define	GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)	\
94	LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
95#define	GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)	\
96	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
97#define	GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)		\
98	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
99#define	GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr)	\
100	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
101#define	GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)		\
102	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
103#define	GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)		\
104	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
105#define	GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)		\
106	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
107
108#define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22)&0x3)
109#define	CHIP_BONDING_92C_1T2R		0x1
110
111#define CHIP_8723		BIT(0)
112#define NORMAL_CHIP		BIT(3)
113#define RF_TYPE_1T1R		(~(BIT(4)|BIT(5)|BIT(6)))
114#define RF_TYPE_1T2R		BIT(4)
115#define RF_TYPE_2T2R		BIT(5)
116#define CHIP_VENDOR_UMC		BIT(7)
117#define B_CUT_VERSION		BIT(12)
118#define C_CUT_VERSION		BIT(13)
119#define D_CUT_VERSION		((BIT(12)|BIT(13)))
120#define E_CUT_VERSION		BIT(14)
121#define	RF_RL_ID		(BIT(31)|BIT(30)|BIT(29)|BIT(28))
122
123/* MASK */
124#define IC_TYPE_MASK		(BIT(0)|BIT(1)|BIT(2))
125#define CHIP_TYPE_MASK		BIT(3)
126#define RF_TYPE_MASK		(BIT(4)|BIT(5)|BIT(6))
127#define MANUFACTUER_MASK	BIT(7)
128#define ROM_VERSION_MASK	(BIT(11)|BIT(10)|BIT(9)|BIT(8))
129#define CUT_VERSION_MASK	(BIT(15)|BIT(14)|BIT(13)|BIT(12))
130
131/* Get element */
132#define GET_CVID_IC_TYPE(version)	((version) & IC_TYPE_MASK)
133#define GET_CVID_CHIP_TYPE(version)	((version) & CHIP_TYPE_MASK)
134#define GET_CVID_RF_TYPE(version)	((version) & RF_TYPE_MASK)
135#define GET_CVID_MANUFACTUER(version)	((version) & MANUFACTUER_MASK)
136#define GET_CVID_ROM_VERSION(version)	((version) & ROM_VERSION_MASK)
137#define GET_CVID_CUT_VERSION(version)	((version) & CUT_VERSION_MASK)
138
139#define IS_81XXC(version)	((GET_CVID_IC_TYPE(version) == 0) ?\
140						true : false)
141#define IS_8723_SERIES(version)	((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \
142						true : false)
143#define IS_1T1R(version)	((GET_CVID_RF_TYPE(version)) ? false : true)
144#define IS_1T2R(version)	((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
145						? true : false)
146#define IS_2T2R(version)	((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
147						? true : false)
148#define IS_CHIP_VENDOR_UMC(version)	((GET_CVID_MANUFACTUER(version)) ? \
149						true : false)
150
151#define IS_VENDOR_UMC_A_CUT(version)	((IS_CHIP_VENDOR_UMC(version))\
152					? ((GET_CVID_CUT_VERSION(version)) ? \
153					false : true) : false)
154#define IS_VENDOR_8723_A_CUT(version)	((IS_8723_SERIES(version))\
155					? ((GET_CVID_CUT_VERSION(version)) ? \
156					false : true) : false)
157#define IS_VENDOR_8723A_B_CUT(version)	((IS_8723_SERIES(version))\
158		? ((GET_CVID_CUT_VERSION(version) == \
159		B_CUT_VERSION) ? true : false) : false)
160#define IS_81xxC_VENDOR_UMC_B_CUT(version)	((IS_CHIP_VENDOR_UMC(version))\
161		? ((GET_CVID_CUT_VERSION(version) == \
162		B_CUT_VERSION) ? true : false) : false)
163
164enum rf_optype {
165	RF_OP_BY_SW_3WIRE = 0,
166	RF_OP_BY_FW,
167	RF_OP_MAX
168};
169
170enum rf_power_state {
171	RF_ON,
172	RF_OFF,
173	RF_SLEEP,
174	RF_SHUT_DOWN,
175};
176
177enum power_save_mode {
178	POWER_SAVE_MODE_ACTIVE,
179	POWER_SAVE_MODE_SAVE,
180};
181
182enum power_policy_config {
183	POWERCFG_MAX_POWER_SAVINGS,
184	POWERCFG_GLOBAL_POWER_SAVINGS,
185	POWERCFG_LOCAL_POWER_SAVINGS,
186	POWERCFG_LENOVO,
187};
188
189enum interface_select_pci {
190	INTF_SEL1_MINICARD = 0,
191	INTF_SEL0_PCIE = 1,
192	INTF_SEL2_RSV = 2,
193	INTF_SEL3_RSV = 3,
194};
195
196enum hal_fw_c2h_cmd_id {
197	HAL_FW_C2H_CMD_Read_MACREG = 0,
198	HAL_FW_C2H_CMD_Read_BBREG = 1,
199	HAL_FW_C2H_CMD_Read_RFREG = 2,
200	HAL_FW_C2H_CMD_Read_EEPROM = 3,
201	HAL_FW_C2H_CMD_Read_EFUSE = 4,
202	HAL_FW_C2H_CMD_Read_CAM = 5,
203	HAL_FW_C2H_CMD_Get_BasicRate = 6,
204	HAL_FW_C2H_CMD_Get_DataRate = 7,
205	HAL_FW_C2H_CMD_Survey = 8,
206	HAL_FW_C2H_CMD_SurveyDone = 9,
207	HAL_FW_C2H_CMD_JoinBss = 10,
208	HAL_FW_C2H_CMD_AddSTA = 11,
209	HAL_FW_C2H_CMD_DelSTA = 12,
210	HAL_FW_C2H_CMD_AtimDone = 13,
211	HAL_FW_C2H_CMD_TX_Report = 14,
212	HAL_FW_C2H_CMD_CCX_Report = 15,
213	HAL_FW_C2H_CMD_DTM_Report = 16,
214	HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
215	HAL_FW_C2H_CMD_C2HLBK = 18,
216	HAL_FW_C2H_CMD_C2HDBG = 19,
217	HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
218	HAL_FW_C2H_CMD_MAX
219};
220
221enum rtl_desc_qsel {
222	QSLT_BK = 0x2,
223	QSLT_BE = 0x0,
224	QSLT_VI = 0x5,
225	QSLT_VO = 0x7,
226	QSLT_BEACON = 0x10,
227	QSLT_HIGH = 0x11,
228	QSLT_MGNT = 0x12,
229	QSLT_CMD = 0x13,
230};
231
232enum rtl_desc8723e_rate {
233	DESC92C_RATE1M = 0x00,
234	DESC92C_RATE2M = 0x01,
235	DESC92C_RATE5_5M = 0x02,
236	DESC92C_RATE11M = 0x03,
237
238	DESC92C_RATE6M = 0x04,
239	DESC92C_RATE9M = 0x05,
240	DESC92C_RATE12M = 0x06,
241	DESC92C_RATE18M = 0x07,
242	DESC92C_RATE24M = 0x08,
243	DESC92C_RATE36M = 0x09,
244	DESC92C_RATE48M = 0x0a,
245	DESC92C_RATE54M = 0x0b,
246
247	DESC92C_RATEMCS0 = 0x0c,
248	DESC92C_RATEMCS1 = 0x0d,
249	DESC92C_RATEMCS2 = 0x0e,
250	DESC92C_RATEMCS3 = 0x0f,
251	DESC92C_RATEMCS4 = 0x10,
252	DESC92C_RATEMCS5 = 0x11,
253	DESC92C_RATEMCS6 = 0x12,
254	DESC92C_RATEMCS7 = 0x13,
255	DESC92C_RATEMCS8 = 0x14,
256	DESC92C_RATEMCS9 = 0x15,
257	DESC92C_RATEMCS10 = 0x16,
258	DESC92C_RATEMCS11 = 0x17,
259	DESC92C_RATEMCS12 = 0x18,
260	DESC92C_RATEMCS13 = 0x19,
261	DESC92C_RATEMCS14 = 0x1a,
262	DESC92C_RATEMCS15 = 0x1b,
263	DESC92C_RATEMCS15_SG = 0x1c,
264	DESC92C_RATEMCS32 = 0x20,
265};
266
267struct phy_sts_cck_8723e_t {
268	u8 adc_pwdb_X[4];
269	u8 sq_rpt;
270	u8 cck_agc_rpt;
271};
272
273struct h2c_cmd_8723e {
274	u8 element_id;
275	u32 cmd_len;
276	u8 *p_cmdbuffer;
277};
278
279#endif
280