1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL8723E_DM_H__ 31#define __RTL8723E_DM_H__ 32 33#define HAL_DM_DIG_DISABLE BIT(0) 34#define HAL_DM_HIPWR_DISABLE BIT(1) 35 36#define OFDM_TABLE_LENGTH 37 37#define CCK_TABLE_LENGTH 33 38 39#define OFDM_TABLE_SIZE 37 40#define CCK_TABLE_SIZE 33 41 42#define BW_AUTO_SWITCH_HIGH_LOW 25 43#define BW_AUTO_SWITCH_LOW_HIGH 30 44 45#define DM_DIG_THRESH_HIGH 40 46#define DM_DIG_THRESH_LOW 35 47 48#define DM_FALSEALARM_THRESH_LOW 400 49#define DM_FALSEALARM_THRESH_HIGH 1000 50 51#define DM_DIG_MAX 0x3e 52#define DM_DIG_MIN 0x1e 53 54#define DM_DIG_FA_UPPER 0x32 55#define DM_DIG_FA_LOWER 0x20 56#define DM_DIG_FA_TH0 0x20 57#define DM_DIG_FA_TH1 0x100 58#define DM_DIG_FA_TH2 0x200 59 60#define DM_DIG_BACKOFF_MAX 12 61#define DM_DIG_BACKOFF_MIN -4 62#define DM_DIG_BACKOFF_DEFAULT 10 63 64#define RXPATHSELECTION_SS_TH_LOW 30 65#define RXPATHSELECTION_DIFF_TH 18 66 67#define DM_RATR_STA_INIT 0 68#define DM_RATR_STA_HIGH 1 69#define DM_RATR_STA_MIDDLE 2 70#define DM_RATR_STA_LOW 3 71 72#define CTS2SELF_THVAL 30 73#define REGC38_TH 20 74 75#define WAIOTTHVAL 25 76 77#define TXHIGHPWRLEVEL_NORMAL 0 78#define TXHIGHPWRLEVEL_LEVEL1 1 79#define TXHIGHPWRLEVEL_LEVEL2 2 80#define TXHIGHPWRLEVEL_BT1 3 81#define TXHIGHPWRLEVEL_BT2 4 82 83#define DM_TYPE_BYFW 0 84#define DM_TYPE_BYDRIVER 1 85 86#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 87#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 88 89struct swat_t { 90 u8 failure_cnt; 91 u8 try_flag; 92 u8 stop_trying; 93 long pre_rssi; 94 long trying_threshold; 95 u8 cur_antenna; 96 u8 pre_antenna; 97 98}; 99 100enum tag_dynamic_init_gain_operation_type_definition { 101 DIG_TYPE_THRESH_HIGH = 0, 102 DIG_TYPE_THRESH_LOW = 1, 103 DIG_TYPE_BACKOFF = 2, 104 DIG_TYPE_RX_GAIN_MIN = 3, 105 DIG_TYPE_RX_GAIN_MAX = 4, 106 DIG_TYPE_ENABLE = 5, 107 DIG_TYPE_DISABLE = 6, 108 DIG_OP_TYPE_MAX 109}; 110 111enum tag_cck_packet_detection_threshold_type_definition { 112 CCK_PD_STAGE_LowRssi = 0, 113 CCK_PD_STAGE_HighRssi = 1, 114 CCK_FA_STAGE_LOW = 2, 115 CCK_FA_STAGE_High = 3, 116 CCK_PD_STAGE_MAX = 4, 117}; 118 119enum dm_1r_cca_e { 120 CCA_1R = 0, 121 CCA_2R = 1, 122 CCA_MAX = 2, 123}; 124 125enum dm_rf_e { 126 RF_SAVE = 0, 127 RF_NORMAL = 1, 128 RF_MAX = 2, 129}; 130 131enum dm_sw_ant_switch_e { 132 ANS_ANTENNA_B = 1, 133 ANS_ANTENNA_A = 2, 134 ANS_ANTENNA_MAX = 3, 135}; 136 137enum dm_dig_ext_port_alg_e { 138 DIG_EXT_PORT_STAGE_0 = 0, 139 DIG_EXT_PORT_STAGE_1 = 1, 140 DIG_EXT_PORT_STAGE_2 = 2, 141 DIG_EXT_PORT_STAGE_3 = 3, 142 DIG_EXT_PORT_STAGE_MAX = 4, 143}; 144 145enum dm_dig_connect_e { 146 DIG_STA_DISCONNECT = 0, 147 DIG_STA_CONNECT = 1, 148 DIG_STA_BEFORE_CONNECT = 2, 149 DIG_MULTISTA_DISCONNECT = 3, 150 DIG_MULTISTA_CONNECT = 4, 151 DIG_CONNECT_MAX 152}; 153 154#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1) 155#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1) 156#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) 157#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1) 158#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1) 159#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \ 160 ( \ 161 (((struct rtl_priv *)(_priv))->mac80211.opmode == \ 162 NL80211_IFTYPE_ADHOC) ? \ 163 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \ 164 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb) \ 165 ) 166 167void rtl8723e_dm_init(struct ieee80211_hw *hw); 168void rtl8723e_dm_watchdog(struct ieee80211_hw *hw); 169void rtl8723e_dm_write_dig(struct ieee80211_hw *hw); 170void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw); 171void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 172void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 173void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw); 174#endif 175