1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 22#ifndef __HALDMOUTSRC_H__ 23#define __HALDMOUTSRC_H__ 24 25/* Definition */ 26/* Define all team support ability. */ 27 28/* Define for all teams. Please Define the constant in your precomp header. */ 29 30/* define DM_ODM_SUPPORT_AP 0 */ 31/* define DM_ODM_SUPPORT_ADSL 0 */ 32/* define DM_ODM_SUPPORT_CE 0 */ 33/* define DM_ODM_SUPPORT_MP 1 */ 34 35/* Define ODM SW team support flag. */ 36 37/* Antenna Switch Relative Definition. */ 38 39/* Add new function SwAntDivCheck8192C(). */ 40/* This is the main function of Antenna diversity function before link. */ 41/* Mainly, it just retains last scan result and scan again. */ 42/* After that, it compares the scan result to see which one gets better 43 * RSSI. It selects antenna with better receiving power and returns better 44 * scan result. */ 45 46#define TP_MODE 0 47#define RSSI_MODE 1 48#define TRAFFIC_LOW 0 49#define TRAFFIC_HIGH 1 50 51/* 3 Tx Power Tracking */ 52/* 3============================================================ */ 53#define DPK_DELTA_MAPPING_NUM 13 54#define index_mapping_HP_NUM 15 55 56 57/* */ 58/* 3 PSD Handler */ 59/* 3============================================================ */ 60 61#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 62#define MODE_40M 0 /* 0:20M, 1:40M */ 63#define PSD_TH2 3 64#define PSD_CHM 20 /* Minimum channel number for BT AFH */ 65#define SIR_STEP_SIZE 3 66#define Smooth_Size_1 5 67#define Smooth_TH_1 3 68#define Smooth_Size_2 10 69#define Smooth_TH_2 4 70#define Smooth_Size_3 20 71#define Smooth_TH_3 4 72#define Smooth_Step_Size 5 73#define Adaptive_SIR 1 74#define PSD_RESCAN 4 75#define PSD_SCAN_INTERVAL 700 /* ms */ 76 77/* 8723A High Power IGI Setting */ 78#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 79#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 80#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 81 82/* LPS define */ 83#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ 84#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ 85#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ 86#define RSSI_OFFSET_DIG 0x05; 87 88/* ANT Test */ 89#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 90#define ANTTESTA 0x01 /* Ant A will be Testing */ 91#define ANTTESTB 0x02 /* Ant B will be testing */ 92 93struct rtw_dig { 94 u8 Dig_Enable_Flag; 95 u8 Dig_Ext_Port_Stage; 96 97 int RssiLowThresh; 98 int RssiHighThresh; 99 100 u32 FALowThresh; 101 u32 FAHighThresh; 102 103 u8 CurSTAConnectState; 104 u8 PreSTAConnectState; 105 u8 CurMultiSTAConnectState; 106 107 u8 PreIGValue; 108 u8 CurIGValue; 109 u8 BackupIGValue; 110 111 s8 BackoffVal; 112 s8 BackoffVal_range_max; 113 s8 BackoffVal_range_min; 114 u8 rx_gain_range_max; 115 u8 rx_gain_range_min; 116 u8 Rssi_val_min; 117 118 u8 PreCCK_CCAThres; 119 u8 CurCCK_CCAThres; 120 u8 PreCCKPDState; 121 u8 CurCCKPDState; 122 123 u8 LargeFAHit; 124 u8 ForbiddenIGI; 125 u32 Recover_cnt; 126 127 u8 DIG_Dynamic_MIN_0; 128 u8 DIG_Dynamic_MIN_1; 129 bool bMediaConnect_0; 130 bool bMediaConnect_1; 131 132 u32 AntDiv_RSSI_max; 133 u32 RSSI_max; 134}; 135 136struct rtl_ps { 137 u8 PreCCAState; 138 u8 CurCCAState; 139 140 u8 PreRFState; 141 u8 CurRFState; 142 143 int Rssi_val_min; 144 145 u8 initialize; 146 u32 Reg874, RegC70, Reg85C, RegA74; 147 148}; 149 150struct false_alarm_stats { 151 u32 Cnt_Parity_Fail; 152 u32 Cnt_Rate_Illegal; 153 u32 Cnt_Crc8_fail; 154 u32 Cnt_Mcs_fail; 155 u32 Cnt_Ofdm_fail; 156 u32 Cnt_Cck_fail; 157 u32 Cnt_all; 158 u32 Cnt_Fast_Fsync; 159 u32 Cnt_SB_Search_fail; 160 u32 Cnt_OFDM_CCA; 161 u32 Cnt_CCK_CCA; 162 u32 Cnt_CCA_all; 163 u32 Cnt_BW_USC; /* Gary */ 164 u32 Cnt_BW_LSC; /* Gary */ 165}; 166 167struct rx_hpc { 168 u8 RXHP_flag; 169 u8 PSD_func_trigger; 170 u8 PSD_bitmap_RXHP[80]; 171 u8 Pre_IGI; 172 u8 Cur_IGI; 173 u8 Pre_pw_th; 174 u8 Cur_pw_th; 175 bool First_time_enter; 176 bool RXHP_enable; 177 u8 TP_Mode; 178 struct timer_list PSDTimer; 179}; 180 181#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 182#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 183 184/* This indicates two different steps. */ 185/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to 186 * the signal on the air. */ 187/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in 188 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to 189 * switch antenna. */ 190 191#define SWAW_STEP_PEAK 0 192#define SWAW_STEP_DETERMINE 1 193 194#define TP_MODE 0 195#define RSSI_MODE 1 196#define TRAFFIC_LOW 0 197#define TRAFFIC_HIGH 1 198 199struct sw_ant_switch { 200 u8 try_flag; 201 s32 PreRSSI; 202 u8 CurAntenna; 203 u8 PreAntenna; 204 u8 RSSI_Trying; 205 u8 TestMode; 206 u8 bTriggerAntennaSwitch; 207 u8 SelectAntennaMap; 208 u8 RSSI_target; 209 210 /* Before link Antenna Switch check */ 211 u8 SWAS_NoLink_State; 212 u32 SWAS_NoLink_BK_Reg860; 213 bool ANTA_ON; /* To indicate Ant A is or not */ 214 bool ANTB_ON; /* To indicate Ant B is on or not */ 215 216 s32 RSSI_sum_A; 217 s32 RSSI_sum_B; 218 s32 RSSI_cnt_A; 219 s32 RSSI_cnt_B; 220 u64 lastTxOkCnt; 221 u64 lastRxOkCnt; 222 u64 TXByteCnt_A; 223 u64 TXByteCnt_B; 224 u64 RXByteCnt_A; 225 u64 RXByteCnt_B; 226 u8 TrafficLoad; 227 struct timer_list SwAntennaSwitchTimer; 228 /* Hybrid Antenna Diversity */ 229 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; 230 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; 231 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; 232 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; 233 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; 234 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; 235 u8 TxAnt[ASSOCIATE_ENTRY_NUM]; 236 u8 TargetSTA; 237 u8 antsel; 238 u8 RxIdleAnt; 239}; 240 241struct edca_turbo { 242 bool bCurrentTurboEDCA; 243 bool bIsCurRDLState; 244 u32 prv_traffic_idx; /* edca turbo */ 245}; 246 247struct odm_rate_adapt { 248 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 249 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 250 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 251 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 252 u32 LastRATR; /* RATR Register Content */ 253}; 254 255#define IQK_MAC_REG_NUM 4 256#define IQK_ADDA_REG_NUM 16 257#define IQK_BB_REG_NUM_MAX 10 258#define IQK_BB_REG_NUM 9 259#define HP_THERMAL_NUM 8 260 261#define AVG_THERMAL_NUM 8 262#define IQK_Matrix_REG_NUM 8 263#define IQK_Matrix_Settings_NUM 1+24+21 264 265#define DM_Type_ByFWi 0 266#define DM_Type_ByDriver 1 267 268/* Declare for common info */ 269 270struct odm_phy_status_info { 271 u8 RxPWDBAll; 272 u8 SignalQuality; /* in 0-100 index. */ 273 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ 274 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ 275 s8 RxPower; /* in dBm Translate from PWdB */ 276 s8 RecvSignalPower;/* Real power in dBm for this packet, no 277 * beautification and aggregation. Keep this raw 278 * info to be used for the other procedures. */ 279 u8 BTRxRSSIPercentage; 280 u8 SignalStrength; /* in 0-100 index. */ 281 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ 282 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ 283}; 284 285struct odm_phy_dbg_info { 286 /* ODM Write,debug info */ 287 s8 RxSNRdB[MAX_PATH_NUM_92CS]; 288 u64 NumQryPhyStatus; 289 u64 NumQryPhyStatusCCK; 290 u64 NumQryPhyStatusOFDM; 291 /* Others */ 292 s32 RxEVM[MAX_PATH_NUM_92CS]; 293}; 294 295struct odm_per_pkt_info { 296 s8 Rate; 297 u8 StationID; 298 bool bPacketMatchBSSID; 299 bool bPacketToSelf; 300 bool bPacketBeacon; 301}; 302 303struct odm_mac_status_info { 304 u8 test; 305}; 306 307enum odm_ability { 308 /* BB Team */ 309 ODM_DIG = 0x00000001, 310 ODM_HIGH_POWER = 0x00000002, 311 ODM_CCK_CCA_TH = 0x00000004, 312 ODM_FA_STATISTICS = 0x00000008, 313 ODM_RAMASK = 0x00000010, 314 ODM_RSSI_MONITOR = 0x00000020, 315 ODM_SW_ANTDIV = 0x00000040, 316 ODM_HW_ANTDIV = 0x00000080, 317 ODM_BB_PWRSV = 0x00000100, 318 ODM_2TPATHDIV = 0x00000200, 319 ODM_1TPATHDIV = 0x00000400, 320 ODM_PSD2AFH = 0x00000800 321}; 322 323/* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ 324/* Please declare below ODM relative info in your STA info structure. */ 325 326struct odm_sta_info { 327 /* Driver Write */ 328 bool bUsed; /* record the sta status link or not? */ 329 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ 330 331 /* ODM Write */ 332 /* 1 PHY_STATUS_INFO */ 333 u8 RSSI_Path[4]; /* */ 334 u8 RSSI_Ave; 335 u8 RXEVM[4]; 336 u8 RXSNR[4]; 337}; 338 339/* 2011/10/20 MH Define Common info enum for all team. */ 340 341enum odm_common_info_def { 342 /* Fixed value: */ 343 344 /* HOOK BEFORE REG INIT----------- */ 345 ODM_CMNINFO_PLATFORM = 0, 346 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 347 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 348 ODM_CMNINFO_MP_TEST_CHIP, 349 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 350 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 351 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 352 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 353 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 354 ODM_CMNINFO_EXT_LNA, /* true */ 355 ODM_CMNINFO_EXT_PA, 356 ODM_CMNINFO_EXT_TRSW, 357 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 358 ODM_CMNINFO_BINHCT_TEST, 359 ODM_CMNINFO_BWIFI_TEST, 360 ODM_CMNINFO_SMART_CONCURRENT, 361 /* HOOK BEFORE REG INIT----------- */ 362 363 /* Dynamic value: */ 364/* POINTER REFERENCE----------- */ 365 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 366 ODM_CMNINFO_TX_UNI, 367 ODM_CMNINFO_RX_UNI, 368 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 369 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ 370 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 371 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 372 ODM_CMNINFO_BW, /* ODM_BW_E */ 373 ODM_CMNINFO_CHNL, 374 375 ODM_CMNINFO_DMSP_GET_VALUE, 376 ODM_CMNINFO_BUDDY_ADAPTOR, 377 ODM_CMNINFO_DMSP_IS_MASTER, 378 ODM_CMNINFO_SCAN, 379 ODM_CMNINFO_POWER_SAVING, 380 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 381 ODM_CMNINFO_DRV_STOP, 382 ODM_CMNINFO_PNP_IN, 383 ODM_CMNINFO_INIT_ON, 384 ODM_CMNINFO_ANT_TEST, 385 ODM_CMNINFO_NET_CLOSED, 386 ODM_CMNINFO_MP_MODE, 387/* POINTER REFERENCE----------- */ 388 389/* CALL BY VALUE------------- */ 390 ODM_CMNINFO_WIFI_DIRECT, 391 ODM_CMNINFO_WIFI_DISPLAY, 392 ODM_CMNINFO_LINK, 393 ODM_CMNINFO_RSSI_MIN, 394 ODM_CMNINFO_DBG_COMP, /* u64 */ 395 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 396 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 397 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 398 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 399 ODM_CMNINFO_BT_DISABLED, 400 ODM_CMNINFO_BT_OPERATION, 401 ODM_CMNINFO_BT_DIG, 402 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ 403 ODM_CMNINFO_BT_DISABLE_EDCA, 404/* CALL BY VALUE-------------*/ 405 406 /* Dynamic ptr array hook itms. */ 407 ODM_CMNINFO_STA_STATUS, 408 ODM_CMNINFO_PHY_STATUS, 409 ODM_CMNINFO_MAC_STATUS, 410 ODM_CMNINFO_MAX, 411}; 412 413/* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 414 415enum odm_ability_def { 416 /* BB ODM section BIT 0-15 */ 417 ODM_BB_DIG = BIT0, 418 ODM_BB_RA_MASK = BIT1, 419 ODM_BB_DYNAMIC_TXPWR = BIT2, 420 ODM_BB_FA_CNT = BIT3, 421 ODM_BB_RSSI_MONITOR = BIT4, 422 ODM_BB_CCK_PD = BIT5, 423 ODM_BB_ANT_DIV = BIT6, 424 ODM_BB_PWR_SAVE = BIT7, 425 ODM_BB_PWR_TRA = BIT8, 426 ODM_BB_RATE_ADAPTIVE = BIT9, 427 ODM_BB_PATH_DIV = BIT10, 428 ODM_BB_PSD = BIT11, 429 ODM_BB_RXHP = BIT12, 430 431 /* MAC DM section BIT 16-23 */ 432 ODM_MAC_EDCA_TURBO = BIT16, 433 ODM_MAC_EARLY_MODE = BIT17, 434 435 /* RF ODM section BIT 24-31 */ 436 ODM_RF_TX_PWR_TRACK = BIT24, 437 ODM_RF_RX_GAIN_TRACK = BIT25, 438 ODM_RF_CALIBRATION = BIT26, 439}; 440 441#define ODM_RTL8188E BIT4 442 443/* ODM_CMNINFO_CUT_VER */ 444enum odm_cut_version { 445 ODM_CUT_A = 1, 446 ODM_CUT_B = 2, 447 ODM_CUT_C = 3, 448 ODM_CUT_D = 4, 449 ODM_CUT_E = 5, 450 ODM_CUT_F = 6, 451 ODM_CUT_TEST = 7, 452}; 453 454/* ODM_CMNINFO_FAB_VER */ 455enum odm_fab_Version { 456 ODM_TSMC = 0, 457 ODM_UMC = 1, 458}; 459 460/* ODM_CMNINFO_RF_TYPE */ 461/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 462enum odm_rf_path { 463 ODM_RF_TX_A = BIT0, 464 ODM_RF_TX_B = BIT1, 465 ODM_RF_TX_C = BIT2, 466 ODM_RF_TX_D = BIT3, 467 ODM_RF_RX_A = BIT4, 468 ODM_RF_RX_B = BIT5, 469 ODM_RF_RX_C = BIT6, 470 ODM_RF_RX_D = BIT7, 471}; 472 473enum odm_rf_type { 474 ODM_1T1R = 0, 475 ODM_1T2R = 1, 476 ODM_2T2R = 2, 477 ODM_2T3R = 3, 478 ODM_2T4R = 4, 479 ODM_3T3R = 5, 480 ODM_3T4R = 6, 481 ODM_4T4R = 7, 482}; 483 484/* ODM Dynamic common info value definition */ 485 486enum odm_mac_phy_mode { 487 ODM_SMSP = 0, 488 ODM_DMSP = 1, 489 ODM_DMDP = 2, 490}; 491 492enum odm_bt_coexist { 493 ODM_BT_BUSY = 1, 494 ODM_BT_ON = 2, 495 ODM_BT_OFF = 3, 496 ODM_BT_NONE = 4, 497}; 498 499/* ODM_CMNINFO_OP_MODE */ 500enum odm_operation_mode { 501 ODM_NO_LINK = BIT0, 502 ODM_LINK = BIT1, 503 ODM_SCAN = BIT2, 504 ODM_POWERSAVE = BIT3, 505 ODM_AP_MODE = BIT4, 506 ODM_CLIENT_MODE = BIT5, 507 ODM_AD_HOC = BIT6, 508 ODM_WIFI_DIRECT = BIT7, 509 ODM_WIFI_DISPLAY = BIT8, 510}; 511 512/* ODM_CMNINFO_WM_MODE */ 513enum odm_wireless_mode { 514 ODM_WM_UNKNOW = 0x0, 515 ODM_WM_B = BIT0, 516 ODM_WM_G = BIT1, 517 ODM_WM_A = BIT2, 518 ODM_WM_N24G = BIT3, 519 ODM_WM_N5G = BIT4, 520 ODM_WM_AUTO = BIT5, 521 ODM_WM_AC = BIT6, 522}; 523 524/* ODM_CMNINFO_BAND */ 525enum odm_band_type { 526 ODM_BAND_2_4G = BIT0, 527 ODM_BAND_5G = BIT1, 528}; 529 530/* ODM_CMNINFO_SEC_CHNL_OFFSET */ 531enum odm_sec_chnl_offset { 532 ODM_DONT_CARE = 0, 533 ODM_BELOW = 1, 534 ODM_ABOVE = 2 535}; 536 537/* ODM_CMNINFO_SEC_MODE */ 538enum odm_security { 539 ODM_SEC_OPEN = 0, 540 ODM_SEC_WEP40 = 1, 541 ODM_SEC_TKIP = 2, 542 ODM_SEC_RESERVE = 3, 543 ODM_SEC_AESCCMP = 4, 544 ODM_SEC_WEP104 = 5, 545 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 546 ODM_SEC_SMS4 = 7, 547}; 548 549/* ODM_CMNINFO_BW */ 550enum odm_bw { 551 ODM_BW20M = 0, 552 ODM_BW40M = 1, 553 ODM_BW80M = 2, 554 ODM_BW160M = 3, 555 ODM_BW10M = 4, 556}; 557 558/* ODM_CMNINFO_BOARD_TYPE */ 559enum odm_board_type { 560 ODM_BOARD_NORMAL = 0, 561 ODM_BOARD_HIGHPWR = 1, 562 ODM_BOARD_MINICARD = 2, 563 ODM_BOARD_SLIM = 3, 564 ODM_BOARD_COMBO = 4, 565}; 566 567/* ODM_CMNINFO_ONE_PATH_CCA */ 568enum odm_cca_path { 569 ODM_CCA_2R = 0, 570 ODM_CCA_1R_A = 1, 571 ODM_CCA_1R_B = 2, 572}; 573 574struct odm_ra_info { 575 u8 RateID; 576 u32 RateMask; 577 u32 RAUseRate; 578 u8 RateSGI; 579 u8 RssiStaRA; 580 u8 PreRssiStaRA; 581 u8 SGIEnable; 582 u8 DecisionRate; 583 u8 PreRate; 584 u8 HighestRate; 585 u8 LowestRate; 586 u32 NscUp; 587 u32 NscDown; 588 u16 RTY[5]; 589 u32 TOTAL; 590 u16 DROP; 591 u8 Active; 592 u16 RptTime; 593 u8 RAWaitingCounter; 594 u8 RAPendingCounter; 595 u8 PTActive; /* on or off */ 596 u8 PTTryState; /* 0 trying state, 1 for decision state */ 597 u8 PTStage; /* 0~6 */ 598 u8 PTStopCount; /* Stop PT counter */ 599 u8 PTPreRate; /* if rate change do PT */ 600 u8 PTPreRssi; /* if RSSI change 5% do PT */ 601 u8 PTModeSS; /* decide whitch rate should do PT */ 602 u8 RAstage; /* StageRA, decide how many times RA will be done 603 * between PT */ 604 u8 PTSmoothFactor; 605}; 606 607struct ijk_matrix_regs_set { 608 bool bIQKDone; 609 s32 Value[1][IQK_Matrix_REG_NUM]; 610}; 611 612struct odm_rf_cal { 613 /* for tx power tracking */ 614 u32 RegA24; /* for TempCCK */ 615 s32 RegE94; 616 s32 RegE9C; 617 s32 RegEB4; 618 s32 RegEBC; 619 620 u8 TXPowercount; 621 bool bTXPowerTrackingInit; 622 bool bTXPowerTracking; 623 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking 624 * as default */ 625 u8 TM_Trigger; 626 u8 InternalPA5G[2]; /* pathA / pathB */ 627 628 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, 629 * and 1 for RFIC1 */ 630 u8 ThermalValue; 631 u8 ThermalValue_LCK; 632 u8 ThermalValue_IQK; 633 u8 ThermalValue_DPK; 634 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 635 u8 ThermalValue_AVG_index; 636 u8 ThermalValue_RxGain; 637 u8 ThermalValue_Crystal; 638 u8 ThermalValue_DPKstore; 639 u8 ThermalValue_DPKtrack; 640 bool TxPowerTrackingInProgress; 641 bool bDPKenable; 642 643 bool bReloadtxpowerindex; 644 u8 bRfPiEnable; 645 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 646 647 u8 bCCKinCH14; 648 u8 CCK_index; 649 u8 OFDM_index[2]; 650 bool bDoneTxpower; 651 652 u8 ThermalValue_HP[HP_THERMAL_NUM]; 653 u8 ThermalValue_HP_index; 654 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 655 656 u8 Delta_IQK; 657 u8 Delta_LCK; 658 659 /* for IQK */ 660 u32 RegC04; 661 u32 Reg874; 662 u32 RegC08; 663 u32 RegB68; 664 u32 RegB6C; 665 u32 Reg870; 666 u32 Reg860; 667 u32 Reg864; 668 669 bool bIQKInitialized; 670 bool bLCKInProgress; 671 bool bAntennaDetected; 672 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 673 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 674 u32 IQK_BB_backup_recover[9]; 675 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 676 677 /* for APK */ 678 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 679 u8 bAPKdone; 680 u8 bAPKThermalMeterIgnore; 681 u8 bDPdone; 682 u8 bDPPathAOK; 683 u8 bDPPathBOK; 684}; 685 686/* ODM Dynamic common info value definition */ 687 688struct fast_ant_train { 689 u8 Bssid[6]; 690 u8 antsel_rx_keep_0; 691 u8 antsel_rx_keep_1; 692 u8 antsel_rx_keep_2; 693 u32 antSumRSSI[7]; 694 u32 antRSSIcnt[7]; 695 u32 antAveRSSI[7]; 696 u8 FAT_State; 697 u32 TrainIdx; 698 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 699 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 700 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 701 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 702 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 703 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 704 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 705 u8 RxIdleAnt; 706 bool bBecomeLinked; 707}; 708 709enum fat_state { 710 FAT_NORMAL_STATE = 0, 711 FAT_TRAINING_STATE = 1, 712}; 713 714enum ant_div_type { 715 NO_ANTDIV = 0xFF, 716 CG_TRX_HW_ANTDIV = 0x01, 717 CGCS_RX_HW_ANTDIV = 0x02, 718 FIXED_HW_ANTDIV = 0x03, 719 CG_TRX_SMART_ANTDIV = 0x04, 720 CGCS_RX_SW_ANTDIV = 0x05, 721}; 722 723/* Copy from SD4 defined structure. We use to support PHY DM integration. */ 724struct odm_dm_struct { 725 /* Add for different team use temporarily */ 726 struct adapter *Adapter; /* For CE/NIC team */ 727 struct rtl8192cd_priv *priv; /* For AP/ADSL team */ 728 /* WHen you use above pointers, they must be initialized. */ 729 bool odm_ready; 730 731 struct rtl8192cd_priv *fake_priv; 732 u64 DebugComponents; 733 u32 DebugLevel; 734 735/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 736 bool bCckHighPower; 737 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 738 u8 ControlChannel; 739/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 740 741/* 1 COMMON INFORMATION */ 742 /* Init Value */ 743/* HOOK BEFORE REG INIT----------- */ 744 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 745 u8 SupportPlatform; 746 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 747 u32 SupportAbility; 748 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ 749 u8 SupportInterface; 750 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any 751 * other type = 1/2/3/... */ 752 u32 SupportICType; 753 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 754 u8 CutVersion; 755 /* Fab Version TSMC/UMC = 0/1 */ 756 u8 FabVersion; 757 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 758 u8 RFType; 759 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */ 760 u8 BoardType; 761 /* with external LNA NO/Yes = 0/1 */ 762 u8 ExtLNA; 763 /* with external PA NO/Yes = 0/1 */ 764 u8 ExtPA; 765 /* with external TRSW NO/Yes = 0/1 */ 766 u8 ExtTRSW; 767 u8 PatchID; /* Customer ID */ 768 bool bInHctTest; 769 bool bWIFITest; 770 771 bool bDualMacSmartConcurrent; 772 u32 BK_SupportAbility; 773 u8 AntDivType; 774/* HOOK BEFORE REG INIT----------- */ 775 776 /* Dynamic Value */ 777/* POINTER REFERENCE----------- */ 778 779 u8 u8_temp; 780 bool bool_temp; 781 struct adapter *adapter_temp; 782 783 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 784 u8 *pMacPhyMode; 785 /* TX Unicast byte count */ 786 u64 *pNumTxBytesUnicast; 787 /* RX Unicast byte count */ 788 u64 *pNumRxBytesUnicast; 789 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 790 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ 791 /* Frequence band 2.4G/5G = 0/1 */ 792 u8 *pBandType; 793 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 794 u8 *pSecChOffset; 795 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 796 u8 *pSecurity; 797 /* BW info 20M/40M/80M = 0/1/2 */ 798 u8 *pBandWidth; 799 /* Central channel location Ch1/Ch2/.... */ 800 u8 *pChannel; /* central channel number */ 801 /* Common info for 92D DMSP */ 802 803 bool *pbGetValueFromOtherMac; 804 struct adapter **pBuddyAdapter; 805 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 806 /* Common info for Status */ 807 bool *pbScanInProcess; 808 bool *pbPowerSaving; 809 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 810 u8 *pOnePathCCA; 811 /* pMgntInfo->AntennaTest */ 812 u8 *pAntennaTest; 813 bool *pbNet_closed; 814/* POINTER REFERENCE----------- */ 815 /* */ 816/* CALL BY VALUE------------- */ 817 bool bWIFI_Direct; 818 bool bWIFI_Display; 819 bool bLinked; 820 u8 RSSI_Min; 821 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 822 bool bIsMPChip; 823 bool bOneEntryOnly; 824 /* Common info for BTDM */ 825 bool bBtDisabled; /* BT is disabled */ 826 bool bBtHsOperation; /* BT HS mode is under progress */ 827 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 828 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the 829 * EDCA Turbo */ 830 bool bBtBusy; /* BT is busy. */ 831/* CALL BY VALUE------------- */ 832 833 /* 2 Define STA info. */ 834 /* _ODM_STA_INFO */ 835 /* For MP, we need to reduce one array pointer for default port.?? */ 836 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 837 838 u16 CurrminRptTime; 839 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as 840 * array index. STA MacID=0, 841 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ 842 /* */ 843 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 844 /* We need to colelct all support abilit to a proper area. */ 845 /* */ 846 bool RaSupport88E; 847 848 /* Define ........... */ 849 850 /* Latest packet phy info (ODM write) */ 851 struct odm_phy_dbg_info PhyDbgInfo; 852 853 /* Latest packet phy info (ODM write) */ 854 struct odm_mac_status_info *pMacInfo; 855 856 /* Different Team independt structure?? */ 857 858 /* ODM Structure */ 859 struct fast_ant_train DM_FatTable; 860 struct rtw_dig DM_DigTable; 861 struct rtl_ps DM_PSTable; 862 struct rx_hpc DM_RXHP_Table; 863 struct false_alarm_stats FalseAlmCnt; 864 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 865 struct sw_ant_switch DM_SWAT_Table; 866 bool RSSI_test; 867 868 struct edca_turbo DM_EDCA_Table; 869 u32 WMMEDCA_BE; 870 /* Copy from SD4 structure */ 871 /* */ 872 /* ================================================== */ 873 /* */ 874 875 bool *pbDriverStopped; 876 bool *pbDriverIsGoingToPnpSetPowerSleep; 877 bool *pinit_adpt_in_progress; 878 879 /* PSD */ 880 bool bUserAssignLevel; 881 struct timer_list PSDTimer; 882 u8 RSSI_BT; /* come from BT */ 883 bool bPSDinProcess; 884 bool bDMInitialGainEnable; 885 886 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 887 u8 bUseRAMask; 888 889 struct odm_rate_adapt RateAdaptive; 890 891 struct odm_rf_cal RFCalibrateInfo; 892 893 /* TX power tracking */ 894 u8 BbSwingIdxOfdm; 895 u8 BbSwingIdxOfdmCurrent; 896 u8 BbSwingIdxOfdmBase; 897 bool BbSwingFlagOfdm; 898 u8 BbSwingIdxCck; 899 u8 BbSwingIdxCckCurrent; 900 u8 BbSwingIdxCckBase; 901 bool BbSwingFlagCck; 902 u8 *mp_mode; 903 /* ODM system resource. */ 904 905 /* ODM relative time. */ 906 struct timer_list PathDivSwitchTimer; 907 /* 2011.09.27 add for Path Diversity */ 908 struct timer_list CCKPathDiversityTimer; 909 struct timer_list FastAntTrainingTimer; 910}; /* DM_Dynamic_Mechanism_Structure */ 911 912#define ODM_RF_PATH_MAX 3 913 914enum ODM_RF_CONTENT { 915 odm_radioa_txt = 0x1000, 916 odm_radiob_txt = 0x1001, 917 odm_radioc_txt = 0x1002, 918 odm_radiod_txt = 0x1003 919}; 920 921enum odm_bb_config_type { 922 CONFIG_BB_PHY_REG, 923 CONFIG_BB_AGC_TAB, 924 CONFIG_BB_AGC_TAB_2G, 925 CONFIG_BB_AGC_TAB_5G, 926 CONFIG_BB_PHY_REG_PG, 927}; 928 929/* Status code */ 930enum rt_status { 931 RT_STATUS_SUCCESS, 932 RT_STATUS_FAILURE, 933 RT_STATUS_PENDING, 934 RT_STATUS_RESOURCE, 935 RT_STATUS_INVALID_CONTEXT, 936 RT_STATUS_INVALID_PARAMETER, 937 RT_STATUS_NOT_SUPPORT, 938 RT_STATUS_OS_API_FAILED, 939}; 940 941/* 3=========================================================== */ 942/* 3 DIG */ 943/* 3=========================================================== */ 944 945enum dm_dig_op { 946 RT_TYPE_THRESH_HIGH = 0, 947 RT_TYPE_THRESH_LOW = 1, 948 RT_TYPE_BACKOFF = 2, 949 RT_TYPE_RX_GAIN_MIN = 3, 950 RT_TYPE_RX_GAIN_MAX = 4, 951 RT_TYPE_ENABLE = 5, 952 RT_TYPE_DISABLE = 6, 953 DIG_OP_TYPE_MAX 954}; 955 956#define DM_DIG_THRESH_HIGH 40 957#define DM_DIG_THRESH_LOW 35 958 959#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ 960 961 962#define DM_false_ALARM_THRESH_LOW 400 963#define DM_false_ALARM_THRESH_HIGH 1000 964 965#define DM_DIG_MAX_NIC 0x4e 966#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ 967 968#define DM_DIG_MAX_AP 0x32 969#define DM_DIG_MIN_AP 0x20 970 971#define DM_DIG_MAX_NIC_HP 0x46 972#define DM_DIG_MIN_NIC_HP 0x2e 973 974#define DM_DIG_MAX_AP_HP 0x42 975#define DM_DIG_MIN_AP_HP 0x30 976 977/* vivi 92c&92d has different definition, 20110504 */ 978/* this is for 92c */ 979#define DM_DIG_FA_TH0 0x200/* 0x20 */ 980#define DM_DIG_FA_TH1 0x300/* 0x100 */ 981#define DM_DIG_FA_TH2 0x400/* 0x200 */ 982/* this is for 92d */ 983#define DM_DIG_FA_TH0_92D 0x100 984#define DM_DIG_FA_TH1_92D 0x400 985#define DM_DIG_FA_TH2_92D 0x600 986 987#define DM_DIG_BACKOFF_MAX 12 988#define DM_DIG_BACKOFF_MIN -4 989#define DM_DIG_BACKOFF_DEFAULT 10 990 991/* 3=========================================================== */ 992/* 3 AGC RX High Power Mode */ 993/* 3=========================================================== */ 994#define LNA_Low_Gain_1 0x64 995#define LNA_Low_Gain_2 0x5A 996#define LNA_Low_Gain_3 0x58 997 998#define FA_RXHP_TH1 5000 999#define FA_RXHP_TH2 1500 1000#define FA_RXHP_TH3 800 1001#define FA_RXHP_TH4 600 1002#define FA_RXHP_TH5 500 1003 1004/* 3=========================================================== */ 1005/* 3 EDCA */ 1006/* 3=========================================================== */ 1007 1008/* 3=========================================================== */ 1009/* 3 Dynamic Tx Power */ 1010/* 3=========================================================== */ 1011/* Dynamic Tx Power Control Threshold */ 1012#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 1013#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 1014#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 1015 1016#define TxHighPwrLevel_Normal 0 1017#define TxHighPwrLevel_Level1 1 1018#define TxHighPwrLevel_Level2 2 1019#define TxHighPwrLevel_BT1 3 1020#define TxHighPwrLevel_BT2 4 1021#define TxHighPwrLevel_15 5 1022#define TxHighPwrLevel_35 6 1023#define TxHighPwrLevel_50 7 1024#define TxHighPwrLevel_70 8 1025#define TxHighPwrLevel_100 9 1026 1027/* 3=========================================================== */ 1028/* 3 Rate Adaptive */ 1029/* 3=========================================================== */ 1030#define DM_RATR_STA_INIT 0 1031#define DM_RATR_STA_HIGH 1 1032#define DM_RATR_STA_MIDDLE 2 1033#define DM_RATR_STA_LOW 3 1034 1035/* 3=========================================================== */ 1036/* 3 BB Power Save */ 1037/* 3=========================================================== */ 1038 1039 1040enum dm_1r_cca { 1041 CCA_1R = 0, 1042 CCA_2R = 1, 1043 CCA_MAX = 2, 1044}; 1045 1046enum dm_rf { 1047 RF_Save = 0, 1048 RF_Normal = 1, 1049 RF_MAX = 2, 1050}; 1051 1052/* 3=========================================================== */ 1053/* 3 Antenna Diversity */ 1054/* 3=========================================================== */ 1055enum dm_swas { 1056 Antenna_A = 1, 1057 Antenna_B = 2, 1058 Antenna_MAX = 3, 1059}; 1060 1061/* Maximal number of antenna detection mechanism needs to perform. */ 1062#define MAX_ANTENNA_DETECTION_CNT 10 1063 1064/* Extern Global Variables. */ 1065#define OFDM_TABLE_SIZE_92C 37 1066#define OFDM_TABLE_SIZE_92D 43 1067#define CCK_TABLE_SIZE 33 1068 1069extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D]; 1070extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1071extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; 1072 1073/* check Sta pointer valid or not */ 1074#define IS_STA_VALID(pSta) (pSta) 1075/* 20100514 Joseph: Add definition for antenna switching test after link. */ 1076/* This indicates two different the steps. */ 1077/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the 1078 * signal on the air. */ 1079/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in 1080 * SWAW_STEP_PEAK */ 1081/* with original RSSI to determine if it is necessary to switch antenna. */ 1082#define SWAW_STEP_PEAK 0 1083#define SWAW_STEP_DETERMINE 1 1084 1085#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1086#define dm_RF_Saving ODM_RF_Saving 1087 1088void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); 1089void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); 1090void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm); 1091void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); 1092bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, 1093 bool bForceUpdate, u8 *pRATRState); 1094u32 ConvertTo_dB(u32 Value); 1095u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, 1096 u32 ra_mask, u8 rssi_level); 1097void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, 1098 enum odm_common_info_def CmnInfo, u32 Value); 1099void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value); 1100void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, 1101 enum odm_common_info_def CmnInfo, void *pValue); 1102void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, 1103 enum odm_common_info_def CmnInfo, 1104 u16 Index, void *pValue); 1105void ODM_DMInit(struct odm_dm_struct *pDM_Odm); 1106void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm); 1107void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); 1108 1109#endif 1110