1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17#ifndef __HALDMOUTSRC_H__ 18#define __HALDMOUTSRC_H__ 19 20/* */ 21/* Definition */ 22/* */ 23/* */ 24/* 2011/09/22 MH Define all team supprt ability. */ 25/* */ 26 27/* */ 28/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ 29/* */ 30/* define DM_ODM_SUPPORT_AP 0 */ 31/* define DM_ODM_SUPPORT_ADSL 0 */ 32/* define DM_ODM_SUPPORT_CE 0 */ 33/* define DM_ODM_SUPPORT_MP 1 */ 34 35#define TP_MODE 0 36#define RSSI_MODE 1 37#define TRAFFIC_LOW 0 38#define TRAFFIC_HIGH 1 39 40 41/* */ 42/* 3 Tx Power Tracking */ 43/* 3============================================================ */ 44#define DPK_DELTA_MAPPING_NUM 13 45#define index_mapping_HP_NUM 15 46 47 48/* */ 49/* 3 PSD Handler */ 50/* 3============================================================ */ 51 52#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 53#define MODE_40M 0 /* 0:20M, 1:40M */ 54#define PSD_TH2 3 55#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 56#define SIR_STEP_SIZE 3 57#define Smooth_Size_1 5 58#define Smooth_TH_1 3 59#define Smooth_Size_2 10 60#define Smooth_TH_2 4 61#define Smooth_Size_3 20 62#define Smooth_TH_3 4 63#define Smooth_Step_Size 5 64#define Adaptive_SIR 1 65#define PSD_RESCAN 4 66#define PSD_SCAN_INTERVAL 700 /* ms */ 67 68/* 8723A High Power IGI Setting */ 69#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 70#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 71#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 72 73/* LPS define */ 74#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ 75#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ 76#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ 77#define RSSI_OFFSET_DIG 0x05; 78 79/* ANT Test */ 80#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 81#define ANTTESTA 0x01 /* Ant A will be Testing */ 82#define ANTTESTB 0x02 /* Ant B will be testing */ 83 84 85/* */ 86/* structure and define */ 87/* */ 88 89struct dig_t { 90 u8 Dig_Enable_Flag; 91 u8 Dig_Ext_Port_Stage; 92 93 int RssiLowThresh; 94 int RssiHighThresh; 95 96 u32 FALowThresh; 97 u32 FAHighThresh; 98 99 u8 CurSTAConnectState; 100 u8 PreSTAConnectState; 101 u8 CurMultiSTAConnectState; 102 103 u8 PreIGValue; 104 u8 CurIGValue; 105 u8 BackupIGValue; 106 107 s8 BackoffVal; 108 s8 BackoffVal_range_max; 109 s8 BackoffVal_range_min; 110 u8 rx_gain_range_max; 111 u8 rx_gain_range_min; 112 u8 Rssi_val_min; 113 114 u8 PreCCK_CCAThres; 115 u8 CurCCK_CCAThres; 116 u8 PreCCKPDState; 117 u8 CurCCKPDState; 118 119 u8 LargeFAHit; 120 u8 ForbiddenIGI; 121 u32 Recover_cnt; 122 123 u8 DIG_Dynamic_MIN_0; 124 u8 DIG_Dynamic_MIN_1; 125 bool bMediaConnect_0; 126 bool bMediaConnect_1; 127 128 u32 RSSI_max; 129}; 130 131struct dynamic_pwr_sav { 132 u8 PreCCAState; 133 u8 CurCCAState; 134 135 u8 PreRFState; 136 u8 CurRFState; 137 138 int Rssi_val_min; 139 140 u8 initialize; 141 u32 Reg874, RegC70, Reg85C, RegA74; 142}; 143 144struct false_alarm_stats { 145 u32 Cnt_Parity_Fail; 146 u32 Cnt_Rate_Illegal; 147 u32 Cnt_Crc8_fail; 148 u32 Cnt_Mcs_fail; 149 u32 Cnt_Ofdm_fail; 150 u32 Cnt_Cck_fail; 151 u32 Cnt_all; 152 u32 Cnt_Fast_Fsync; 153 u32 Cnt_SB_Search_fail; 154 u32 Cnt_OFDM_CCA; 155 u32 Cnt_CCK_CCA; 156 u32 Cnt_CCA_all; 157 u32 Cnt_BW_USC; /* Gary */ 158 u32 Cnt_BW_LSC; /* Gary */ 159}; 160 161struct pri_cca { 162 u8 PriCCA_flag; 163 u8 intf_flag; 164 u8 intf_type; 165 u8 DupRTS_flag; 166 u8 Monitor_flag; 167}; 168 169struct rx_hp { 170 u8 RXHP_flag; 171 u8 PSD_func_trigger; 172 u8 PSD_bitmap_RXHP[80]; 173 u8 Pre_IGI; 174 u8 Cur_IGI; 175 u8 Pre_pw_th; 176 u8 Cur_pw_th; 177 bool First_time_enter; 178 bool RXHP_enable; 179 u8 TP_Mode; 180}; 181 182#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 183#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 184 185/* This indicates two different the steps. */ 186/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 187/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 188/* with original RSSI to determine if it is necessary to switch antenna. */ 189#define SWAW_STEP_PEAK 0 190#define SWAW_STEP_DETERMINE 1 191 192#define TP_MODE 0 193#define RSSI_MODE 1 194#define TRAFFIC_LOW 0 195#define TRAFFIC_HIGH 1 196 197struct sw_ant_sw { 198 u8 try_flag; 199 s32 PreRSSI; 200 u8 CurAntenna; 201 u8 PreAntenna; 202 u8 RSSI_Trying; 203 u8 TestMode; 204 u8 bTriggerAntennaSwitch; 205 u8 SelectAntennaMap; 206 u8 RSSI_target; 207 208 /* Before link Antenna Switch check */ 209 u8 SWAS_NoLink_State; 210 u32 SWAS_NoLink_BK_Reg860; 211 bool ANTA_ON; /* To indicate Ant A is or not */ 212 bool ANTB_ON; /* To indicate Ant B is on or not */ 213 214 s32 RSSI_sum_A; 215 s32 RSSI_sum_B; 216 s32 RSSI_cnt_A; 217 s32 RSSI_cnt_B; 218 219 u64 lastTxOkCnt; 220 u64 lastRxOkCnt; 221 u64 TXByteCnt_A; 222 u64 TXByteCnt_B; 223 u64 RXByteCnt_A; 224 u64 RXByteCnt_B; 225 u8 TrafficLoad; 226}; 227 228struct edca_turbo { 229 bool bCurrentTurboEDCA; 230 bool bIsCurRDLState; 231 u32 prv_traffic_idx; /* edca turbo */ 232}; 233 234struct odm_rate_adapt { 235 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 236 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 237 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 238 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 239 u32 LastRATR; /* RATR Register Content */ 240}; 241 242#define IQK_MAC_REG_NUM 4 243#define IQK_ADDA_REG_NUM 16 244#define IQK_BB_REG_NUM_MAX 10 245#define IQK_BB_REG_NUM 9 246#define HP_THERMAL_NUM 8 247 248#define AVG_THERMAL_NUM 8 249#define IQK_Matrix_REG_NUM 8 250#define IQK_Matrix_Settings_NUM 1+24+21 251 252#define DM_Type_ByFW 0 253#define DM_Type_ByDriver 1 254 255/* Declare for common info */ 256 257struct odm_phy_dbg_info { 258 /* ODM Write,debug info */ 259 s8 RxSNRdB[RF_PATH_MAX]; 260 u64 NumQryPhyStatus; 261 u64 NumQryPhyStatusCCK; 262 u64 NumQryPhyStatusOFDM; 263 /* Others */ 264 s32 RxEVM[RF_PATH_MAX]; 265 266}; 267 268struct odm_packet_info { 269 u8 Rate; 270 u8 StationID; 271 bool bPacketMatchBSSID; 272 bool bPacketToSelf; 273 bool bPacketBeacon; 274}; 275 276 277enum { 278 /* BB Team */ 279 ODM_DIG = 0x00000001, 280 ODM_HIGH_POWER = 0x00000002, 281 ODM_CCK_CCA_TH = 0x00000004, 282 ODM_FA_STATISTICS = 0x00000008, 283 ODM_RAMASK = 0x00000010, 284 ODM_RSSI_MONITOR = 0x00000020, 285 ODM_SW_ANTDIV = 0x00000040, 286 ODM_HW_ANTDIV = 0x00000080, 287 ODM_BB_PWRSV = 0x00000100, 288 ODM_2TPATHDIV = 0x00000200, 289 ODM_1TPATHDIV = 0x00000400, 290 ODM_PSD2AFH = 0x00000800 291}; 292 293/* */ 294/* 2011/10/20 MH Define Common info enum for all team. */ 295/* */ 296 297enum odm_cmninfo { 298 /* Fixed value: */ 299 /* */ 300 301 ODM_CMNINFO_PLATFORM = 0, 302 ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */ 303 ODM_CMNINFO_MP_TEST_CHIP, 304 ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */ 305 ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */ 306 ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */ 307 ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */ 308 ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */ 309 ODM_CMNINFO_EXT_LNA, /* true */ 310 ODM_CMNINFO_EXT_PA, 311 ODM_CMNINFO_EXT_TRSW, 312 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 313 ODM_CMNINFO_BINHCT_TEST, 314 ODM_CMNINFO_BWIFI_TEST, 315 ODM_CMNINFO_SMART_CONCURRENT, 316 317 318 /* */ 319 /* Dynamic value: */ 320 /* */ 321 ODM_CMNINFO_MP_MODE, 322 323 ODM_CMNINFO_WIFI_DIRECT, 324 ODM_CMNINFO_WIFI_DISPLAY, 325 ODM_CMNINFO_LINK, 326 ODM_CMNINFO_RSSI_MIN, 327 ODM_CMNINFO_DBG_COMP, /* u64 */ 328 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 329 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 330 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 331 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 332 ODM_CMNINFO_BT_DISABLED, 333 ODM_CMNINFO_BT_OPERATION, 334 ODM_CMNINFO_BT_DIG, 335 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ 336 ODM_CMNINFO_BT_DISABLE_EDCA, 337 338 /* */ 339 /* Dynamic ptr array hook itms. */ 340 /* */ 341 ODM_CMNINFO_STA_STATUS, 342 ODM_CMNINFO_PHY_STATUS, 343 ODM_CMNINFO_MAC_STATUS, 344 345 ODM_CMNINFO_MAX, 346}; 347 348/* Define ODM support ability. ODM_CMNINFO_ABILITY */ 349enum { 350 /* BB ODM section BIT 0-15 */ 351 ODM_BB_DIG = BIT(0), 352 ODM_BB_RA_MASK = BIT(1), 353 ODM_BB_DYNAMIC_TXPWR = BIT(2), 354 ODM_BB_FA_CNT = BIT(3), 355 ODM_BB_RSSI_MONITOR = BIT(4), 356 ODM_BB_CCK_PD = BIT(5), 357 ODM_BB_ANT_DIV = BIT(6), 358 ODM_BB_PWR_SAVE = BIT(7), 359 ODM_BB_PWR_TRAIN = BIT(8), 360 ODM_BB_RATE_ADAPTIVE = BIT(9), 361 ODM_BB_PATH_DIV = BIT(10), 362 ODM_BB_PSD = BIT(11), 363 ODM_BB_RXHP = BIT(12), 364 365 /* MAC DM section BIT 16-23 */ 366 ODM_MAC_EDCA_TURBO = BIT(16), 367 ODM_MAC_EARLY_MODE = BIT(17), 368 369 /* RF ODM section BIT 24-31 */ 370 ODM_RF_TX_PWR_TRACK = BIT(24), 371 ODM_RF_RX_GAIN_TRACK = BIT(25), 372 ODM_RF_CALIBRATION = BIT(26), 373 374}; 375 376/* ODM_CMNINFO_INTERFACE */ 377enum odm_interface_def { 378 ODM_ITRF_PCIE = 0x1, 379 ODM_ITRF_USB = 0x2, 380 ODM_ITRF_SDIO = 0x4, 381 ODM_ITRF_ALL = 0x7, 382}; 383 384/* ODM_CMNINFO_IC_TYPE */ 385enum odm_ic_type_def { 386 ODM_RTL8192S = BIT(0), 387 ODM_RTL8192C = BIT(1), 388 ODM_RTL8192D = BIT(2), 389 ODM_RTL8723A = BIT(3), 390 ODM_RTL8188E = BIT(4), 391 ODM_RTL8812 = BIT(5), 392 ODM_RTL8821 = BIT(6), 393}; 394 395/* ODM_CMNINFO_CUT_VER */ 396enum odm_cut_version { 397 ODM_CUT_A = 1, 398 ODM_CUT_B = 2, 399 ODM_CUT_C = 3, 400 ODM_CUT_D = 4, 401 ODM_CUT_E = 5, 402 ODM_CUT_F = 6, 403 ODM_CUT_TEST = 7, 404}; 405 406/* ODM_CMNINFO_FAB_VER */ 407enum odm_fab_version { 408 ODM_TSMC = 0, 409 ODM_UMC = 1, 410}; 411 412/* ODM_CMNINFO_RF_TYPE */ 413/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 414enum rf_path_def { 415 ODM_RF_TX_A = BIT(0), 416 ODM_RF_TX_B = BIT(1), 417 ODM_RF_TX_C = BIT(2), 418 ODM_RF_TX_D = BIT(3), 419 ODM_RF_RX_A = BIT(4), 420 ODM_RF_RX_B = BIT(5), 421 ODM_RF_RX_C = BIT(6), 422 ODM_RF_RX_D = BIT(7), 423}; 424 425 426enum odm_rf_type { 427 ODM_1T1R = 0, 428 ODM_1T2R = 1, 429 ODM_2T2R = 2, 430 ODM_2T3R = 3, 431 ODM_2T4R = 4, 432 ODM_3T3R = 5, 433 ODM_3T4R = 6, 434 ODM_4T4R = 7, 435}; 436 437/* ODM Dynamic common info value definition */ 438 439enum odm_mac_phy_mode { 440 ODM_SMSP = 0, 441 ODM_DMSP = 1, 442 ODM_DMDP = 2, 443}; 444 445 446enum odm_bt_coexist { 447 ODM_BT_BUSY = 1, 448 ODM_BT_ON = 2, 449 ODM_BT_OFF = 3, 450 ODM_BT_NONE = 4, 451}; 452 453/* ODM_CMNINFO_OP_MODE */ 454enum odm_operation_mode { 455 ODM_NO_LINK = BIT(0), 456 ODM_LINK = BIT(1), 457 ODM_SCAN = BIT(2), 458 ODM_POWERSAVE = BIT(3), 459 ODM_AP_MODE = BIT(4), 460 ODM_CLIENT_MODE = BIT(5), 461 ODM_AD_HOC = BIT(6), 462 ODM_WIFI_DIRECT = BIT(7), 463 ODM_WIFI_DISPLAY = BIT(8), 464}; 465 466/* ODM_CMNINFO_WM_MODE */ 467enum odm_wireless_mode { 468 ODM_WM_UNKNOW = 0x0, 469 ODM_WM_B = BIT(0), 470 ODM_WM_G = BIT(1), 471 ODM_WM_A = BIT(2), 472 ODM_WM_N24G = BIT(3), 473 ODM_WM_N5G = BIT(4), 474 ODM_WM_AUTO = BIT(5), 475 ODM_WM_AC = BIT(6), 476}; 477 478/* ODM_CMNINFO_BAND */ 479enum odm_band_type { 480 ODM_BAND_2_4G = BIT(0), 481 ODM_BAND_5G = BIT(1), 482 483}; 484 485/* ODM_CMNINFO_SEC_CHNL_OFFSET */ 486enum odm_sec_chnl_offset { 487 ODM_DONT_CARE = 0, 488 ODM_BELOW = 1, 489 ODM_ABOVE = 2 490}; 491 492/* ODM_CMNINFO_CHNL */ 493 494/* ODM_CMNINFO_BOARD_TYPE */ 495enum odm_board_type { 496 ODM_BOARD_NORMAL = 0, 497 ODM_BOARD_HIGHPWR = 1, 498 ODM_BOARD_MINICARD = 2, 499 ODM_BOARD_SLIM = 3, 500 ODM_BOARD_COMBO = 4, 501 502}; 503 504/* ODM_CMNINFO_ONE_PATH_CCA */ 505enum odm_cca_path { 506 ODM_CCA_2R = 0, 507 ODM_CCA_1R_A = 1, 508 ODM_CCA_1R_B = 2, 509}; 510 511struct iqk_matrix_regs_set { 512 bool bIQKDone; 513 s32 Value[1][IQK_Matrix_REG_NUM]; 514}; 515 516struct odm_rf_cal_t { 517 /* for tx power tracking */ 518 519 u32 RegA24; /* for TempCCK */ 520 s32 RegE94; 521 s32 RegE9C; 522 s32 RegEB4; 523 s32 RegEBC; 524 525 /* u8 bTXPowerTracking; */ 526 u8 TXPowercount; 527 bool bTXPowerTrackingInit; 528 bool bTXPowerTracking; 529 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 530 u8 TM_Trigger; 531 u8 InternalPA5G[2]; /* pathA / pathB */ 532 533 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 534 u8 ThermalValue; 535 u8 ThermalValue_LCK; 536 u8 ThermalValue_IQK; 537 u8 ThermalValue_DPK; 538 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 539 u8 ThermalValue_AVG_index; 540 u8 ThermalValue_RxGain; 541 u8 ThermalValue_Crystal; 542 u8 ThermalValue_DPKstore; 543 u8 ThermalValue_DPKtrack; 544 bool TxPowerTrackingInProgress; 545 bool bDPKenable; 546 547 bool bReloadtxpowerindex; 548 u8 bRfPiEnable; 549 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 550 551 u8 bCCKinCH14; 552 u8 CCK_index; 553 u8 OFDM_index[2]; 554 bool bDoneTxpower; 555 556 u8 ThermalValue_HP[HP_THERMAL_NUM]; 557 u8 ThermalValue_HP_index; 558 struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 559 560 u8 Delta_IQK; 561 u8 Delta_LCK; 562 563 /* for IQK */ 564 u32 RegC04; 565 u32 Reg874; 566 u32 RegC08; 567 u32 RegB68; 568 u32 RegB6C; 569 u32 Reg870; 570 u32 Reg860; 571 u32 Reg864; 572 573 bool bIQKInitialized; 574 bool bLCKInProgress; 575 bool bAntennaDetected; 576 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 577 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 578 u32 IQK_BB_backup_recover[9]; 579 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 580 581 /* for APK */ 582 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 583 u8 bAPKdone; 584 u8 bAPKThermalMeterIgnore; 585 u8 bDPdone; 586 u8 bDPPathAOK; 587 u8 bDPPathBOK; 588}; 589 590/* ODM Dynamic common info value definition */ 591struct odm_fat_t { 592 u8 Bssid[6]; 593 u8 antsel_rx_keep_0; 594 u8 antsel_rx_keep_1; 595 u8 antsel_rx_keep_2; 596 u32 antSumRSSI[7]; 597 u32 antRSSIcnt[7]; 598 u32 antAveRSSI[7]; 599 u8 FAT_State; 600 u32 TrainIdx; 601 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 602 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 603 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 604 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 605 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 606 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 607 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 608 u8 RxIdleAnt; 609 bool bBecomeLinked; 610}; 611 612enum fat_state { 613 FAT_NORMAL_STATE = 0, 614 FAT_TRAINING_STATE = 1, 615}; 616 617enum ant_dif_type { 618 NO_ANTDIV = 0xFF, 619 CG_TRX_HW_ANTDIV = 0x01, 620 CGCS_RX_HW_ANTDIV = 0x02, 621 FIXED_HW_ANTDIV = 0x03, 622 CG_TRX_SMART_ANTDIV = 0x04, 623 CGCS_RX_SW_ANTDIV = 0x05, 624}; 625 626/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 627struct dm_odm_t { 628 /* */ 629 /* Add for different team use temporarily */ 630 /* */ 631 struct rtw_adapter *Adapter; /* For CE/NIC team */ 632 633 u64 DebugComponents; 634 u32 DebugLevel; 635 636/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 637 bool bCckHighPower; 638 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 639 u8 ControlChannel; 640/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 641 642/* 1 COMMON INFORMATION */ 643 644 /* Init Value */ 645/* HOOK BEFORE REG INIT----------- */ 646 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 647 u32 SupportAbility; 648 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ 649 u8 SupportInterface; 650 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 651 u32 SupportICType; 652 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 653 u8 CutVersion; 654 /* Fab Version TSMC/UMC = 0/1 */ 655 u8 FabVersion; 656 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 657 u8 RFType; 658 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 659 u8 BoardType; 660 /* with external LNA NO/Yes = 0/1 */ 661 u8 ExtLNA; 662 /* with external PA NO/Yes = 0/1 */ 663 u8 ExtPA; 664 /* with external TRSW NO/Yes = 0/1 */ 665 u8 ExtTRSW; 666 u8 PatchID; /* Customer ID */ 667 bool bInHctTest; 668 bool bWIFITest; 669 670 bool bDualMacSmartConcurrent; 671 u32 BK_SupportAbility; 672/* HOOK BEFORE REG INIT----------- */ 673 674 /* */ 675 /* Dynamic Value */ 676 /* */ 677/* POINTER REFERENCE----------- */ 678 679 u8 u8_temp; 680 bool bool_temp; 681 struct rtw_adapter *PADAPTER_temp; 682 683/* POINTER REFERENCE----------- */ 684 /* */ 685/* CALL BY VALUE------------- */ 686 bool bWIFI_Direct; 687 bool bWIFI_Display; 688 bool bLinked; 689 u8 RSSI_Min; 690 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 691 bool bIsMPChip; 692 bool bOneEntryOnly; 693 /* Common info for BTDM */ 694 bool bBtDisabled; /* BT is disabled */ 695 bool bBtHsOperation; /* BT HS mode is under progress */ 696 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 697 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 698 bool bBtBusy; /* BT is busy. */ 699/* CALL BY VALUE------------- */ 700 701 /* 2 Define STA info. */ 702 /* _ODM_STA_INFO */ 703 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 704 struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 705 706 /* */ 707 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 708 /* We need to colelct all support abilit to a proper area. */ 709 /* */ 710 bool RaSupport88E; 711 712 /* Define ........... */ 713 714 /* Latest packet phy info (ODM write) */ 715 struct odm_phy_dbg_info PhyDbgInfo; 716 /* PHY_INFO_88E PhyInfo; */ 717 718 /* Latest packet phy info (ODM write) */ 719 /* MAC_INFO_88E MacInfo; */ 720 721 /* Different Team independt structure?? */ 722 723 /* */ 724 /* TX_RTP_CMN TX_retrpo; */ 725 /* TX_RTP_88E TX_retrpo; */ 726 /* TX_RTP_8195 TX_retrpo; */ 727 728 /* */ 729 /* ODM Structure */ 730 /* */ 731 struct odm_fat_t DM_FatTable; 732 struct dig_t DM_DigTable; 733 struct dynamic_pwr_sav DM_PSTable; 734 struct pri_cca DM_PriCCA; 735 struct rx_hp DM_RXHP_Table; 736 struct false_alarm_stats FalseAlmCnt; 737 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 738 struct sw_ant_sw DM_SWAT_Table; 739 740 struct edca_turbo DM_EDCA_Table; 741 u32 WMMEDCA_BE; 742 /* Copy from SD4 structure */ 743 /* */ 744 /* ================================================== */ 745 /* */ 746 747 /* PSD */ 748 bool bUserAssignLevel; 749 u8 RSSI_BT; /* come from BT */ 750 bool bPSDinProcess; 751 752 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 753 u8 bUseRAMask; 754 755 struct odm_rate_adapt RateAdaptive; 756 757 758 struct odm_rf_cal_t RFCalibrateInfo; 759 760 /* */ 761 /* TX power tracking */ 762 /* */ 763 u8 BbSwingIdxOfdm; 764 u8 BbSwingIdxOfdmCurrent; 765 u8 BbSwingIdxOfdmBase; 766 bool BbSwingFlagOfdm; 767 u8 BbSwingIdxCck; 768 u8 BbSwingIdxCckCurrent; 769 u8 BbSwingIdxCckBase; 770 bool BbSwingFlagCck; 771 /* */ 772 /* ODM system resource. */ 773 /* */ 774}; /* DM_Dynamic_Mechanism_Structure */ 775 776enum odm_rf_content { 777 odm_radioa_txt = 0x1000, 778 odm_radiob_txt = 0x1001, 779 odm_radioc_txt = 0x1002, 780 odm_radiod_txt = 0x1003 781}; 782 783/* Status code */ 784enum rt_status { 785 RT_STATUS_SUCCESS, 786 RT_STATUS_FAILURE, 787 RT_STATUS_PENDING, 788 RT_STATUS_RESOURCE, 789 RT_STATUS_INVALID_CONTEXT, 790 RT_STATUS_INVALID_PARAMETER, 791 RT_STATUS_NOT_SUPPORT, 792 RT_STATUS_OS_API_FAILED, 793}; 794 795/* include "odm_function.h" */ 796 797/* 3=========================================================== */ 798/* 3 DIG */ 799/* 3=========================================================== */ 800 801enum dm_dig_op { 802 DIG_TYPE_THRESH_HIGH = 0, 803 DIG_TYPE_THRESH_LOW = 1, 804 DIG_TYPE_BACKOFF = 2, 805 DIG_TYPE_RX_GAIN_MIN = 3, 806 DIG_TYPE_RX_GAIN_MAX = 4, 807 DIG_TYPE_ENABLE = 5, 808 DIG_TYPE_DISABLE = 6, 809 DIG_OP_TYPE_MAX 810}; 811 812#define DM_DIG_THRESH_HIGH 40 813#define DM_DIG_THRESH_LOW 35 814 815#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ 816 817 818#define DM_FALSEALARM_THRESH_LOW 400 819#define DM_FALSEALARM_THRESH_HIGH 1000 820 821#define DM_DIG_MAX_NIC 0x4e 822#define DM_DIG_MIN_NIC 0x1e 823 824#define DM_DIG_MAX_AP 0x32 825#define DM_DIG_MIN_AP 0x20 826 827#define DM_DIG_MAX_NIC_HP 0x46 828#define DM_DIG_MIN_NIC_HP 0x2e 829 830#define DM_DIG_MAX_AP_HP 0x42 831#define DM_DIG_MIN_AP_HP 0x30 832 833/* vivi 92c&92d has different definition, 20110504 */ 834/* this is for 92c */ 835#define DM_DIG_FA_TH0 0x200 836#define DM_DIG_FA_TH1 0x300 837#define DM_DIG_FA_TH2 0x400 838/* this is for 92d */ 839#define DM_DIG_FA_TH0_92D 0x100 840#define DM_DIG_FA_TH1_92D 0x400 841#define DM_DIG_FA_TH2_92D 0x600 842 843#define DM_DIG_BACKOFF_MAX 12 844#define DM_DIG_BACKOFF_MIN -4 845#define DM_DIG_BACKOFF_DEFAULT 10 846 847/* 3=========================================================== */ 848/* 3 AGC RX High Power Mode */ 849/* 3=========================================================== */ 850#define LNA_Low_Gain_1 0x64 851#define LNA_Low_Gain_2 0x5A 852#define LNA_Low_Gain_3 0x58 853 854#define FA_RXHP_TH1 5000 855#define FA_RXHP_TH2 1500 856#define FA_RXHP_TH3 800 857#define FA_RXHP_TH4 600 858#define FA_RXHP_TH5 500 859 860/* 3=========================================================== */ 861/* 3 EDCA */ 862/* 3=========================================================== */ 863 864/* 3=========================================================== */ 865/* 3 Dynamic Tx Power */ 866/* 3=========================================================== */ 867/* Dynamic Tx Power Control Threshold */ 868#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 869#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 870#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 871 872#define TxHighPwrLevel_Normal 0 873#define TxHighPwrLevel_Level1 1 874#define TxHighPwrLevel_Level2 2 875#define TxHighPwrLevel_BT1 3 876#define TxHighPwrLevel_BT2 4 877#define TxHighPwrLevel_15 5 878#define TxHighPwrLevel_35 6 879#define TxHighPwrLevel_50 7 880#define TxHighPwrLevel_70 8 881#define TxHighPwrLevel_100 9 882 883/* 3=========================================================== */ 884/* 3 Rate Adaptive */ 885/* 3=========================================================== */ 886#define DM_RATR_STA_INIT 0 887#define DM_RATR_STA_HIGH 1 888#define DM_RATR_STA_MIDDLE 2 889#define DM_RATR_STA_LOW 3 890 891/* 3=========================================================== */ 892/* 3 BB Power Save */ 893/* 3=========================================================== */ 894 895 896enum dm_1r_cca { 897 CCA_1R =0, 898 CCA_2R = 1, 899 CCA_MAX = 2, 900}; 901 902enum dm_rf_def { 903 RF_Save =0, 904 RF_Normal = 1, 905 RF_MAX = 2, 906}; 907 908/* 3=========================================================== */ 909/* 3 Antenna Diversity */ 910/* 3=========================================================== */ 911enum dm_swas { 912 Antenna_A = 1, 913 Antenna_B = 2, 914 Antenna_MAX = 3, 915}; 916 917/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 918#define MAX_ANTENNA_DETECTION_CNT 10 919 920/* */ 921/* Extern Global Variables. */ 922/* */ 923#define OFDM_TABLE_SIZE_92C 37 924#define OFDM_TABLE_SIZE_92D 43 925#define CCK_TABLE_SIZE 33 926 927extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D]; 928extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8]; 929extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8]; 930 931 932 933/* 20100514 Joseph: Add definition for antenna switching test after link. */ 934/* This indicates two different the steps. */ 935/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 936/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 937/* with original RSSI to determine if it is necessary to switch antenna. */ 938#define SWAW_STEP_PEAK 0 939#define SWAW_STEP_DETERMINE 1 940 941struct hal_data_8723a; 942 943void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI); 944void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres); 945 946void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna); 947 948 949#define dm_RF_Saving ODM_RF_Saving23a 950void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal); 951 952#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a 953void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm); 954 955bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate, 956 u8 *pRATRState); 957 958 959u32 ConvertTo_dB23a(u32 Value); 960 961u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd); 962 963void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm); 964 965u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid, u32 ra_mask, u8 rssi_level); 966 967 968void ODM23a_DMInit(struct dm_odm_t *pDM_Odm); 969 970void ODM_DMWatchdog23a(struct rtw_adapter *adapter); 971 972void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value); 973 974void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue); 975 976void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 977 978void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm); 979 980void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate); 981 982void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm); 983 984bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode); 985 986void odm_dtc(struct dm_odm_t *pDM_Odm); 987 988#endif 989