odm.h revision 3f22aed843c7f7984e61f64394dc6b00000e2d18
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17#ifndef __HALDMOUTSRC_H__ 18#define __HALDMOUTSRC_H__ 19 20/* */ 21/* Definition */ 22/* */ 23/* */ 24/* 2011/09/22 MH Define all team supprt ability. */ 25/* */ 26 27/* */ 28/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ 29/* */ 30/* define DM_ODM_SUPPORT_AP 0 */ 31/* define DM_ODM_SUPPORT_ADSL 0 */ 32/* define DM_ODM_SUPPORT_CE 0 */ 33/* define DM_ODM_SUPPORT_MP 1 */ 34 35#define TP_MODE 0 36#define RSSI_MODE 1 37#define TRAFFIC_LOW 0 38#define TRAFFIC_HIGH 1 39 40 41/* */ 42/* 3 Tx Power Tracking */ 43/* 3============================================================ */ 44#define DPK_DELTA_MAPPING_NUM 13 45#define index_mapping_HP_NUM 15 46 47 48/* */ 49/* 3 PSD Handler */ 50/* 3============================================================ */ 51 52#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 53#define MODE_40M 0 /* 0:20M, 1:40M */ 54#define PSD_TH2 3 55#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 56#define SIR_STEP_SIZE 3 57#define Smooth_Size_1 5 58#define Smooth_TH_1 3 59#define Smooth_Size_2 10 60#define Smooth_TH_2 4 61#define Smooth_Size_3 20 62#define Smooth_TH_3 4 63#define Smooth_Step_Size 5 64#define Adaptive_SIR 1 65#define PSD_RESCAN 4 66#define PSD_SCAN_INTERVAL 700 /* ms */ 67 68/* 8723A High Power IGI Setting */ 69#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 70#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 71#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 72 73/* LPS define */ 74#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ 75#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ 76#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ 77#define RSSI_OFFSET_DIG 0x05; 78 79/* ANT Test */ 80#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 81#define ANTTESTA 0x01 /* Ant A will be Testing */ 82#define ANTTESTB 0x02 /* Ant B will be testing */ 83 84 85/* */ 86/* structure and define */ 87/* */ 88 89struct dig_t { 90 u8 Dig_Enable_Flag; 91 u8 Dig_Ext_Port_Stage; 92 93 int RssiLowThresh; 94 int RssiHighThresh; 95 96 u32 FALowThresh; 97 u32 FAHighThresh; 98 99 u8 CurSTAConnectState; 100 u8 PreSTAConnectState; 101 u8 CurMultiSTAConnectState; 102 103 u8 PreIGValue; 104 u8 CurIGValue; 105 u8 BackupIGValue; 106 107 s8 BackoffVal; 108 s8 BackoffVal_range_max; 109 s8 BackoffVal_range_min; 110 u8 rx_gain_range_max; 111 u8 rx_gain_range_min; 112 u8 Rssi_val_min; 113 114 u8 PreCCK_CCAThres; 115 u8 CurCCK_CCAThres; 116 u8 PreCCKPDState; 117 u8 CurCCKPDState; 118 119 u8 LargeFAHit; 120 u8 ForbiddenIGI; 121 u32 Recover_cnt; 122 123 u8 DIG_Dynamic_MIN_0; 124 u8 DIG_Dynamic_MIN_1; 125 bool bMediaConnect_0; 126 bool bMediaConnect_1; 127 128 u32 AntDiv_RSSI_max; 129 u32 RSSI_max; 130}; 131 132struct dynamic_pwr_sav { 133 u8 PreCCAState; 134 u8 CurCCAState; 135 136 u8 PreRFState; 137 u8 CurRFState; 138 139 int Rssi_val_min; 140 141 u8 initialize; 142 u32 Reg874,RegC70,Reg85C,RegA74; 143}; 144 145struct false_alarm_stats { 146 u32 Cnt_Parity_Fail; 147 u32 Cnt_Rate_Illegal; 148 u32 Cnt_Crc8_fail; 149 u32 Cnt_Mcs_fail; 150 u32 Cnt_Ofdm_fail; 151 u32 Cnt_Cck_fail; 152 u32 Cnt_all; 153 u32 Cnt_Fast_Fsync; 154 u32 Cnt_SB_Search_fail; 155 u32 Cnt_OFDM_CCA; 156 u32 Cnt_CCK_CCA; 157 u32 Cnt_CCA_all; 158 u32 Cnt_BW_USC; /* Gary */ 159 u32 Cnt_BW_LSC; /* Gary */ 160}; 161 162struct pri_cca { 163 u8 PriCCA_flag; 164 u8 intf_flag; 165 u8 intf_type; 166 u8 DupRTS_flag; 167 u8 Monitor_flag; 168}; 169 170struct rx_hp { 171 u8 RXHP_flag; 172 u8 PSD_func_trigger; 173 u8 PSD_bitmap_RXHP[80]; 174 u8 Pre_IGI; 175 u8 Cur_IGI; 176 u8 Pre_pw_th; 177 u8 Cur_pw_th; 178 bool First_time_enter; 179 bool RXHP_enable; 180 u8 TP_Mode; 181}; 182 183#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 184#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 185 186/* This indicates two different the steps. */ 187/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 188/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 189/* with original RSSI to determine if it is necessary to switch antenna. */ 190#define SWAW_STEP_PEAK 0 191#define SWAW_STEP_DETERMINE 1 192 193#define TP_MODE 0 194#define RSSI_MODE 1 195#define TRAFFIC_LOW 0 196#define TRAFFIC_HIGH 1 197 198struct sw_ant_sw { 199 u8 try_flag; 200 s32 PreRSSI; 201 u8 CurAntenna; 202 u8 PreAntenna; 203 u8 RSSI_Trying; 204 u8 TestMode; 205 u8 bTriggerAntennaSwitch; 206 u8 SelectAntennaMap; 207 u8 RSSI_target; 208 209 /* Before link Antenna Switch check */ 210 u8 SWAS_NoLink_State; 211 u32 SWAS_NoLink_BK_Reg860; 212 bool ANTA_ON; /* To indicate Ant A is or not */ 213 bool ANTB_ON; /* To indicate Ant B is on or not */ 214 215 s32 RSSI_sum_A; 216 s32 RSSI_sum_B; 217 s32 RSSI_cnt_A; 218 s32 RSSI_cnt_B; 219 220 u64 lastTxOkCnt; 221 u64 lastRxOkCnt; 222 u64 TXByteCnt_A; 223 u64 TXByteCnt_B; 224 u64 RXByteCnt_A; 225 u64 RXByteCnt_B; 226 u8 TrafficLoad; 227}; 228 229struct edca_turbo { 230 bool bCurrentTurboEDCA; 231 bool bIsCurRDLState; 232 u32 prv_traffic_idx; /* edca turbo */ 233}; 234 235struct odm_rate_adapt { 236 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 237 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 238 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 239 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 240 u32 LastRATR; /* RATR Register Content */ 241}; 242 243#define IQK_MAC_REG_NUM 4 244#define IQK_ADDA_REG_NUM 16 245#define IQK_BB_REG_NUM_MAX 10 246#define IQK_BB_REG_NUM 9 247#define HP_THERMAL_NUM 8 248 249#define AVG_THERMAL_NUM 8 250#define IQK_Matrix_REG_NUM 8 251#define IQK_Matrix_Settings_NUM 1+24+21 252 253#define DM_Type_ByFW 0 254#define DM_Type_ByDriver 1 255 256/* Declare for common info */ 257 258struct odm_phy_dbg_info { 259 /* ODM Write,debug info */ 260 s8 RxSNRdB[RF_PATH_MAX]; 261 u64 NumQryPhyStatus; 262 u64 NumQryPhyStatusCCK; 263 u64 NumQryPhyStatusOFDM; 264 /* Others */ 265 s32 RxEVM[RF_PATH_MAX]; 266 267}; 268 269struct odm_packet_info { 270 u8 Rate; 271 u8 StationID; 272 bool bPacketMatchBSSID; 273 bool bPacketToSelf; 274 bool bPacketBeacon; 275}; 276 277 278enum { 279 /* BB Team */ 280 ODM_DIG = 0x00000001, 281 ODM_HIGH_POWER = 0x00000002, 282 ODM_CCK_CCA_TH = 0x00000004, 283 ODM_FA_STATISTICS = 0x00000008, 284 ODM_RAMASK = 0x00000010, 285 ODM_RSSI_MONITOR = 0x00000020, 286 ODM_SW_ANTDIV = 0x00000040, 287 ODM_HW_ANTDIV = 0x00000080, 288 ODM_BB_PWRSV = 0x00000100, 289 ODM_2TPATHDIV = 0x00000200, 290 ODM_1TPATHDIV = 0x00000400, 291 ODM_PSD2AFH = 0x00000800 292}; 293 294/* */ 295/* 2011/10/20 MH Define Common info enum for all team. */ 296/* */ 297 298enum odm_cmninfo { 299 /* Fixed value: */ 300 /* */ 301 302 ODM_CMNINFO_PLATFORM = 0, 303 ODM_CMNINFO_ABILITY, /* enum odm_ability */ 304 ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */ 305 ODM_CMNINFO_MP_TEST_CHIP, 306 ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */ 307 ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */ 308 ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */ 309 ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */ 310 ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */ 311 ODM_CMNINFO_EXT_LNA, /* true */ 312 ODM_CMNINFO_EXT_PA, 313 ODM_CMNINFO_EXT_TRSW, 314 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 315 ODM_CMNINFO_BINHCT_TEST, 316 ODM_CMNINFO_BWIFI_TEST, 317 ODM_CMNINFO_SMART_CONCURRENT, 318 319 320 /* */ 321 /* Dynamic value: */ 322 /* */ 323 ODM_CMNINFO_MAC_PHY_MODE, /* enum odm_mac_phy_mode */ 324 ODM_CMNINFO_TX_UNI, 325 ODM_CMNINFO_RX_UNI, 326 ODM_CMNINFO_WM_MODE, /* enum odm_wireless_mode */ 327 ODM_CMNINFO_BAND, /* enum odm_band_type */ 328 ODM_CMNINFO_SEC_CHNL_OFFSET, /* enum odm_sec_chnl_offset */ 329 ODM_CMNINFO_SEC_MODE, /* enum odm_security */ 330 ODM_CMNINFO_BW, /* enum odm_band_width */ 331 ODM_CMNINFO_CHNL, 332 333 ODM_CMNINFO_DMSP_GET_VALUE, 334 ODM_CMNINFO_BUDDY_ADAPTOR, 335 ODM_CMNINFO_DMSP_IS_MASTER, 336 ODM_CMNINFO_SCAN, 337 ODM_CMNINFO_POWER_SAVING, 338 ODM_CMNINFO_ONE_PATH_CCA, /* enum odm_cca_path */ 339 ODM_CMNINFO_DRV_STOP, 340 ODM_CMNINFO_PNP_IN, 341 ODM_CMNINFO_INIT_ON, 342 ODM_CMNINFO_ANT_TEST, 343 ODM_CMNINFO_NET_CLOSED, 344 ODM_CMNINFO_MP_MODE, 345 346 ODM_CMNINFO_WIFI_DIRECT, 347 ODM_CMNINFO_WIFI_DISPLAY, 348 ODM_CMNINFO_LINK, 349 ODM_CMNINFO_RSSI_MIN, 350 ODM_CMNINFO_DBG_COMP, /* u64 */ 351 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 352 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 353 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 354 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 355 ODM_CMNINFO_BT_DISABLED, 356 ODM_CMNINFO_BT_OPERATION, 357 ODM_CMNINFO_BT_DIG, 358 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ 359 ODM_CMNINFO_BT_DISABLE_EDCA, 360 361 /* */ 362 /* Dynamic ptr array hook itms. */ 363 /* */ 364 ODM_CMNINFO_STA_STATUS, 365 ODM_CMNINFO_PHY_STATUS, 366 ODM_CMNINFO_MAC_STATUS, 367 368 ODM_CMNINFO_MAX, 369}; 370 371/* Define ODM support ability. ODM_CMNINFO_ABILITY */ 372enum { 373 /* BB ODM section BIT 0-15 */ 374 ODM_BB_DIG = BIT(0), 375 ODM_BB_RA_MASK = BIT(1), 376 ODM_BB_DYNAMIC_TXPWR = BIT(2), 377 ODM_BB_FA_CNT = BIT(3), 378 ODM_BB_RSSI_MONITOR = BIT(4), 379 ODM_BB_CCK_PD = BIT(5), 380 ODM_BB_ANT_DIV = BIT(6), 381 ODM_BB_PWR_SAVE = BIT(7), 382 ODM_BB_PWR_TRAIN = BIT(8), 383 ODM_BB_RATE_ADAPTIVE = BIT(9), 384 ODM_BB_PATH_DIV = BIT(10), 385 ODM_BB_PSD = BIT(11), 386 ODM_BB_RXHP = BIT(12), 387 388 /* MAC DM section BIT 16-23 */ 389 ODM_MAC_EDCA_TURBO = BIT(16), 390 ODM_MAC_EARLY_MODE = BIT(17), 391 392 /* RF ODM section BIT 24-31 */ 393 ODM_RF_TX_PWR_TRACK = BIT(24), 394 ODM_RF_RX_GAIN_TRACK = BIT(25), 395 ODM_RF_CALIBRATION = BIT(26), 396 397}; 398 399/* ODM_CMNINFO_INTERFACE */ 400enum odm_interface_def { 401 ODM_ITRF_PCIE = 0x1, 402 ODM_ITRF_USB = 0x2, 403 ODM_ITRF_SDIO = 0x4, 404 ODM_ITRF_ALL = 0x7, 405}; 406 407/* ODM_CMNINFO_IC_TYPE */ 408enum odm_ic_type_def { 409 ODM_RTL8192S = BIT(0), 410 ODM_RTL8192C = BIT(1), 411 ODM_RTL8192D = BIT(2), 412 ODM_RTL8723A = BIT(3), 413 ODM_RTL8188E = BIT(4), 414 ODM_RTL8812 = BIT(5), 415 ODM_RTL8821 = BIT(6), 416}; 417 418/* ODM_CMNINFO_CUT_VER */ 419enum odm_cut_version { 420 ODM_CUT_A = 1, 421 ODM_CUT_B = 2, 422 ODM_CUT_C = 3, 423 ODM_CUT_D = 4, 424 ODM_CUT_E = 5, 425 ODM_CUT_F = 6, 426 ODM_CUT_TEST = 7, 427}; 428 429/* ODM_CMNINFO_FAB_VER */ 430enum odm_fab_version { 431 ODM_TSMC = 0, 432 ODM_UMC = 1, 433}; 434 435/* ODM_CMNINFO_RF_TYPE */ 436/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 437enum rf_path_def { 438 ODM_RF_TX_A = BIT(0), 439 ODM_RF_TX_B = BIT(1), 440 ODM_RF_TX_C = BIT(2), 441 ODM_RF_TX_D = BIT(3), 442 ODM_RF_RX_A = BIT(4), 443 ODM_RF_RX_B = BIT(5), 444 ODM_RF_RX_C = BIT(6), 445 ODM_RF_RX_D = BIT(7), 446}; 447 448 449enum odm_rf_type { 450 ODM_1T1R = 0, 451 ODM_1T2R = 1, 452 ODM_2T2R = 2, 453 ODM_2T3R = 3, 454 ODM_2T4R = 4, 455 ODM_3T3R = 5, 456 ODM_3T4R = 6, 457 ODM_4T4R = 7, 458}; 459 460/* ODM Dynamic common info value definition */ 461 462enum odm_mac_phy_mode { 463 ODM_SMSP = 0, 464 ODM_DMSP = 1, 465 ODM_DMDP = 2, 466}; 467 468 469enum odm_bt_coexist { 470 ODM_BT_BUSY = 1, 471 ODM_BT_ON = 2, 472 ODM_BT_OFF = 3, 473 ODM_BT_NONE = 4, 474}; 475 476/* ODM_CMNINFO_OP_MODE */ 477enum odm_operation_mode { 478 ODM_NO_LINK = BIT(0), 479 ODM_LINK = BIT(1), 480 ODM_SCAN = BIT(2), 481 ODM_POWERSAVE = BIT(3), 482 ODM_AP_MODE = BIT(4), 483 ODM_CLIENT_MODE = BIT(5), 484 ODM_AD_HOC = BIT(6), 485 ODM_WIFI_DIRECT = BIT(7), 486 ODM_WIFI_DISPLAY = BIT(8), 487}; 488 489/* ODM_CMNINFO_WM_MODE */ 490enum odm_wireless_mode { 491 ODM_WM_UNKNOW = 0x0, 492 ODM_WM_B = BIT(0), 493 ODM_WM_G = BIT(1), 494 ODM_WM_A = BIT(2), 495 ODM_WM_N24G = BIT(3), 496 ODM_WM_N5G = BIT(4), 497 ODM_WM_AUTO = BIT(5), 498 ODM_WM_AC = BIT(6), 499}; 500 501/* ODM_CMNINFO_BAND */ 502enum odm_band_type { 503 ODM_BAND_2_4G = BIT(0), 504 ODM_BAND_5G = BIT(1), 505 506}; 507 508/* ODM_CMNINFO_SEC_CHNL_OFFSET */ 509enum odm_sec_chnl_offset { 510 ODM_DONT_CARE = 0, 511 ODM_BELOW = 1, 512 ODM_ABOVE = 2 513}; 514 515/* ODM_CMNINFO_BW */ 516enum odm_band_width { 517 ODM_BW20M = 0, 518 ODM_BW40M = 1, 519 ODM_BW80M = 2, 520 ODM_BW160M = 3, 521 ODM_BW10M = 4, 522}; 523 524/* ODM_CMNINFO_CHNL */ 525 526/* ODM_CMNINFO_BOARD_TYPE */ 527enum odm_board_type { 528 ODM_BOARD_NORMAL = 0, 529 ODM_BOARD_HIGHPWR = 1, 530 ODM_BOARD_MINICARD = 2, 531 ODM_BOARD_SLIM = 3, 532 ODM_BOARD_COMBO = 4, 533 534}; 535 536/* ODM_CMNINFO_ONE_PATH_CCA */ 537enum odm_cca_path { 538 ODM_CCA_2R = 0, 539 ODM_CCA_1R_A = 1, 540 ODM_CCA_1R_B = 2, 541}; 542 543struct iqk_matrix_regs_set { 544 bool bIQKDone; 545 s32 Value[1][IQK_Matrix_REG_NUM]; 546}; 547 548struct odm_rf_cal_t { 549 /* for tx power tracking */ 550 551 u32 RegA24; /* for TempCCK */ 552 s32 RegE94; 553 s32 RegE9C; 554 s32 RegEB4; 555 s32 RegEBC; 556 557 /* u8 bTXPowerTracking; */ 558 u8 TXPowercount; 559 bool bTXPowerTrackingInit; 560 bool bTXPowerTracking; 561 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 562 u8 TM_Trigger; 563 u8 InternalPA5G[2]; /* pathA / pathB */ 564 565 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 566 u8 ThermalValue; 567 u8 ThermalValue_LCK; 568 u8 ThermalValue_IQK; 569 u8 ThermalValue_DPK; 570 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 571 u8 ThermalValue_AVG_index; 572 u8 ThermalValue_RxGain; 573 u8 ThermalValue_Crystal; 574 u8 ThermalValue_DPKstore; 575 u8 ThermalValue_DPKtrack; 576 bool TxPowerTrackingInProgress; 577 bool bDPKenable; 578 579 bool bReloadtxpowerindex; 580 u8 bRfPiEnable; 581 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 582 583 u8 bCCKinCH14; 584 u8 CCK_index; 585 u8 OFDM_index[2]; 586 bool bDoneTxpower; 587 588 u8 ThermalValue_HP[HP_THERMAL_NUM]; 589 u8 ThermalValue_HP_index; 590 struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 591 592 u8 Delta_IQK; 593 u8 Delta_LCK; 594 595 /* for IQK */ 596 u32 RegC04; 597 u32 Reg874; 598 u32 RegC08; 599 u32 RegB68; 600 u32 RegB6C; 601 u32 Reg870; 602 u32 Reg860; 603 u32 Reg864; 604 605 bool bIQKInitialized; 606 bool bLCKInProgress; 607 bool bAntennaDetected; 608 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 609 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 610 u32 IQK_BB_backup_recover[9]; 611 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 612 613 /* for APK */ 614 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 615 u8 bAPKdone; 616 u8 bAPKThermalMeterIgnore; 617 u8 bDPdone; 618 u8 bDPPathAOK; 619 u8 bDPPathBOK; 620}; 621 622/* ODM Dynamic common info value definition */ 623struct odm_fat_t { 624 u8 Bssid[6]; 625 u8 antsel_rx_keep_0; 626 u8 antsel_rx_keep_1; 627 u8 antsel_rx_keep_2; 628 u32 antSumRSSI[7]; 629 u32 antRSSIcnt[7]; 630 u32 antAveRSSI[7]; 631 u8 FAT_State; 632 u32 TrainIdx; 633 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 634 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 635 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 636 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 637 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 638 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 639 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 640 u8 RxIdleAnt; 641 bool bBecomeLinked; 642}; 643 644enum fat_state { 645 FAT_NORMAL_STATE = 0, 646 FAT_TRAINING_STATE = 1, 647}; 648 649enum ant_dif_type { 650 NO_ANTDIV = 0xFF, 651 CG_TRX_HW_ANTDIV = 0x01, 652 CGCS_RX_HW_ANTDIV = 0x02, 653 FIXED_HW_ANTDIV = 0x03, 654 CG_TRX_SMART_ANTDIV = 0x04, 655 CGCS_RX_SW_ANTDIV = 0x05, 656}; 657 658/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 659struct dm_odm_t { 660 /* */ 661 /* Add for different team use temporarily */ 662 /* */ 663 struct rtw_adapter *Adapter; /* For CE/NIC team */ 664 665 u64 DebugComponents; 666 u32 DebugLevel; 667 668/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 669 bool bCckHighPower; 670 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 671 u8 ControlChannel; 672/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 673 674/* 1 COMMON INFORMATION */ 675 676 /* Init Value */ 677/* HOOK BEFORE REG INIT----------- */ 678 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 679 u32 SupportAbility; 680 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ 681 u8 SupportInterface; 682 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 683 u32 SupportICType; 684 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 685 u8 CutVersion; 686 /* Fab Version TSMC/UMC = 0/1 */ 687 u8 FabVersion; 688 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 689 u8 RFType; 690 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 691 u8 BoardType; 692 /* with external LNA NO/Yes = 0/1 */ 693 u8 ExtLNA; 694 /* with external PA NO/Yes = 0/1 */ 695 u8 ExtPA; 696 /* with external TRSW NO/Yes = 0/1 */ 697 u8 ExtTRSW; 698 u8 PatchID; /* Customer ID */ 699 bool bInHctTest; 700 bool bWIFITest; 701 702 bool bDualMacSmartConcurrent; 703 u32 BK_SupportAbility; 704 u8 AntDivType; 705/* HOOK BEFORE REG INIT----------- */ 706 707 /* */ 708 /* Dynamic Value */ 709 /* */ 710/* POINTER REFERENCE----------- */ 711 712 u8 u8_temp; 713 bool bool_temp; 714 struct rtw_adapter *PADAPTER_temp; 715 716 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 717 u8 *pMacPhyMode; 718 /* TX Unicast byte count */ 719 u64 *pNumTxBytesUnicast; 720 /* RX Unicast byte count */ 721 u64 *pNumRxBytesUnicast; 722 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 723 u8 *pWirelessMode; /* enum odm_wireless_mode */ 724 /* Frequence band 2.4G/5G = 0/1 */ 725 u8 *pBandType; 726 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 727 u8 *pSecChOffset; 728 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 729 u8 *pSecurity; 730 /* BW info 20M/40M/80M = 0/1/2 */ 731 u8 *pBandWidth; 732 /* Central channel location Ch1/Ch2/.... */ 733 u8 *pChannel; /* central channel number */ 734 /* Common info for 92D DMSP */ 735 736 bool *pbGetValueFromOtherMac; 737 struct rtw_adapter **pBuddyAdapter; 738 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 739 /* Common info for Status */ 740 bool *pbScanInProcess; 741 bool *pbPowerSaving; 742 /* CCA Path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path. */ 743 u8 *pOnePathCCA; 744 /* pMgntInfo->AntennaTest */ 745 u8 *pAntennaTest; 746 bool *pbNet_closed; 747/* POINTER REFERENCE----------- */ 748 /* */ 749/* CALL BY VALUE------------- */ 750 bool bWIFI_Direct; 751 bool bWIFI_Display; 752 bool bLinked; 753 u8 RSSI_Min; 754 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 755 bool bIsMPChip; 756 bool bOneEntryOnly; 757 /* Common info for BTDM */ 758 bool bBtDisabled; /* BT is disabled */ 759 bool bBtHsOperation; /* BT HS mode is under progress */ 760 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 761 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 762 bool bBtBusy; /* BT is busy. */ 763/* CALL BY VALUE------------- */ 764 765 /* 2 Define STA info. */ 766 /* _ODM_STA_INFO */ 767 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 768 struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 769 770 /* */ 771 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 772 /* We need to colelct all support abilit to a proper area. */ 773 /* */ 774 bool RaSupport88E; 775 776 /* Define ........... */ 777 778 /* Latest packet phy info (ODM write) */ 779 struct odm_phy_dbg_info PhyDbgInfo; 780 /* PHY_INFO_88E PhyInfo; */ 781 782 /* Latest packet phy info (ODM write) */ 783 /* MAC_INFO_88E MacInfo; */ 784 785 /* Different Team independt structure?? */ 786 787 /* */ 788 /* TX_RTP_CMN TX_retrpo; */ 789 /* TX_RTP_88E TX_retrpo; */ 790 /* TX_RTP_8195 TX_retrpo; */ 791 792 /* */ 793 /* ODM Structure */ 794 /* */ 795 struct odm_fat_t DM_FatTable; 796 struct dig_t DM_DigTable; 797 struct dynamic_pwr_sav DM_PSTable; 798 struct pri_cca DM_PriCCA; 799 struct rx_hp DM_RXHP_Table; 800 struct false_alarm_stats FalseAlmCnt; 801 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 802 struct sw_ant_sw DM_SWAT_Table; 803 bool RSSI_test; 804 805 struct edca_turbo DM_EDCA_Table; 806 u32 WMMEDCA_BE; 807 /* Copy from SD4 structure */ 808 /* */ 809 /* ================================================== */ 810 /* */ 811 812 /* common */ 813 bool *pbDriverStopped; 814 bool *pbDriverIsGoingToPnpSetPowerSleep; 815 bool *pinit_adpt_in_progress; 816 817 /* PSD */ 818 bool bUserAssignLevel; 819 u8 RSSI_BT; /* come from BT */ 820 bool bPSDinProcess; 821 822 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 823 u8 bUseRAMask; 824 825 struct odm_rate_adapt RateAdaptive; 826 827 828 struct odm_rf_cal_t RFCalibrateInfo; 829 830 /* */ 831 /* TX power tracking */ 832 /* */ 833 u8 BbSwingIdxOfdm; 834 u8 BbSwingIdxOfdmCurrent; 835 u8 BbSwingIdxOfdmBase; 836 bool BbSwingFlagOfdm; 837 u8 BbSwingIdxCck; 838 u8 BbSwingIdxCckCurrent; 839 u8 BbSwingIdxCckBase; 840 bool BbSwingFlagCck; 841 /* */ 842 /* ODM system resource. */ 843 /* */ 844}; /* DM_Dynamic_Mechanism_Structure */ 845 846enum odm_rf_content { 847 odm_radioa_txt = 0x1000, 848 odm_radiob_txt = 0x1001, 849 odm_radioc_txt = 0x1002, 850 odm_radiod_txt = 0x1003 851}; 852 853/* Status code */ 854enum rt_status { 855 RT_STATUS_SUCCESS, 856 RT_STATUS_FAILURE, 857 RT_STATUS_PENDING, 858 RT_STATUS_RESOURCE, 859 RT_STATUS_INVALID_CONTEXT, 860 RT_STATUS_INVALID_PARAMETER, 861 RT_STATUS_NOT_SUPPORT, 862 RT_STATUS_OS_API_FAILED, 863}; 864 865/* include "odm_function.h" */ 866 867/* 3=========================================================== */ 868/* 3 DIG */ 869/* 3=========================================================== */ 870 871enum dm_dig_op { 872 DIG_TYPE_THRESH_HIGH = 0, 873 DIG_TYPE_THRESH_LOW = 1, 874 DIG_TYPE_BACKOFF = 2, 875 DIG_TYPE_RX_GAIN_MIN = 3, 876 DIG_TYPE_RX_GAIN_MAX = 4, 877 DIG_TYPE_ENABLE = 5, 878 DIG_TYPE_DISABLE = 6, 879 DIG_OP_TYPE_MAX 880}; 881 882#define DM_DIG_THRESH_HIGH 40 883#define DM_DIG_THRESH_LOW 35 884 885#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ 886 887 888#define DM_FALSEALARM_THRESH_LOW 400 889#define DM_FALSEALARM_THRESH_HIGH 1000 890 891#define DM_DIG_MAX_NIC 0x4e 892#define DM_DIG_MIN_NIC 0x1e 893 894#define DM_DIG_MAX_AP 0x32 895#define DM_DIG_MIN_AP 0x20 896 897#define DM_DIG_MAX_NIC_HP 0x46 898#define DM_DIG_MIN_NIC_HP 0x2e 899 900#define DM_DIG_MAX_AP_HP 0x42 901#define DM_DIG_MIN_AP_HP 0x30 902 903/* vivi 92c&92d has different definition, 20110504 */ 904/* this is for 92c */ 905#define DM_DIG_FA_TH0 0x200 906#define DM_DIG_FA_TH1 0x300 907#define DM_DIG_FA_TH2 0x400 908/* this is for 92d */ 909#define DM_DIG_FA_TH0_92D 0x100 910#define DM_DIG_FA_TH1_92D 0x400 911#define DM_DIG_FA_TH2_92D 0x600 912 913#define DM_DIG_BACKOFF_MAX 12 914#define DM_DIG_BACKOFF_MIN -4 915#define DM_DIG_BACKOFF_DEFAULT 10 916 917/* 3=========================================================== */ 918/* 3 AGC RX High Power Mode */ 919/* 3=========================================================== */ 920#define LNA_Low_Gain_1 0x64 921#define LNA_Low_Gain_2 0x5A 922#define LNA_Low_Gain_3 0x58 923 924#define FA_RXHP_TH1 5000 925#define FA_RXHP_TH2 1500 926#define FA_RXHP_TH3 800 927#define FA_RXHP_TH4 600 928#define FA_RXHP_TH5 500 929 930/* 3=========================================================== */ 931/* 3 EDCA */ 932/* 3=========================================================== */ 933 934/* 3=========================================================== */ 935/* 3 Dynamic Tx Power */ 936/* 3=========================================================== */ 937/* Dynamic Tx Power Control Threshold */ 938#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 939#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 940#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 941 942#define TxHighPwrLevel_Normal 0 943#define TxHighPwrLevel_Level1 1 944#define TxHighPwrLevel_Level2 2 945#define TxHighPwrLevel_BT1 3 946#define TxHighPwrLevel_BT2 4 947#define TxHighPwrLevel_15 5 948#define TxHighPwrLevel_35 6 949#define TxHighPwrLevel_50 7 950#define TxHighPwrLevel_70 8 951#define TxHighPwrLevel_100 9 952 953/* 3=========================================================== */ 954/* 3 Rate Adaptive */ 955/* 3=========================================================== */ 956#define DM_RATR_STA_INIT 0 957#define DM_RATR_STA_HIGH 1 958#define DM_RATR_STA_MIDDLE 2 959#define DM_RATR_STA_LOW 3 960 961/* 3=========================================================== */ 962/* 3 BB Power Save */ 963/* 3=========================================================== */ 964 965 966enum dm_1r_cca { 967 CCA_1R =0, 968 CCA_2R = 1, 969 CCA_MAX = 2, 970}; 971 972enum dm_rf_def { 973 RF_Save =0, 974 RF_Normal = 1, 975 RF_MAX = 2, 976}; 977 978/* 3=========================================================== */ 979/* 3 Antenna Diversity */ 980/* 3=========================================================== */ 981enum dm_swas { 982 Antenna_A = 1, 983 Antenna_B = 2, 984 Antenna_MAX = 3, 985}; 986 987/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 988#define MAX_ANTENNA_DETECTION_CNT 10 989 990/* */ 991/* Extern Global Variables. */ 992/* */ 993#define OFDM_TABLE_SIZE_92C 37 994#define OFDM_TABLE_SIZE_92D 43 995#define CCK_TABLE_SIZE 33 996 997extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D]; 998extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8]; 999extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8]; 1000 1001 1002 1003/* 20100514 Joseph: Add definition for antenna switching test after link. */ 1004/* This indicates two different the steps. */ 1005/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1006/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1007/* with original RSSI to determine if it is necessary to switch antenna. */ 1008#define SWAW_STEP_PEAK 0 1009#define SWAW_STEP_DETERMINE 1 1010 1011void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI); 1012void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres); 1013 1014void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna); 1015 1016 1017#define dm_RF_Saving ODM_RF_Saving23a 1018void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal); 1019 1020#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink 1021void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm); 1022 1023#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a 1024void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm); 1025 1026bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate, 1027 u8 *pRATRState); 1028 1029 1030#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1031void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID, 1032 struct phy_info *pPhyInfo); 1033 1034u32 ConvertTo_dB23a(u32 Value); 1035 1036u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd); 1037 1038void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm); 1039 1040u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level); 1041 1042 1043void ODM23a_DMInit(struct dm_odm_t *pDM_Odm); 1044 1045void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1046 1047void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value); 1048 1049void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, void *pValue); 1050 1051void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue); 1052 1053void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1054 1055void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm); 1056 1057void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate); 1058 1059void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm); 1060 1061bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode); 1062 1063void odm_dtc(struct dm_odm_t *pDM_Odm); 1064 1065#endif 1066