odm.h revision 59497030a27ef67a2c06fa362218aa4dcdfd4410
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17#ifndef __HALDMOUTSRC_H__ 18#define __HALDMOUTSRC_H__ 19 20/* */ 21/* Definition */ 22/* */ 23/* */ 24/* 2011/09/22 MH Define all team supprt ability. */ 25/* */ 26 27/* */ 28/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ 29/* */ 30/* define DM_ODM_SUPPORT_AP 0 */ 31/* define DM_ODM_SUPPORT_ADSL 0 */ 32/* define DM_ODM_SUPPORT_CE 0 */ 33/* define DM_ODM_SUPPORT_MP 1 */ 34 35#define TP_MODE 0 36#define RSSI_MODE 1 37#define TRAFFIC_LOW 0 38#define TRAFFIC_HIGH 1 39 40 41/* */ 42/* 3 Tx Power Tracking */ 43/* 3============================================================ */ 44#define DPK_DELTA_MAPPING_NUM 13 45#define index_mapping_HP_NUM 15 46 47 48/* */ 49/* 3 PSD Handler */ 50/* 3============================================================ */ 51 52#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 53#define MODE_40M 0 /* 0:20M, 1:40M */ 54#define PSD_TH2 3 55#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 56#define SIR_STEP_SIZE 3 57#define Smooth_Size_1 5 58#define Smooth_TH_1 3 59#define Smooth_Size_2 10 60#define Smooth_TH_2 4 61#define Smooth_Size_3 20 62#define Smooth_TH_3 4 63#define Smooth_Step_Size 5 64#define Adaptive_SIR 1 65#define PSD_RESCAN 4 66#define PSD_SCAN_INTERVAL 700 /* ms */ 67 68/* 8723A High Power IGI Setting */ 69#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 70#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 71#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 72 73/* LPS define */ 74#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ 75#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ 76#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ 77#define RSSI_OFFSET_DIG 0x05; 78 79/* ANT Test */ 80#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 81#define ANTTESTA 0x01 /* Ant A will be Testing */ 82#define ANTTESTB 0x02 /* Ant B will be testing */ 83 84 85/* */ 86/* structure and define */ 87/* */ 88 89/* */ 90/* 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. */ 91/* We need to remove to other position??? */ 92/* */ 93struct rtl8723a_priv { 94 u8 temp; 95}; 96 97 98struct dig_t { 99 u8 Dig_Enable_Flag; 100 u8 Dig_Ext_Port_Stage; 101 102 int RssiLowThresh; 103 int RssiHighThresh; 104 105 u32 FALowThresh; 106 u32 FAHighThresh; 107 108 u8 CurSTAConnectState; 109 u8 PreSTAConnectState; 110 u8 CurMultiSTAConnectState; 111 112 u8 PreIGValue; 113 u8 CurIGValue; 114 u8 BackupIGValue; 115 116 s8 BackoffVal; 117 s8 BackoffVal_range_max; 118 s8 BackoffVal_range_min; 119 u8 rx_gain_range_max; 120 u8 rx_gain_range_min; 121 u8 Rssi_val_min; 122 123 u8 PreCCK_CCAThres; 124 u8 CurCCK_CCAThres; 125 u8 PreCCKPDState; 126 u8 CurCCKPDState; 127 128 u8 LargeFAHit; 129 u8 ForbiddenIGI; 130 u32 Recover_cnt; 131 132 u8 DIG_Dynamic_MIN_0; 133 u8 DIG_Dynamic_MIN_1; 134 bool bMediaConnect_0; 135 bool bMediaConnect_1; 136 137 u32 AntDiv_RSSI_max; 138 u32 RSSI_max; 139}; 140 141struct dynamic_pwr_sav { 142 u8 PreCCAState; 143 u8 CurCCAState; 144 145 u8 PreRFState; 146 u8 CurRFState; 147 148 int Rssi_val_min; 149 150 u8 initialize; 151 u32 Reg874,RegC70,Reg85C,RegA74; 152}; 153 154struct false_alarm_stats { 155 u32 Cnt_Parity_Fail; 156 u32 Cnt_Rate_Illegal; 157 u32 Cnt_Crc8_fail; 158 u32 Cnt_Mcs_fail; 159 u32 Cnt_Ofdm_fail; 160 u32 Cnt_Cck_fail; 161 u32 Cnt_all; 162 u32 Cnt_Fast_Fsync; 163 u32 Cnt_SB_Search_fail; 164 u32 Cnt_OFDM_CCA; 165 u32 Cnt_CCK_CCA; 166 u32 Cnt_CCA_all; 167 u32 Cnt_BW_USC; /* Gary */ 168 u32 Cnt_BW_LSC; /* Gary */ 169}; 170 171struct pri_cca { 172 u8 PriCCA_flag; 173 u8 intf_flag; 174 u8 intf_type; 175 u8 DupRTS_flag; 176 u8 Monitor_flag; 177}; 178 179struct rx_hp { 180 u8 RXHP_flag; 181 u8 PSD_func_trigger; 182 u8 PSD_bitmap_RXHP[80]; 183 u8 Pre_IGI; 184 u8 Cur_IGI; 185 u8 Pre_pw_th; 186 u8 Cur_pw_th; 187 bool First_time_enter; 188 bool RXHP_enable; 189 u8 TP_Mode; 190}; 191 192#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 193#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 194 195/* This indicates two different the steps. */ 196/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 197/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 198/* with original RSSI to determine if it is necessary to switch antenna. */ 199#define SWAW_STEP_PEAK 0 200#define SWAW_STEP_DETERMINE 1 201 202#define TP_MODE 0 203#define RSSI_MODE 1 204#define TRAFFIC_LOW 0 205#define TRAFFIC_HIGH 1 206 207struct sw_ant_sw { 208 u8 try_flag; 209 s32 PreRSSI; 210 u8 CurAntenna; 211 u8 PreAntenna; 212 u8 RSSI_Trying; 213 u8 TestMode; 214 u8 bTriggerAntennaSwitch; 215 u8 SelectAntennaMap; 216 u8 RSSI_target; 217 218 /* Before link Antenna Switch check */ 219 u8 SWAS_NoLink_State; 220 u32 SWAS_NoLink_BK_Reg860; 221 bool ANTA_ON; /* To indicate Ant A is or not */ 222 bool ANTB_ON; /* To indicate Ant B is on or not */ 223 224 s32 RSSI_sum_A; 225 s32 RSSI_sum_B; 226 s32 RSSI_cnt_A; 227 s32 RSSI_cnt_B; 228 229 u64 lastTxOkCnt; 230 u64 lastRxOkCnt; 231 u64 TXByteCnt_A; 232 u64 TXByteCnt_B; 233 u64 RXByteCnt_A; 234 u64 RXByteCnt_B; 235 u8 TrafficLoad; 236}; 237 238struct edca_turbo { 239 bool bCurrentTurboEDCA; 240 bool bIsCurRDLState; 241 u32 prv_traffic_idx; /* edca turbo */ 242}; 243 244struct odm_rate_adapt { 245 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 246 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 247 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 248 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 249 u32 LastRATR; /* RATR Register Content */ 250}; 251 252#define IQK_MAC_REG_NUM 4 253#define IQK_ADDA_REG_NUM 16 254#define IQK_BB_REG_NUM_MAX 10 255#define IQK_BB_REG_NUM 9 256#define HP_THERMAL_NUM 8 257 258#define AVG_THERMAL_NUM 8 259#define IQK_Matrix_REG_NUM 8 260#define IQK_Matrix_Settings_NUM 1+24+21 261 262#define DM_Type_ByFW 0 263#define DM_Type_ByDriver 1 264 265/* Declare for common info */ 266 267struct odm_phy_info { 268 u8 RxPWDBAll; 269 u8 SignalQuality; /* in 0-100 index. */ 270 u8 RxMIMOSignalQuality[RF_PATH_MAX]; /* EVM */ 271 u8 RxMIMOSignalStrength[RF_PATH_MAX];/* in 0~100 index */ 272 s8 RxPower; /* in dBm Translate from PWdB */ 273 s8 RecvSignalPower;/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ 274 u8 BTRxRSSIPercentage; 275 u8 SignalStrength; /* in 0-100 index. */ 276 u8 RxPwr[RF_PATH_MAX];/* per-path's pwdb */ 277 u8 RxSNR[RF_PATH_MAX];/* per-path's SNR */ 278}; 279 280 281struct odm_phy_dbg_info { 282 /* ODM Write,debug info */ 283 s8 RxSNRdB[RF_PATH_MAX]; 284 u64 NumQryPhyStatus; 285 u64 NumQryPhyStatusCCK; 286 u64 NumQryPhyStatusOFDM; 287 /* Others */ 288 s32 RxEVM[RF_PATH_MAX]; 289 290}; 291 292struct odm_packet_info { 293 u8 Rate; 294 u8 StationID; 295 bool bPacketMatchBSSID; 296 bool bPacketToSelf; 297 bool bPacketBeacon; 298}; 299 300struct odm_mac_info { 301 u8 test; 302 303}; 304 305 306enum { 307 /* BB Team */ 308 ODM_DIG = 0x00000001, 309 ODM_HIGH_POWER = 0x00000002, 310 ODM_CCK_CCA_TH = 0x00000004, 311 ODM_FA_STATISTICS = 0x00000008, 312 ODM_RAMASK = 0x00000010, 313 ODM_RSSI_MONITOR = 0x00000020, 314 ODM_SW_ANTDIV = 0x00000040, 315 ODM_HW_ANTDIV = 0x00000080, 316 ODM_BB_PWRSV = 0x00000100, 317 ODM_2TPATHDIV = 0x00000200, 318 ODM_1TPATHDIV = 0x00000400, 319 ODM_PSD2AFH = 0x00000800 320}; 321 322/* */ 323/* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ 324/* Please declare below ODM relative info in your STA info structure. */ 325/* */ 326struct odm_sta_info { 327 /* Driver Write */ 328 bool bUsed; /* record the sta status link or not? */ 329 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ 330 331 /* ODM Write */ 332 /* 1 PHY_STATUS_INFO */ 333 u8 RSSI_Path[4]; /* */ 334 u8 RSSI_Ave; 335 u8 RXEVM[4]; 336 u8 RXSNR[4]; 337 338 /* ODM Write */ 339 /* 1 TX_INFO (may changed by IC) */ 340 341 /* */ 342 /* Please use compile flag to disable the structure for other IC except 88E. */ 343 /* Move To lower layer. */ 344 /* */ 345 /* ODM Write Wilson will handle this part(said by Luke.Lee) */ 346}; 347 348/* */ 349/* 2011/10/20 MH Define Common info enum for all team. */ 350/* */ 351 352enum odm_cmninfo { 353 /* Fixed value: */ 354 /* */ 355 356 ODM_CMNINFO_PLATFORM = 0, 357 ODM_CMNINFO_ABILITY, /* enum odm_ability */ 358 ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */ 359 ODM_CMNINFO_MP_TEST_CHIP, 360 ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */ 361 ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */ 362 ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */ 363 ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */ 364 ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */ 365 ODM_CMNINFO_EXT_LNA, /* true */ 366 ODM_CMNINFO_EXT_PA, 367 ODM_CMNINFO_EXT_TRSW, 368 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 369 ODM_CMNINFO_BINHCT_TEST, 370 ODM_CMNINFO_BWIFI_TEST, 371 ODM_CMNINFO_SMART_CONCURRENT, 372 373 374 /* */ 375 /* Dynamic value: */ 376 /* */ 377 ODM_CMNINFO_MAC_PHY_MODE, /* enum odm_mac_phy_mode */ 378 ODM_CMNINFO_TX_UNI, 379 ODM_CMNINFO_RX_UNI, 380 ODM_CMNINFO_WM_MODE, /* enum odm_wireless_mode */ 381 ODM_CMNINFO_BAND, /* enum odm_band_type */ 382 ODM_CMNINFO_SEC_CHNL_OFFSET, /* enum odm_sec_chnl_offset */ 383 ODM_CMNINFO_SEC_MODE, /* enum odm_security */ 384 ODM_CMNINFO_BW, /* enum odm_band_width */ 385 ODM_CMNINFO_CHNL, 386 387 ODM_CMNINFO_DMSP_GET_VALUE, 388 ODM_CMNINFO_BUDDY_ADAPTOR, 389 ODM_CMNINFO_DMSP_IS_MASTER, 390 ODM_CMNINFO_SCAN, 391 ODM_CMNINFO_POWER_SAVING, 392 ODM_CMNINFO_ONE_PATH_CCA, /* enum odm_cca_path */ 393 ODM_CMNINFO_DRV_STOP, 394 ODM_CMNINFO_PNP_IN, 395 ODM_CMNINFO_INIT_ON, 396 ODM_CMNINFO_ANT_TEST, 397 ODM_CMNINFO_NET_CLOSED, 398 ODM_CMNINFO_MP_MODE, 399 400 ODM_CMNINFO_WIFI_DIRECT, 401 ODM_CMNINFO_WIFI_DISPLAY, 402 ODM_CMNINFO_LINK, 403 ODM_CMNINFO_RSSI_MIN, 404 ODM_CMNINFO_DBG_COMP, /* u64 */ 405 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 406 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 407 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 408 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 409 ODM_CMNINFO_BT_DISABLED, 410 ODM_CMNINFO_BT_OPERATION, 411 ODM_CMNINFO_BT_DIG, 412 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ 413 ODM_CMNINFO_BT_DISABLE_EDCA, 414 415 /* */ 416 /* Dynamic ptr array hook itms. */ 417 /* */ 418 ODM_CMNINFO_STA_STATUS, 419 ODM_CMNINFO_PHY_STATUS, 420 ODM_CMNINFO_MAC_STATUS, 421 422 ODM_CMNINFO_MAX, 423}; 424 425/* Define ODM support ability. ODM_CMNINFO_ABILITY */ 426enum { 427 /* BB ODM section BIT 0-15 */ 428 ODM_BB_DIG = BIT0, 429 ODM_BB_RA_MASK = BIT1, 430 ODM_BB_DYNAMIC_TXPWR = BIT2, 431 ODM_BB_FA_CNT = BIT3, 432 ODM_BB_RSSI_MONITOR = BIT4, 433 ODM_BB_CCK_PD = BIT5, 434 ODM_BB_ANT_DIV = BIT6, 435 ODM_BB_PWR_SAVE = BIT7, 436 ODM_BB_PWR_TRAIN = BIT8, 437 ODM_BB_RATE_ADAPTIVE = BIT9, 438 ODM_BB_PATH_DIV = BIT10, 439 ODM_BB_PSD = BIT11, 440 ODM_BB_RXHP = BIT12, 441 442 /* MAC DM section BIT 16-23 */ 443 ODM_MAC_EDCA_TURBO = BIT16, 444 ODM_MAC_EARLY_MODE = BIT17, 445 446 /* RF ODM section BIT 24-31 */ 447 ODM_RF_TX_PWR_TRACK = BIT24, 448 ODM_RF_RX_GAIN_TRACK = BIT25, 449 ODM_RF_CALIBRATION = BIT26, 450 451}; 452 453/* ODM_CMNINFO_INTERFACE */ 454enum odm_interface_def { 455 ODM_ITRF_PCIE = 0x1, 456 ODM_ITRF_USB = 0x2, 457 ODM_ITRF_SDIO = 0x4, 458 ODM_ITRF_ALL = 0x7, 459}; 460 461/* ODM_CMNINFO_IC_TYPE */ 462enum odm_ic_type_def { 463 ODM_RTL8192S = BIT0, 464 ODM_RTL8192C = BIT1, 465 ODM_RTL8192D = BIT2, 466 ODM_RTL8723A = BIT3, 467 ODM_RTL8188E = BIT4, 468 ODM_RTL8812 = BIT5, 469 ODM_RTL8821 = BIT6, 470}; 471 472#define ODM_IC_11N_SERIES \ 473 (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E) 474#define ODM_IC_11AC_SERIES (ODM_RTL8812) 475 476/* ODM_CMNINFO_CUT_VER */ 477enum odm_cut_version { 478 ODM_CUT_A = 1, 479 ODM_CUT_B = 2, 480 ODM_CUT_C = 3, 481 ODM_CUT_D = 4, 482 ODM_CUT_E = 5, 483 ODM_CUT_F = 6, 484 ODM_CUT_TEST = 7, 485}; 486 487/* ODM_CMNINFO_FAB_VER */ 488enum odm_fab_version { 489 ODM_TSMC = 0, 490 ODM_UMC = 1, 491}; 492 493/* ODM_CMNINFO_RF_TYPE */ 494/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 495enum rf_path_def { 496 ODM_RF_TX_A = BIT0, 497 ODM_RF_TX_B = BIT1, 498 ODM_RF_TX_C = BIT2, 499 ODM_RF_TX_D = BIT3, 500 ODM_RF_RX_A = BIT4, 501 ODM_RF_RX_B = BIT5, 502 ODM_RF_RX_C = BIT6, 503 ODM_RF_RX_D = BIT7, 504}; 505 506 507enum odm_rf_type { 508 ODM_1T1R = 0, 509 ODM_1T2R = 1, 510 ODM_2T2R = 2, 511 ODM_2T3R = 3, 512 ODM_2T4R = 4, 513 ODM_3T3R = 5, 514 ODM_3T4R = 6, 515 ODM_4T4R = 7, 516}; 517 518/* ODM Dynamic common info value definition */ 519 520enum odm_mac_phy_mode { 521 ODM_SMSP = 0, 522 ODM_DMSP = 1, 523 ODM_DMDP = 2, 524}; 525 526 527enum odm_bt_coexist { 528 ODM_BT_BUSY = 1, 529 ODM_BT_ON = 2, 530 ODM_BT_OFF = 3, 531 ODM_BT_NONE = 4, 532}; 533 534/* ODM_CMNINFO_OP_MODE */ 535enum odm_operation_mode { 536 ODM_NO_LINK = BIT0, 537 ODM_LINK = BIT1, 538 ODM_SCAN = BIT2, 539 ODM_POWERSAVE = BIT3, 540 ODM_AP_MODE = BIT4, 541 ODM_CLIENT_MODE = BIT5, 542 ODM_AD_HOC = BIT6, 543 ODM_WIFI_DIRECT = BIT7, 544 ODM_WIFI_DISPLAY = BIT8, 545}; 546 547/* ODM_CMNINFO_WM_MODE */ 548enum odm_wireless_mode { 549 ODM_WM_UNKNOW = 0x0, 550 ODM_WM_B = BIT0, 551 ODM_WM_G = BIT1, 552 ODM_WM_A = BIT2, 553 ODM_WM_N24G = BIT3, 554 ODM_WM_N5G = BIT4, 555 ODM_WM_AUTO = BIT5, 556 ODM_WM_AC = BIT6, 557}; 558 559/* ODM_CMNINFO_BAND */ 560enum odm_band_type { 561 ODM_BAND_2_4G = BIT0, 562 ODM_BAND_5G = BIT1, 563 564}; 565 566/* ODM_CMNINFO_SEC_CHNL_OFFSET */ 567enum odm_sec_chnl_offset { 568 ODM_DONT_CARE = 0, 569 ODM_BELOW = 1, 570 ODM_ABOVE = 2 571}; 572 573/* ODM_CMNINFO_SEC_MODE */ 574enum odm_security { 575 ODM_SEC_OPEN = 0, 576 ODM_SEC_WEP40 = 1, 577 ODM_SEC_TKIP = 2, 578 ODM_SEC_RESERVE = 3, 579 ODM_SEC_AESCCMP = 4, 580 ODM_SEC_WEP104 = 5, 581 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 582 ODM_SEC_SMS4 = 7, 583}; 584 585/* ODM_CMNINFO_BW */ 586enum odm_band_width { 587 ODM_BW20M = 0, 588 ODM_BW40M = 1, 589 ODM_BW80M = 2, 590 ODM_BW160M = 3, 591 ODM_BW10M = 4, 592}; 593 594/* ODM_CMNINFO_CHNL */ 595 596/* ODM_CMNINFO_BOARD_TYPE */ 597enum odm_board_type { 598 ODM_BOARD_NORMAL = 0, 599 ODM_BOARD_HIGHPWR = 1, 600 ODM_BOARD_MINICARD = 2, 601 ODM_BOARD_SLIM = 3, 602 ODM_BOARD_COMBO = 4, 603 604}; 605 606/* ODM_CMNINFO_ONE_PATH_CCA */ 607enum odm_cca_path { 608 ODM_CCA_2R = 0, 609 ODM_CCA_1R_A = 1, 610 ODM_CCA_1R_B = 2, 611}; 612 613struct odm_ra_info { 614 u8 RateID; 615 u32 RateMask; 616 u32 RAUseRate; 617 u8 RateSGI; 618 u8 RssiStaRA; 619 u8 PreRssiStaRA; 620 u8 SGIEnable; 621 u8 DecisionRate; 622 u8 PreRate; 623 u8 HighestRate; 624 u8 LowestRate; 625 u32 NscUp; 626 u32 NscDown; 627 u16 RTY[5]; 628 u32 TOTAL; 629 u16 DROP; 630 u8 Active; 631 u16 RptTime; 632 u8 RAWaitingCounter; 633 u8 RAPendingCounter; 634 u8 PTActive; /* on or off */ 635 u8 PTTryState; /* 0 trying state, 1 for decision state */ 636 u8 PTStage; /* 0~6 */ 637 u8 PTStopCount; /* Stop PT counter */ 638 u8 PTPreRate; /* if rate change do PT */ 639 u8 PTPreRssi; /* if RSSI change 5% do PT */ 640 u8 PTModeSS; /* decide whitch rate should do PT */ 641 u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ 642 u8 PTSmoothFactor; 643}; 644 645struct iqk_matrix_regs_set { 646 bool bIQKDone; 647 s32 Value[1][IQK_Matrix_REG_NUM]; 648}; 649 650struct odm_rf_cal_t { 651 /* for tx power tracking */ 652 653 u32 RegA24; /* for TempCCK */ 654 s32 RegE94; 655 s32 RegE9C; 656 s32 RegEB4; 657 s32 RegEBC; 658 659 /* u8 bTXPowerTracking; */ 660 u8 TXPowercount; 661 bool bTXPowerTrackingInit; 662 bool bTXPowerTracking; 663 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 664 u8 TM_Trigger; 665 u8 InternalPA5G[2]; /* pathA / pathB */ 666 667 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 668 u8 ThermalValue; 669 u8 ThermalValue_LCK; 670 u8 ThermalValue_IQK; 671 u8 ThermalValue_DPK; 672 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 673 u8 ThermalValue_AVG_index; 674 u8 ThermalValue_RxGain; 675 u8 ThermalValue_Crystal; 676 u8 ThermalValue_DPKstore; 677 u8 ThermalValue_DPKtrack; 678 bool TxPowerTrackingInProgress; 679 bool bDPKenable; 680 681 bool bReloadtxpowerindex; 682 u8 bRfPiEnable; 683 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 684 685 u8 bCCKinCH14; 686 u8 CCK_index; 687 u8 OFDM_index[2]; 688 bool bDoneTxpower; 689 690 u8 ThermalValue_HP[HP_THERMAL_NUM]; 691 u8 ThermalValue_HP_index; 692 struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 693 694 u8 Delta_IQK; 695 u8 Delta_LCK; 696 697 /* for IQK */ 698 u32 RegC04; 699 u32 Reg874; 700 u32 RegC08; 701 u32 RegB68; 702 u32 RegB6C; 703 u32 Reg870; 704 u32 Reg860; 705 u32 Reg864; 706 707 bool bIQKInitialized; 708 bool bLCKInProgress; 709 bool bAntennaDetected; 710 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 711 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 712 u32 IQK_BB_backup_recover[9]; 713 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 714 715 /* for APK */ 716 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 717 u8 bAPKdone; 718 u8 bAPKThermalMeterIgnore; 719 u8 bDPdone; 720 u8 bDPPathAOK; 721 u8 bDPPathBOK; 722}; 723 724/* ODM Dynamic common info value definition */ 725struct odm_fat_t { 726 u8 Bssid[6]; 727 u8 antsel_rx_keep_0; 728 u8 antsel_rx_keep_1; 729 u8 antsel_rx_keep_2; 730 u32 antSumRSSI[7]; 731 u32 antRSSIcnt[7]; 732 u32 antAveRSSI[7]; 733 u8 FAT_State; 734 u32 TrainIdx; 735 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 736 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 737 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 738 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 739 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 740 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 741 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 742 u8 RxIdleAnt; 743 bool bBecomeLinked; 744}; 745 746enum fat_state { 747 FAT_NORMAL_STATE = 0, 748 FAT_TRAINING_STATE = 1, 749}; 750 751enum ant_dif_type { 752 NO_ANTDIV = 0xFF, 753 CG_TRX_HW_ANTDIV = 0x01, 754 CGCS_RX_HW_ANTDIV = 0x02, 755 FIXED_HW_ANTDIV = 0x03, 756 CG_TRX_SMART_ANTDIV = 0x04, 757 CGCS_RX_SW_ANTDIV = 0x05, 758}; 759 760/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 761struct dm_odm_t { 762 /* */ 763 /* Add for different team use temporarily */ 764 /* */ 765 struct rtw_adapter *Adapter; /* For CE/NIC team */ 766 struct rtl8723a_priv *priv; /* For AP/ADSL team */ 767 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 768 bool odm_ready; 769 770 struct rtl8723a_priv fake_priv; 771 772 u64 DebugComponents; 773 u32 DebugLevel; 774 775/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 776 bool bCckHighPower; 777 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 778 u8 ControlChannel; 779/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 780 781/* 1 COMMON INFORMATION */ 782 783 /* Init Value */ 784/* HOOK BEFORE REG INIT----------- */ 785 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 786 u32 SupportAbility; 787 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ 788 u8 SupportInterface; 789 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 790 u32 SupportICType; 791 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 792 u8 CutVersion; 793 /* Fab Version TSMC/UMC = 0/1 */ 794 u8 FabVersion; 795 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 796 u8 RFType; 797 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 798 u8 BoardType; 799 /* with external LNA NO/Yes = 0/1 */ 800 u8 ExtLNA; 801 /* with external PA NO/Yes = 0/1 */ 802 u8 ExtPA; 803 /* with external TRSW NO/Yes = 0/1 */ 804 u8 ExtTRSW; 805 u8 PatchID; /* Customer ID */ 806 bool bInHctTest; 807 bool bWIFITest; 808 809 bool bDualMacSmartConcurrent; 810 u32 BK_SupportAbility; 811 u8 AntDivType; 812/* HOOK BEFORE REG INIT----------- */ 813 814 /* */ 815 /* Dynamic Value */ 816 /* */ 817/* POINTER REFERENCE----------- */ 818 819 u8 u8_temp; 820 bool bool_temp; 821 struct rtw_adapter *PADAPTER_temp; 822 823 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 824 u8 *pMacPhyMode; 825 /* TX Unicast byte count */ 826 u64 *pNumTxBytesUnicast; 827 /* RX Unicast byte count */ 828 u64 *pNumRxBytesUnicast; 829 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 830 u8 *pWirelessMode; /* enum odm_wireless_mode */ 831 /* Frequence band 2.4G/5G = 0/1 */ 832 u8 *pBandType; 833 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 834 u8 *pSecChOffset; 835 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 836 u8 *pSecurity; 837 /* BW info 20M/40M/80M = 0/1/2 */ 838 u8 *pBandWidth; 839 /* Central channel location Ch1/Ch2/.... */ 840 u8 *pChannel; /* central channel number */ 841 /* Common info for 92D DMSP */ 842 843 bool *pbGetValueFromOtherMac; 844 struct rtw_adapter **pBuddyAdapter; 845 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 846 /* Common info for Status */ 847 bool *pbScanInProcess; 848 bool *pbPowerSaving; 849 /* CCA Path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path. */ 850 u8 *pOnePathCCA; 851 /* pMgntInfo->AntennaTest */ 852 u8 *pAntennaTest; 853 bool *pbNet_closed; 854/* POINTER REFERENCE----------- */ 855 /* */ 856/* CALL BY VALUE------------- */ 857 bool bWIFI_Direct; 858 bool bWIFI_Display; 859 bool bLinked; 860 u8 RSSI_Min; 861 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 862 bool bIsMPChip; 863 bool bOneEntryOnly; 864 /* Common info for BTDM */ 865 bool bBtDisabled; /* BT is disabled */ 866 bool bBtHsOperation; /* BT HS mode is under progress */ 867 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 868 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 869 bool bBtBusy; /* BT is busy. */ 870/* CALL BY VALUE------------- */ 871 872 /* 2 Define STA info. */ 873 /* _ODM_STA_INFO */ 874 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 875 struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 876 877 /* */ 878 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 879 /* We need to colelct all support abilit to a proper area. */ 880 /* */ 881 bool RaSupport88E; 882 883 /* Define ........... */ 884 885 /* Latest packet phy info (ODM write) */ 886 struct odm_phy_dbg_info PhyDbgInfo; 887 /* PHY_INFO_88E PhyInfo; */ 888 889 /* Latest packet phy info (ODM write) */ 890 struct odm_mac_info *pMacInfo; 891 /* MAC_INFO_88E MacInfo; */ 892 893 /* Different Team independt structure?? */ 894 895 /* */ 896 /* TX_RTP_CMN TX_retrpo; */ 897 /* TX_RTP_88E TX_retrpo; */ 898 /* TX_RTP_8195 TX_retrpo; */ 899 900 /* */ 901 /* ODM Structure */ 902 /* */ 903 struct odm_fat_t DM_FatTable; 904 struct dig_t DM_DigTable; 905 struct dynamic_pwr_sav DM_PSTable; 906 struct pri_cca DM_PriCCA; 907 struct rx_hp DM_RXHP_Table; 908 struct false_alarm_stats FalseAlmCnt; 909 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 910 struct sw_ant_sw DM_SWAT_Table; 911 bool RSSI_test; 912 913 struct edca_turbo DM_EDCA_Table; 914 u32 WMMEDCA_BE; 915 /* Copy from SD4 structure */ 916 /* */ 917 /* ================================================== */ 918 /* */ 919 920 /* common */ 921 bool *pbDriverStopped; 922 bool *pbDriverIsGoingToPnpSetPowerSleep; 923 bool *pinit_adpt_in_progress; 924 925 /* PSD */ 926 bool bUserAssignLevel; 927 u8 RSSI_BT; /* come from BT */ 928 bool bPSDinProcess; 929 bool bDMInitialGainEnable; 930 931 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 932 u8 bUseRAMask; 933 934 struct odm_rate_adapt RateAdaptive; 935 936 937 struct odm_rf_cal_t RFCalibrateInfo; 938 939 /* */ 940 /* TX power tracking */ 941 /* */ 942 u8 BbSwingIdxOfdm; 943 u8 BbSwingIdxOfdmCurrent; 944 u8 BbSwingIdxOfdmBase; 945 bool BbSwingFlagOfdm; 946 u8 BbSwingIdxCck; 947 u8 BbSwingIdxCckCurrent; 948 u8 BbSwingIdxCckBase; 949 bool BbSwingFlagCck; 950 /* */ 951 /* ODM system resource. */ 952 /* */ 953}; /* DM_Dynamic_Mechanism_Structure */ 954 955enum odm_rf_content { 956 odm_radioa_txt = 0x1000, 957 odm_radiob_txt = 0x1001, 958 odm_radioc_txt = 0x1002, 959 odm_radiod_txt = 0x1003 960}; 961 962enum odm_bb_config_type { 963 CONFIG_BB_PHY_REG, 964 CONFIG_BB_AGC_TAB, 965 CONFIG_BB_AGC_TAB_2G, 966 CONFIG_BB_AGC_TAB_5G, 967 CONFIG_BB_PHY_REG_PG, 968}; 969 970/* Status code */ 971enum rt_status { 972 RT_STATUS_SUCCESS, 973 RT_STATUS_FAILURE, 974 RT_STATUS_PENDING, 975 RT_STATUS_RESOURCE, 976 RT_STATUS_INVALID_CONTEXT, 977 RT_STATUS_INVALID_PARAMETER, 978 RT_STATUS_NOT_SUPPORT, 979 RT_STATUS_OS_API_FAILED, 980}; 981 982/* include "odm_function.h" */ 983 984/* 3=========================================================== */ 985/* 3 DIG */ 986/* 3=========================================================== */ 987 988enum dm_dig_op { 989 DIG_TYPE_THRESH_HIGH = 0, 990 DIG_TYPE_THRESH_LOW = 1, 991 DIG_TYPE_BACKOFF = 2, 992 DIG_TYPE_RX_GAIN_MIN = 3, 993 DIG_TYPE_RX_GAIN_MAX = 4, 994 DIG_TYPE_ENABLE = 5, 995 DIG_TYPE_DISABLE = 6, 996 DIG_OP_TYPE_MAX 997}; 998 999#define DM_DIG_THRESH_HIGH 40 1000#define DM_DIG_THRESH_LOW 35 1001 1002#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ 1003 1004 1005#define DM_FALSEALARM_THRESH_LOW 400 1006#define DM_FALSEALARM_THRESH_HIGH 1000 1007 1008#define DM_DIG_MAX_NIC 0x4e 1009#define DM_DIG_MIN_NIC 0x1e 1010 1011#define DM_DIG_MAX_AP 0x32 1012#define DM_DIG_MIN_AP 0x20 1013 1014#define DM_DIG_MAX_NIC_HP 0x46 1015#define DM_DIG_MIN_NIC_HP 0x2e 1016 1017#define DM_DIG_MAX_AP_HP 0x42 1018#define DM_DIG_MIN_AP_HP 0x30 1019 1020/* vivi 92c&92d has different definition, 20110504 */ 1021/* this is for 92c */ 1022#define DM_DIG_FA_TH0 0x200 1023#define DM_DIG_FA_TH1 0x300 1024#define DM_DIG_FA_TH2 0x400 1025/* this is for 92d */ 1026#define DM_DIG_FA_TH0_92D 0x100 1027#define DM_DIG_FA_TH1_92D 0x400 1028#define DM_DIG_FA_TH2_92D 0x600 1029 1030#define DM_DIG_BACKOFF_MAX 12 1031#define DM_DIG_BACKOFF_MIN -4 1032#define DM_DIG_BACKOFF_DEFAULT 10 1033 1034/* 3=========================================================== */ 1035/* 3 AGC RX High Power Mode */ 1036/* 3=========================================================== */ 1037#define LNA_Low_Gain_1 0x64 1038#define LNA_Low_Gain_2 0x5A 1039#define LNA_Low_Gain_3 0x58 1040 1041#define FA_RXHP_TH1 5000 1042#define FA_RXHP_TH2 1500 1043#define FA_RXHP_TH3 800 1044#define FA_RXHP_TH4 600 1045#define FA_RXHP_TH5 500 1046 1047/* 3=========================================================== */ 1048/* 3 EDCA */ 1049/* 3=========================================================== */ 1050 1051/* 3=========================================================== */ 1052/* 3 Dynamic Tx Power */ 1053/* 3=========================================================== */ 1054/* Dynamic Tx Power Control Threshold */ 1055#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 1056#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 1057#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 1058 1059#define TxHighPwrLevel_Normal 0 1060#define TxHighPwrLevel_Level1 1 1061#define TxHighPwrLevel_Level2 2 1062#define TxHighPwrLevel_BT1 3 1063#define TxHighPwrLevel_BT2 4 1064#define TxHighPwrLevel_15 5 1065#define TxHighPwrLevel_35 6 1066#define TxHighPwrLevel_50 7 1067#define TxHighPwrLevel_70 8 1068#define TxHighPwrLevel_100 9 1069 1070/* 3=========================================================== */ 1071/* 3 Rate Adaptive */ 1072/* 3=========================================================== */ 1073#define DM_RATR_STA_INIT 0 1074#define DM_RATR_STA_HIGH 1 1075#define DM_RATR_STA_MIDDLE 2 1076#define DM_RATR_STA_LOW 3 1077 1078/* 3=========================================================== */ 1079/* 3 BB Power Save */ 1080/* 3=========================================================== */ 1081 1082 1083enum dm_1r_cca { 1084 CCA_1R =0, 1085 CCA_2R = 1, 1086 CCA_MAX = 2, 1087}; 1088 1089enum dm_rf_def { 1090 RF_Save =0, 1091 RF_Normal = 1, 1092 RF_MAX = 2, 1093}; 1094 1095/* 3=========================================================== */ 1096/* 3 Antenna Diversity */ 1097/* 3=========================================================== */ 1098enum dm_swas { 1099 Antenna_A = 1, 1100 Antenna_B = 2, 1101 Antenna_MAX = 3, 1102}; 1103 1104/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1105#define MAX_ANTENNA_DETECTION_CNT 10 1106 1107/* */ 1108/* Extern Global Variables. */ 1109/* */ 1110#define OFDM_TABLE_SIZE_92C 37 1111#define OFDM_TABLE_SIZE_92D 43 1112#define CCK_TABLE_SIZE 33 1113 1114extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D]; 1115extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8]; 1116extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8]; 1117 1118 1119 1120/* */ 1121/* check Sta pointer valid or not */ 1122/* */ 1123#define IS_STA_VALID(pSta) (pSta) 1124/* 20100514 Joseph: Add definition for antenna switching test after link. */ 1125/* This indicates two different the steps. */ 1126/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1127/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1128/* with original RSSI to determine if it is necessary to switch antenna. */ 1129#define SWAW_STEP_PEAK 0 1130#define SWAW_STEP_DETERMINE 1 1131 1132void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI); 1133void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres); 1134 1135void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna); 1136 1137 1138#define dm_RF_Saving ODM_RF_Saving23a 1139void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal); 1140 1141#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink 1142void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm); 1143 1144#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a 1145void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm); 1146 1147bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate, 1148 u8 *pRATRState); 1149 1150 1151#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1152void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID, 1153 struct odm_phy_info *pPhyInfo); 1154 1155u32 ConvertTo_dB23a(u32 Value); 1156 1157u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd); 1158 1159void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm); 1160 1161u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level); 1162 1163 1164void ODM23a_DMInit(struct dm_odm_t *pDM_Odm); 1165 1166void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1167 1168void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value); 1169 1170void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, void *pValue); 1171 1172void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue); 1173 1174void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1175 1176void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm); 1177 1178void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate); 1179 1180void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm); 1181 1182bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode); 1183 1184void odm_dtc(struct dm_odm_t *pDM_Odm); 1185 1186#endif 1187