1/* 2 * pinmux driver for CSR SiRFprimaII 3 * 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group 5 * company. 6 * 7 * Licensed under GPLv2 or later. 8 */ 9 10#include <linux/init.h> 11#include <linux/module.h> 12#include <linux/irq.h> 13#include <linux/platform_device.h> 14#include <linux/io.h> 15#include <linux/slab.h> 16#include <linux/err.h> 17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinmux.h> 19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/machine.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/of_device.h> 24#include <linux/of_platform.h> 25#include <linux/bitops.h> 26#include <linux/gpio.h> 27#include <linux/of_gpio.h> 28 29#include "pinctrl-sirf.h" 30 31#define DRIVER_NAME "pinmux-sirf" 32 33struct sirfsoc_gpio_bank { 34 int id; 35 int parent_irq; 36 spinlock_t lock; 37}; 38 39struct sirfsoc_gpio_chip { 40 struct of_mm_gpio_chip chip; 41 bool is_marco; /* for marco, some registers are different with prima2 */ 42 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; 43}; 44 45static DEFINE_SPINLOCK(sgpio_lock); 46 47static struct sirfsoc_pin_group *sirfsoc_pin_groups; 48static int sirfsoc_pingrp_cnt; 49 50static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) 51{ 52 return sirfsoc_pingrp_cnt; 53} 54 55static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, 56 unsigned selector) 57{ 58 return sirfsoc_pin_groups[selector].name; 59} 60 61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, 62 unsigned selector, 63 const unsigned **pins, 64 unsigned *num_pins) 65{ 66 *pins = sirfsoc_pin_groups[selector].pins; 67 *num_pins = sirfsoc_pin_groups[selector].num_pins; 68 return 0; 69} 70 71static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, 72 struct seq_file *s, unsigned offset) 73{ 74 seq_printf(s, " " DRIVER_NAME); 75} 76 77static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, 78 struct device_node *np_config, 79 struct pinctrl_map **map, unsigned *num_maps) 80{ 81 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); 82 struct device_node *np; 83 struct property *prop; 84 const char *function, *group; 85 int ret, index = 0, count = 0; 86 87 /* calculate number of maps required */ 88 for_each_child_of_node(np_config, np) { 89 ret = of_property_read_string(np, "sirf,function", &function); 90 if (ret < 0) 91 return ret; 92 93 ret = of_property_count_strings(np, "sirf,pins"); 94 if (ret < 0) 95 return ret; 96 97 count += ret; 98 } 99 100 if (!count) { 101 dev_err(spmx->dev, "No child nodes passed via DT\n"); 102 return -ENODEV; 103 } 104 105 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); 106 if (!*map) 107 return -ENOMEM; 108 109 for_each_child_of_node(np_config, np) { 110 of_property_read_string(np, "sirf,function", &function); 111 of_property_for_each_string(np, "sirf,pins", prop, group) { 112 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; 113 (*map)[index].data.mux.group = group; 114 (*map)[index].data.mux.function = function; 115 index++; 116 } 117 } 118 119 *num_maps = count; 120 121 return 0; 122} 123 124static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, 125 struct pinctrl_map *map, unsigned num_maps) 126{ 127 kfree(map); 128} 129 130static struct pinctrl_ops sirfsoc_pctrl_ops = { 131 .get_groups_count = sirfsoc_get_groups_count, 132 .get_group_name = sirfsoc_get_group_name, 133 .get_group_pins = sirfsoc_get_group_pins, 134 .pin_dbg_show = sirfsoc_pin_dbg_show, 135 .dt_node_to_map = sirfsoc_dt_node_to_map, 136 .dt_free_map = sirfsoc_dt_free_map, 137}; 138 139static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; 140static int sirfsoc_pmxfunc_cnt; 141 142static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, 143 unsigned selector, bool enable) 144{ 145 int i; 146 const struct sirfsoc_padmux *mux = 147 sirfsoc_pmx_functions[selector].padmux; 148 const struct sirfsoc_muxmask *mask = mux->muxmask; 149 150 for (i = 0; i < mux->muxmask_counts; i++) { 151 u32 muxval; 152 if (!spmx->is_marco) { 153 muxval = readl(spmx->gpio_virtbase + 154 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 155 if (enable) 156 muxval = muxval & ~mask[i].mask; 157 else 158 muxval = muxval | mask[i].mask; 159 writel(muxval, spmx->gpio_virtbase + 160 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 161 } else { 162 if (enable) 163 writel(mask[i].mask, spmx->gpio_virtbase + 164 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); 165 else 166 writel(mask[i].mask, spmx->gpio_virtbase + 167 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 168 } 169 } 170 171 if (mux->funcmask && enable) { 172 u32 func_en_val; 173 174 func_en_val = 175 readl(spmx->rsc_virtbase + mux->ctrlreg); 176 func_en_val = 177 (func_en_val & ~mux->funcmask) | (mux->funcval); 178 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); 179 } 180} 181 182static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev, 183 unsigned selector, 184 unsigned group) 185{ 186 struct sirfsoc_pmx *spmx; 187 188 spmx = pinctrl_dev_get_drvdata(pmxdev); 189 sirfsoc_pinmux_endisable(spmx, selector, true); 190 191 return 0; 192} 193 194static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) 195{ 196 return sirfsoc_pmxfunc_cnt; 197} 198 199static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, 200 unsigned selector) 201{ 202 return sirfsoc_pmx_functions[selector].name; 203} 204 205static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, 206 unsigned selector, 207 const char * const **groups, 208 unsigned * const num_groups) 209{ 210 *groups = sirfsoc_pmx_functions[selector].groups; 211 *num_groups = sirfsoc_pmx_functions[selector].num_groups; 212 return 0; 213} 214 215static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, 216 struct pinctrl_gpio_range *range, unsigned offset) 217{ 218 struct sirfsoc_pmx *spmx; 219 220 int group = range->id; 221 222 u32 muxval; 223 224 spmx = pinctrl_dev_get_drvdata(pmxdev); 225 226 if (!spmx->is_marco) { 227 muxval = readl(spmx->gpio_virtbase + 228 SIRFSOC_GPIO_PAD_EN(group)); 229 muxval = muxval | (1 << (offset - range->pin_base)); 230 writel(muxval, spmx->gpio_virtbase + 231 SIRFSOC_GPIO_PAD_EN(group)); 232 } else { 233 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + 234 SIRFSOC_GPIO_PAD_EN(group)); 235 } 236 237 return 0; 238} 239 240static struct pinmux_ops sirfsoc_pinmux_ops = { 241 .set_mux = sirfsoc_pinmux_set_mux, 242 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 243 .get_function_name = sirfsoc_pinmux_get_func_name, 244 .get_function_groups = sirfsoc_pinmux_get_groups, 245 .gpio_request_enable = sirfsoc_pinmux_request_gpio, 246}; 247 248static struct pinctrl_desc sirfsoc_pinmux_desc = { 249 .name = DRIVER_NAME, 250 .pctlops = &sirfsoc_pctrl_ops, 251 .pmxops = &sirfsoc_pinmux_ops, 252 .owner = THIS_MODULE, 253}; 254 255static void __iomem *sirfsoc_rsc_of_iomap(void) 256{ 257 const struct of_device_id rsc_ids[] = { 258 { .compatible = "sirf,prima2-rsc" }, 259 { .compatible = "sirf,marco-rsc" }, 260 {} 261 }; 262 struct device_node *np; 263 264 np = of_find_matching_node(NULL, rsc_ids); 265 if (!np) 266 panic("unable to find compatible rsc node in dtb\n"); 267 268 return of_iomap(np, 0); 269} 270 271static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, 272 const struct of_phandle_args *gpiospec, 273 u32 *flags) 274{ 275 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) 276 return -EINVAL; 277 278 if (flags) 279 *flags = gpiospec->args[1]; 280 281 return gpiospec->args[0]; 282} 283 284static const struct of_device_id pinmux_ids[] = { 285 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, 286 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, 287 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, }, 288 {} 289}; 290 291static int sirfsoc_pinmux_probe(struct platform_device *pdev) 292{ 293 int ret; 294 struct sirfsoc_pmx *spmx; 295 struct device_node *np = pdev->dev.of_node; 296 const struct sirfsoc_pinctrl_data *pdata; 297 298 /* Create state holders etc for this driver */ 299 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); 300 if (!spmx) 301 return -ENOMEM; 302 303 spmx->dev = &pdev->dev; 304 305 platform_set_drvdata(pdev, spmx); 306 307 spmx->gpio_virtbase = of_iomap(np, 0); 308 if (!spmx->gpio_virtbase) { 309 dev_err(&pdev->dev, "can't map gpio registers\n"); 310 return -ENOMEM; 311 } 312 313 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); 314 if (!spmx->rsc_virtbase) { 315 ret = -ENOMEM; 316 dev_err(&pdev->dev, "can't map rsc registers\n"); 317 goto out_no_rsc_remap; 318 } 319 320 if (of_device_is_compatible(np, "sirf,marco-pinctrl")) 321 spmx->is_marco = 1; 322 323 pdata = of_match_node(pinmux_ids, np)->data; 324 sirfsoc_pin_groups = pdata->grps; 325 sirfsoc_pingrp_cnt = pdata->grps_cnt; 326 sirfsoc_pmx_functions = pdata->funcs; 327 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; 328 sirfsoc_pinmux_desc.pins = pdata->pads; 329 sirfsoc_pinmux_desc.npins = pdata->pads_cnt; 330 331 332 /* Now register the pin controller and all pins it handles */ 333 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); 334 if (!spmx->pmx) { 335 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); 336 ret = -EINVAL; 337 goto out_no_pmx; 338 } 339 340 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); 341 342 return 0; 343 344out_no_pmx: 345 iounmap(spmx->rsc_virtbase); 346out_no_rsc_remap: 347 iounmap(spmx->gpio_virtbase); 348 return ret; 349} 350 351#ifdef CONFIG_PM_SLEEP 352static int sirfsoc_pinmux_suspend_noirq(struct device *dev) 353{ 354 int i, j; 355 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); 356 357 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 358 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { 359 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + 360 SIRFSOC_GPIO_CTRL(i, j)); 361 } 362 spmx->ints_regs[i] = readl(spmx->gpio_virtbase + 363 SIRFSOC_GPIO_INT_STATUS(i)); 364 spmx->paden_regs[i] = readl(spmx->gpio_virtbase + 365 SIRFSOC_GPIO_PAD_EN(i)); 366 } 367 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); 368 369 for (i = 0; i < 3; i++) 370 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); 371 372 return 0; 373} 374 375static int sirfsoc_pinmux_resume_noirq(struct device *dev) 376{ 377 int i, j; 378 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); 379 380 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 381 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { 382 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + 383 SIRFSOC_GPIO_CTRL(i, j)); 384 } 385 writel(spmx->ints_regs[i], spmx->gpio_virtbase + 386 SIRFSOC_GPIO_INT_STATUS(i)); 387 writel(spmx->paden_regs[i], spmx->gpio_virtbase + 388 SIRFSOC_GPIO_PAD_EN(i)); 389 } 390 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); 391 392 for (i = 0; i < 3; i++) 393 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); 394 395 return 0; 396} 397 398static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { 399 .suspend_noirq = sirfsoc_pinmux_suspend_noirq, 400 .resume_noirq = sirfsoc_pinmux_resume_noirq, 401 .freeze_noirq = sirfsoc_pinmux_suspend_noirq, 402 .restore_noirq = sirfsoc_pinmux_resume_noirq, 403}; 404#endif 405 406static struct platform_driver sirfsoc_pinmux_driver = { 407 .driver = { 408 .name = DRIVER_NAME, 409 .owner = THIS_MODULE, 410 .of_match_table = pinmux_ids, 411#ifdef CONFIG_PM_SLEEP 412 .pm = &sirfsoc_pinmux_pm_ops, 413#endif 414 }, 415 .probe = sirfsoc_pinmux_probe, 416}; 417 418static int __init sirfsoc_pinmux_init(void) 419{ 420 return platform_driver_register(&sirfsoc_pinmux_driver); 421} 422arch_initcall(sirfsoc_pinmux_init); 423 424static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc) 425{ 426 return container_of(gc, struct sirfsoc_gpio_chip, chip.gc); 427} 428 429static inline struct sirfsoc_gpio_bank * 430sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) 431{ 432 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; 433} 434 435static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) 436{ 437 return offset % SIRFSOC_GPIO_BANK_SIZE; 438} 439 440static void sirfsoc_gpio_irq_ack(struct irq_data *d) 441{ 442 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 443 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 444 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 445 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 446 u32 val, offset; 447 unsigned long flags; 448 449 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 450 451 spin_lock_irqsave(&sgpio_lock, flags); 452 453 val = readl(sgpio->chip.regs + offset); 454 455 writel(val, sgpio->chip.regs + offset); 456 457 spin_unlock_irqrestore(&sgpio_lock, flags); 458} 459 460static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, 461 struct sirfsoc_gpio_bank *bank, 462 int idx) 463{ 464 u32 val, offset; 465 unsigned long flags; 466 467 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 468 469 spin_lock_irqsave(&sgpio_lock, flags); 470 471 val = readl(sgpio->chip.regs + offset); 472 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 473 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 474 writel(val, sgpio->chip.regs + offset); 475 476 spin_unlock_irqrestore(&sgpio_lock, flags); 477} 478 479static void sirfsoc_gpio_irq_mask(struct irq_data *d) 480{ 481 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 482 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 483 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 484 485 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); 486} 487 488static void sirfsoc_gpio_irq_unmask(struct irq_data *d) 489{ 490 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 491 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 492 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 493 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 494 u32 val, offset; 495 unsigned long flags; 496 497 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 498 499 spin_lock_irqsave(&sgpio_lock, flags); 500 501 val = readl(sgpio->chip.regs + offset); 502 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 503 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; 504 writel(val, sgpio->chip.regs + offset); 505 506 spin_unlock_irqrestore(&sgpio_lock, flags); 507} 508 509static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) 510{ 511 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 512 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 513 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 514 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 515 u32 val, offset; 516 unsigned long flags; 517 518 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 519 520 spin_lock_irqsave(&sgpio_lock, flags); 521 522 val = readl(sgpio->chip.regs + offset); 523 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); 524 525 switch (type) { 526 case IRQ_TYPE_NONE: 527 break; 528 case IRQ_TYPE_EDGE_RISING: 529 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 531 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 532 break; 533 case IRQ_TYPE_EDGE_FALLING: 534 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 535 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 536 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 537 break; 538 case IRQ_TYPE_EDGE_BOTH: 539 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 540 SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 541 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 542 break; 543 case IRQ_TYPE_LEVEL_LOW: 544 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 545 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 546 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 547 break; 548 case IRQ_TYPE_LEVEL_HIGH: 549 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 550 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 551 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 552 break; 553 } 554 555 writel(val, sgpio->chip.regs + offset); 556 557 spin_unlock_irqrestore(&sgpio_lock, flags); 558 559 return 0; 560} 561 562static struct irq_chip sirfsoc_irq_chip = { 563 .name = "sirf-gpio-irq", 564 .irq_ack = sirfsoc_gpio_irq_ack, 565 .irq_mask = sirfsoc_gpio_irq_mask, 566 .irq_unmask = sirfsoc_gpio_irq_unmask, 567 .irq_set_type = sirfsoc_gpio_irq_type, 568}; 569 570static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) 571{ 572 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 573 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 574 struct sirfsoc_gpio_bank *bank; 575 u32 status, ctrl; 576 int idx = 0; 577 struct irq_chip *chip = irq_get_chip(irq); 578 int i; 579 580 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 581 bank = &sgpio->sgpio_bank[i]; 582 if (bank->parent_irq == irq) 583 break; 584 } 585 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); 586 587 chained_irq_enter(chip, desc); 588 589 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); 590 if (!status) { 591 printk(KERN_WARNING 592 "%s: gpio id %d status %#x no interrupt is flaged\n", 593 __func__, bank->id, status); 594 handle_bad_irq(irq, desc); 595 return; 596 } 597 598 while (status) { 599 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); 600 601 /* 602 * Here we must check whether the corresponding GPIO's interrupt 603 * has been enabled, otherwise just skip it 604 */ 605 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { 606 pr_debug("%s: gpio id %d idx %d happens\n", 607 __func__, bank->id, idx); 608 generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + 609 bank->id * SIRFSOC_GPIO_BANK_SIZE)); 610 } 611 612 idx++; 613 status = status >> 1; 614 } 615 616 chained_irq_exit(chip, desc); 617} 618 619static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, 620 unsigned ctrl_offset) 621{ 622 u32 val; 623 624 val = readl(sgpio->chip.regs + ctrl_offset); 625 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; 626 writel(val, sgpio->chip.regs + ctrl_offset); 627} 628 629static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) 630{ 631 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 632 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 633 unsigned long flags; 634 635 if (pinctrl_request_gpio(chip->base + offset)) 636 return -ENODEV; 637 638 spin_lock_irqsave(&bank->lock, flags); 639 640 /* 641 * default status: 642 * set direction as input and mask irq 643 */ 644 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); 645 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); 646 647 spin_unlock_irqrestore(&bank->lock, flags); 648 649 return 0; 650} 651 652static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) 653{ 654 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 655 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 656 unsigned long flags; 657 658 spin_lock_irqsave(&bank->lock, flags); 659 660 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); 661 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); 662 663 spin_unlock_irqrestore(&bank->lock, flags); 664 665 pinctrl_free_gpio(chip->base + offset); 666} 667 668static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 669{ 670 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 671 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 672 int idx = sirfsoc_gpio_to_bankoff(gpio); 673 unsigned long flags; 674 unsigned offset; 675 676 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 677 678 spin_lock_irqsave(&bank->lock, flags); 679 680 sirfsoc_gpio_set_input(sgpio, offset); 681 682 spin_unlock_irqrestore(&bank->lock, flags); 683 684 return 0; 685} 686 687static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, 688 struct sirfsoc_gpio_bank *bank, 689 unsigned offset, 690 int value) 691{ 692 u32 out_ctrl; 693 unsigned long flags; 694 695 spin_lock_irqsave(&bank->lock, flags); 696 697 out_ctrl = readl(sgpio->chip.regs + offset); 698 if (value) 699 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 700 else 701 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 702 703 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 704 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; 705 writel(out_ctrl, sgpio->chip.regs + offset); 706 707 spin_unlock_irqrestore(&bank->lock, flags); 708} 709 710static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, 711 unsigned gpio, int value) 712{ 713 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 714 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 715 int idx = sirfsoc_gpio_to_bankoff(gpio); 716 u32 offset; 717 unsigned long flags; 718 719 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 720 721 spin_lock_irqsave(&sgpio_lock, flags); 722 723 sirfsoc_gpio_set_output(sgpio, bank, offset, value); 724 725 spin_unlock_irqrestore(&sgpio_lock, flags); 726 727 return 0; 728} 729 730static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) 731{ 732 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 733 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 734 u32 val; 735 unsigned long flags; 736 737 spin_lock_irqsave(&bank->lock, flags); 738 739 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 740 741 spin_unlock_irqrestore(&bank->lock, flags); 742 743 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); 744} 745 746static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, 747 int value) 748{ 749 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 750 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 751 u32 ctrl; 752 unsigned long flags; 753 754 spin_lock_irqsave(&bank->lock, flags); 755 756 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 757 if (value) 758 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 759 else 760 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 761 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 762 763 spin_unlock_irqrestore(&bank->lock, flags); 764} 765 766static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, 767 const u32 *pullups) 768{ 769 int i, n; 770 const unsigned long *p = (const unsigned long *)pullups; 771 772 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 773 for_each_set_bit(n, p + i, BITS_PER_LONG) { 774 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 775 u32 val = readl(sgpio->chip.regs + offset); 776 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 777 val |= SIRFSOC_GPIO_CTL_PULL_HIGH; 778 writel(val, sgpio->chip.regs + offset); 779 } 780 } 781} 782 783static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, 784 const u32 *pulldowns) 785{ 786 int i, n; 787 const unsigned long *p = (const unsigned long *)pulldowns; 788 789 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 790 for_each_set_bit(n, p + i, BITS_PER_LONG) { 791 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 792 u32 val = readl(sgpio->chip.regs + offset); 793 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 794 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; 795 writel(val, sgpio->chip.regs + offset); 796 } 797 } 798} 799 800static int sirfsoc_gpio_probe(struct device_node *np) 801{ 802 int i, err = 0; 803 static struct sirfsoc_gpio_chip *sgpio; 804 struct sirfsoc_gpio_bank *bank; 805 void __iomem *regs; 806 struct platform_device *pdev; 807 bool is_marco = false; 808 809 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; 810 811 pdev = of_find_device_by_node(np); 812 if (!pdev) 813 return -ENODEV; 814 815 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); 816 if (!sgpio) 817 return -ENOMEM; 818 819 regs = of_iomap(np, 0); 820 if (!regs) 821 return -ENOMEM; 822 823 if (of_device_is_compatible(np, "sirf,marco-pinctrl")) 824 is_marco = 1; 825 826 sgpio->chip.gc.request = sirfsoc_gpio_request; 827 sgpio->chip.gc.free = sirfsoc_gpio_free; 828 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; 829 sgpio->chip.gc.get = sirfsoc_gpio_get_value; 830 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; 831 sgpio->chip.gc.set = sirfsoc_gpio_set_value; 832 sgpio->chip.gc.base = 0; 833 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; 834 sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); 835 sgpio->chip.gc.of_node = np; 836 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; 837 sgpio->chip.gc.of_gpio_n_cells = 2; 838 sgpio->chip.gc.dev = &pdev->dev; 839 sgpio->chip.regs = regs; 840 sgpio->is_marco = is_marco; 841 842 err = gpiochip_add(&sgpio->chip.gc); 843 if (err) { 844 dev_err(&pdev->dev, "%s: error in probe function with status %d\n", 845 np->full_name, err); 846 goto out; 847 } 848 849 err = gpiochip_irqchip_add(&sgpio->chip.gc, 850 &sirfsoc_irq_chip, 851 0, handle_level_irq, 852 IRQ_TYPE_NONE); 853 if (err) { 854 dev_err(&pdev->dev, 855 "could not connect irqchip to gpiochip\n"); 856 goto out_banks; 857 } 858 859 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 860 bank = &sgpio->sgpio_bank[i]; 861 spin_lock_init(&bank->lock); 862 bank->parent_irq = platform_get_irq(pdev, i); 863 if (bank->parent_irq < 0) { 864 err = bank->parent_irq; 865 goto out_banks; 866 } 867 868 gpiochip_set_chained_irqchip(&sgpio->chip.gc, 869 &sirfsoc_irq_chip, 870 bank->parent_irq, 871 sirfsoc_gpio_handle_irq); 872 } 873 874 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), 875 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); 876 if (err) { 877 dev_err(&pdev->dev, 878 "could not add gpiochip pin range\n"); 879 goto out_no_range; 880 } 881 882 if (!of_property_read_u32_array(np, "sirf,pullups", pullups, 883 SIRFSOC_GPIO_NO_OF_BANKS)) 884 sirfsoc_gpio_set_pullup(sgpio, pullups); 885 886 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, 887 SIRFSOC_GPIO_NO_OF_BANKS)) 888 sirfsoc_gpio_set_pulldown(sgpio, pulldowns); 889 890 return 0; 891 892out_no_range: 893out_banks: 894 gpiochip_remove(&sgpio->chip.gc); 895out: 896 iounmap(regs); 897 return err; 898} 899 900static int __init sirfsoc_gpio_init(void) 901{ 902 903 struct device_node *np; 904 905 np = of_find_matching_node(NULL, pinmux_ids); 906 907 if (!np) 908 return -ENODEV; 909 910 return sirfsoc_gpio_probe(np); 911} 912subsys_initcall(sirfsoc_gpio_init); 913 914MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>"); 915MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>"); 916MODULE_AUTHOR("Barry Song <baohua.song@csr.com>"); 917MODULE_DESCRIPTION("SIRFSOC pin control driver"); 918MODULE_LICENSE("GPL"); 919