1/** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#ifndef __DRIVERS_USB_DWC3_CORE_H 20#define __DRIVERS_USB_DWC3_CORE_H 21 22#include <linux/device.h> 23#include <linux/spinlock.h> 24#include <linux/ioport.h> 25#include <linux/list.h> 26#include <linux/dma-mapping.h> 27#include <linux/mm.h> 28#include <linux/debugfs.h> 29 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32#include <linux/usb/otg.h> 33 34#include <linux/phy/phy.h> 35 36#define DWC3_MSG_MAX 500 37 38/* Global constants */ 39#define DWC3_EP0_BOUNCE_SIZE 512 40#define DWC3_ENDPOINTS_NUM 32 41#define DWC3_XHCI_RESOURCES_NUM 2 42 43#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 44#define DWC3_EVENT_SIZE 4 /* bytes */ 45#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 46#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 47#define DWC3_EVENT_TYPE_MASK 0xfe 48 49#define DWC3_EVENT_TYPE_DEV 0 50#define DWC3_EVENT_TYPE_CARKIT 3 51#define DWC3_EVENT_TYPE_I2C 4 52 53#define DWC3_DEVICE_EVENT_DISCONNECT 0 54#define DWC3_DEVICE_EVENT_RESET 1 55#define DWC3_DEVICE_EVENT_CONNECT_DONE 2 56#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 57#define DWC3_DEVICE_EVENT_WAKEUP 4 58#define DWC3_DEVICE_EVENT_HIBER_REQ 5 59#define DWC3_DEVICE_EVENT_EOPF 6 60#define DWC3_DEVICE_EVENT_SOF 7 61#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 62#define DWC3_DEVICE_EVENT_CMD_CMPL 10 63#define DWC3_DEVICE_EVENT_OVERFLOW 11 64 65#define DWC3_GEVNTCOUNT_MASK 0xfffc 66#define DWC3_GSNPSID_MASK 0xffff0000 67#define DWC3_GSNPSREV_MASK 0xffff 68 69/* DWC3 registers memory space boundries */ 70#define DWC3_XHCI_REGS_START 0x0 71#define DWC3_XHCI_REGS_END 0x7fff 72#define DWC3_GLOBALS_REGS_START 0xc100 73#define DWC3_GLOBALS_REGS_END 0xc6ff 74#define DWC3_DEVICE_REGS_START 0xc700 75#define DWC3_DEVICE_REGS_END 0xcbff 76#define DWC3_OTG_REGS_START 0xcc00 77#define DWC3_OTG_REGS_END 0xccff 78 79/* Global Registers */ 80#define DWC3_GSBUSCFG0 0xc100 81#define DWC3_GSBUSCFG1 0xc104 82#define DWC3_GTXTHRCFG 0xc108 83#define DWC3_GRXTHRCFG 0xc10c 84#define DWC3_GCTL 0xc110 85#define DWC3_GEVTEN 0xc114 86#define DWC3_GSTS 0xc118 87#define DWC3_GSNPSID 0xc120 88#define DWC3_GGPIO 0xc124 89#define DWC3_GUID 0xc128 90#define DWC3_GUCTL 0xc12c 91#define DWC3_GBUSERRADDR0 0xc130 92#define DWC3_GBUSERRADDR1 0xc134 93#define DWC3_GPRTBIMAP0 0xc138 94#define DWC3_GPRTBIMAP1 0xc13c 95#define DWC3_GHWPARAMS0 0xc140 96#define DWC3_GHWPARAMS1 0xc144 97#define DWC3_GHWPARAMS2 0xc148 98#define DWC3_GHWPARAMS3 0xc14c 99#define DWC3_GHWPARAMS4 0xc150 100#define DWC3_GHWPARAMS5 0xc154 101#define DWC3_GHWPARAMS6 0xc158 102#define DWC3_GHWPARAMS7 0xc15c 103#define DWC3_GDBGFIFOSPACE 0xc160 104#define DWC3_GDBGLTSSM 0xc164 105#define DWC3_GPRTBIMAP_HS0 0xc180 106#define DWC3_GPRTBIMAP_HS1 0xc184 107#define DWC3_GPRTBIMAP_FS0 0xc188 108#define DWC3_GPRTBIMAP_FS1 0xc18c 109 110#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 111#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 112 113#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 114 115#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 116 117#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 118#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 119 120#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 121#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 122#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 123#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 124 125#define DWC3_GHWPARAMS8 0xc600 126 127/* Device Registers */ 128#define DWC3_DCFG 0xc700 129#define DWC3_DCTL 0xc704 130#define DWC3_DEVTEN 0xc708 131#define DWC3_DSTS 0xc70c 132#define DWC3_DGCMDPAR 0xc710 133#define DWC3_DGCMD 0xc714 134#define DWC3_DALEPENA 0xc720 135#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 136#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 137#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 138#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 139 140/* OTG Registers */ 141#define DWC3_OCFG 0xcc00 142#define DWC3_OCTL 0xcc04 143#define DWC3_OEVT 0xcc08 144#define DWC3_OEVTEN 0xcc0C 145#define DWC3_OSTS 0xcc10 146 147/* Bit fields */ 148 149/* Global Configuration Register */ 150#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 151#define DWC3_GCTL_U2RSTECN (1 << 16) 152#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 153#define DWC3_GCTL_CLK_BUS (0) 154#define DWC3_GCTL_CLK_PIPE (1) 155#define DWC3_GCTL_CLK_PIPEHALF (2) 156#define DWC3_GCTL_CLK_MASK (3) 157 158#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 159#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 160#define DWC3_GCTL_PRTCAP_HOST 1 161#define DWC3_GCTL_PRTCAP_DEVICE 2 162#define DWC3_GCTL_PRTCAP_OTG 3 163 164#define DWC3_GCTL_CORESOFTRESET (1 << 11) 165#define DWC3_GCTL_SOFITPSYNC (1 << 10) 166#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 167#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 168#define DWC3_GCTL_DISSCRAMBLE (1 << 3) 169#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 170#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 171 172/* Global USB2 PHY Configuration Register */ 173#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 174#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 175 176/* Global USB3 PIPE Control Register */ 177#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 178#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 179 180/* Global TX Fifo Size Register */ 181#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 182#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 183 184/* Global Event Size Registers */ 185#define DWC3_GEVNTSIZ_INTMASK (1 << 31) 186#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 187 188/* Global HWPARAMS1 Register */ 189#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 190#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 191#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 192#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 193#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 194#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 195 196/* Global HWPARAMS3 Register */ 197#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 198#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 199#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 200#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 201#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 202#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 203#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 204#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 205#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 206#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 207#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 208 209/* Global HWPARAMS4 Register */ 210#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 211#define DWC3_MAX_HIBER_SCRATCHBUFS 15 212 213/* Device Configuration Register */ 214#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 215#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 216 217#define DWC3_DCFG_SPEED_MASK (7 << 0) 218#define DWC3_DCFG_SUPERSPEED (4 << 0) 219#define DWC3_DCFG_HIGHSPEED (0 << 0) 220#define DWC3_DCFG_FULLSPEED2 (1 << 0) 221#define DWC3_DCFG_LOWSPEED (2 << 0) 222#define DWC3_DCFG_FULLSPEED1 (3 << 0) 223 224#define DWC3_DCFG_LPM_CAP (1 << 22) 225 226/* Device Control Register */ 227#define DWC3_DCTL_RUN_STOP (1 << 31) 228#define DWC3_DCTL_CSFTRST (1 << 30) 229#define DWC3_DCTL_LSFTRST (1 << 29) 230 231#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 232#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 233 234#define DWC3_DCTL_APPL1RES (1 << 23) 235 236/* These apply for core versions 1.87a and earlier */ 237#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 238#define DWC3_DCTL_TRGTULST(n) ((n) << 17) 239#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 240#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 241#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 242#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 243#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 244 245/* These apply for core versions 1.94a and later */ 246#define DWC3_DCTL_KEEP_CONNECT (1 << 19) 247#define DWC3_DCTL_L1_HIBER_EN (1 << 18) 248#define DWC3_DCTL_CRS (1 << 17) 249#define DWC3_DCTL_CSS (1 << 16) 250 251#define DWC3_DCTL_INITU2ENA (1 << 12) 252#define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 253#define DWC3_DCTL_INITU1ENA (1 << 10) 254#define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 255#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 256 257#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 258#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 259 260#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 261#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 262#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 263#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 264#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 265#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 266#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 267 268/* Device Event Enable Register */ 269#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 270#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 271#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 272#define DWC3_DEVTEN_ERRTICERREN (1 << 9) 273#define DWC3_DEVTEN_SOFEN (1 << 7) 274#define DWC3_DEVTEN_EOPFEN (1 << 6) 275#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 276#define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 277#define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 278#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 279#define DWC3_DEVTEN_USBRSTEN (1 << 1) 280#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 281 282/* Device Status Register */ 283#define DWC3_DSTS_DCNRD (1 << 29) 284 285/* This applies for core versions 1.87a and earlier */ 286#define DWC3_DSTS_PWRUPREQ (1 << 24) 287 288/* These apply for core versions 1.94a and later */ 289#define DWC3_DSTS_RSS (1 << 25) 290#define DWC3_DSTS_SSS (1 << 24) 291 292#define DWC3_DSTS_COREIDLE (1 << 23) 293#define DWC3_DSTS_DEVCTRLHLT (1 << 22) 294 295#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 296#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 297 298#define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 299 300#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 301#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 302 303#define DWC3_DSTS_CONNECTSPD (7 << 0) 304 305#define DWC3_DSTS_SUPERSPEED (4 << 0) 306#define DWC3_DSTS_HIGHSPEED (0 << 0) 307#define DWC3_DSTS_FULLSPEED2 (1 << 0) 308#define DWC3_DSTS_LOWSPEED (2 << 0) 309#define DWC3_DSTS_FULLSPEED1 (3 << 0) 310 311/* Device Generic Command Register */ 312#define DWC3_DGCMD_SET_LMP 0x01 313#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 314#define DWC3_DGCMD_XMIT_FUNCTION 0x03 315 316/* These apply for core versions 1.94a and later */ 317#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 318#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 319 320#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 321#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 322#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 323#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 324 325#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 326#define DWC3_DGCMD_CMDACT (1 << 10) 327#define DWC3_DGCMD_CMDIOC (1 << 8) 328 329/* Device Generic Command Parameter Register */ 330#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 331#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 332#define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 333#define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 334#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 335#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 336 337/* Device Endpoint Command Register */ 338#define DWC3_DEPCMD_PARAM_SHIFT 16 339#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 340#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 341#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 342#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 343#define DWC3_DEPCMD_CMDACT (1 << 10) 344#define DWC3_DEPCMD_CMDIOC (1 << 8) 345 346#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 347#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 348#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 349#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 350#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 351#define DWC3_DEPCMD_SETSTALL (0x04 << 0) 352/* This applies for core versions 1.90a and earlier */ 353#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 354/* This applies for core versions 1.94a and later */ 355#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 356#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 357#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 358 359/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 360#define DWC3_DALEPENA_EP(n) (1 << n) 361 362#define DWC3_DEPCMD_TYPE_CONTROL 0 363#define DWC3_DEPCMD_TYPE_ISOC 1 364#define DWC3_DEPCMD_TYPE_BULK 2 365#define DWC3_DEPCMD_TYPE_INTR 3 366 367/* Structures */ 368 369struct dwc3_trb; 370 371/** 372 * struct dwc3_event_buffer - Software event buffer representation 373 * @buf: _THE_ buffer 374 * @length: size of this buffer 375 * @lpos: event offset 376 * @count: cache of last read event count register 377 * @flags: flags related to this event buffer 378 * @dma: dma_addr_t 379 * @dwc: pointer to DWC controller 380 */ 381struct dwc3_event_buffer { 382 void *buf; 383 unsigned length; 384 unsigned int lpos; 385 unsigned int count; 386 unsigned int flags; 387 388#define DWC3_EVENT_PENDING BIT(0) 389 390 dma_addr_t dma; 391 392 struct dwc3 *dwc; 393}; 394 395#define DWC3_EP_FLAG_STALLED (1 << 0) 396#define DWC3_EP_FLAG_WEDGED (1 << 1) 397 398#define DWC3_EP_DIRECTION_TX true 399#define DWC3_EP_DIRECTION_RX false 400 401#define DWC3_TRB_NUM 32 402#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 403 404/** 405 * struct dwc3_ep - device side endpoint representation 406 * @endpoint: usb endpoint 407 * @request_list: list of requests for this endpoint 408 * @req_queued: list of requests on this ep which have TRBs setup 409 * @trb_pool: array of transaction buffers 410 * @trb_pool_dma: dma address of @trb_pool 411 * @free_slot: next slot which is going to be used 412 * @busy_slot: first slot which is owned by HW 413 * @desc: usb_endpoint_descriptor pointer 414 * @dwc: pointer to DWC controller 415 * @saved_state: ep state saved during hibernation 416 * @flags: endpoint flags (wedged, stalled, ...) 417 * @current_trb: index of current used trb 418 * @number: endpoint number (1 - 15) 419 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 420 * @resource_index: Resource transfer index 421 * @interval: the interval on which the ISOC transfer is started 422 * @name: a human readable name e.g. ep1out-bulk 423 * @direction: true for TX, false for RX 424 * @stream_capable: true when streams are enabled 425 */ 426struct dwc3_ep { 427 struct usb_ep endpoint; 428 struct list_head request_list; 429 struct list_head req_queued; 430 431 struct dwc3_trb *trb_pool; 432 dma_addr_t trb_pool_dma; 433 u32 free_slot; 434 u32 busy_slot; 435 const struct usb_ss_ep_comp_descriptor *comp_desc; 436 struct dwc3 *dwc; 437 438 u32 saved_state; 439 unsigned flags; 440#define DWC3_EP_ENABLED (1 << 0) 441#define DWC3_EP_STALL (1 << 1) 442#define DWC3_EP_WEDGE (1 << 2) 443#define DWC3_EP_BUSY (1 << 4) 444#define DWC3_EP_PENDING_REQUEST (1 << 5) 445#define DWC3_EP_MISSED_ISOC (1 << 6) 446 447 /* This last one is specific to EP0 */ 448#define DWC3_EP0_DIR_IN (1 << 31) 449 450 unsigned current_trb; 451 452 u8 number; 453 u8 type; 454 u8 resource_index; 455 u32 interval; 456 457 char name[20]; 458 459 unsigned direction:1; 460 unsigned stream_capable:1; 461}; 462 463enum dwc3_phy { 464 DWC3_PHY_UNKNOWN = 0, 465 DWC3_PHY_USB3, 466 DWC3_PHY_USB2, 467}; 468 469enum dwc3_ep0_next { 470 DWC3_EP0_UNKNOWN = 0, 471 DWC3_EP0_COMPLETE, 472 DWC3_EP0_NRDY_DATA, 473 DWC3_EP0_NRDY_STATUS, 474}; 475 476enum dwc3_ep0_state { 477 EP0_UNCONNECTED = 0, 478 EP0_SETUP_PHASE, 479 EP0_DATA_PHASE, 480 EP0_STATUS_PHASE, 481}; 482 483enum dwc3_link_state { 484 /* In SuperSpeed */ 485 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 486 DWC3_LINK_STATE_U1 = 0x01, 487 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 488 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 489 DWC3_LINK_STATE_SS_DIS = 0x04, 490 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 491 DWC3_LINK_STATE_SS_INACT = 0x06, 492 DWC3_LINK_STATE_POLL = 0x07, 493 DWC3_LINK_STATE_RECOV = 0x08, 494 DWC3_LINK_STATE_HRESET = 0x09, 495 DWC3_LINK_STATE_CMPLY = 0x0a, 496 DWC3_LINK_STATE_LPBK = 0x0b, 497 DWC3_LINK_STATE_RESET = 0x0e, 498 DWC3_LINK_STATE_RESUME = 0x0f, 499 DWC3_LINK_STATE_MASK = 0x0f, 500}; 501 502/* TRB Length, PCM and Status */ 503#define DWC3_TRB_SIZE_MASK (0x00ffffff) 504#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 505#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 506#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 507 508#define DWC3_TRBSTS_OK 0 509#define DWC3_TRBSTS_MISSED_ISOC 1 510#define DWC3_TRBSTS_SETUP_PENDING 2 511#define DWC3_TRB_STS_XFER_IN_PROG 4 512 513/* TRB Control */ 514#define DWC3_TRB_CTRL_HWO (1 << 0) 515#define DWC3_TRB_CTRL_LST (1 << 1) 516#define DWC3_TRB_CTRL_CHN (1 << 2) 517#define DWC3_TRB_CTRL_CSP (1 << 3) 518#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 519#define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 520#define DWC3_TRB_CTRL_IOC (1 << 11) 521#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 522 523#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 524#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 525#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 526#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 527#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 528#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 529#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 530#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 531 532/** 533 * struct dwc3_trb - transfer request block (hw format) 534 * @bpl: DW0-3 535 * @bph: DW4-7 536 * @size: DW8-B 537 * @trl: DWC-F 538 */ 539struct dwc3_trb { 540 u32 bpl; 541 u32 bph; 542 u32 size; 543 u32 ctrl; 544} __packed; 545 546/** 547 * dwc3_hwparams - copy of HWPARAMS registers 548 * @hwparams0 - GHWPARAMS0 549 * @hwparams1 - GHWPARAMS1 550 * @hwparams2 - GHWPARAMS2 551 * @hwparams3 - GHWPARAMS3 552 * @hwparams4 - GHWPARAMS4 553 * @hwparams5 - GHWPARAMS5 554 * @hwparams6 - GHWPARAMS6 555 * @hwparams7 - GHWPARAMS7 556 * @hwparams8 - GHWPARAMS8 557 */ 558struct dwc3_hwparams { 559 u32 hwparams0; 560 u32 hwparams1; 561 u32 hwparams2; 562 u32 hwparams3; 563 u32 hwparams4; 564 u32 hwparams5; 565 u32 hwparams6; 566 u32 hwparams7; 567 u32 hwparams8; 568}; 569 570/* HWPARAMS0 */ 571#define DWC3_MODE(n) ((n) & 0x7) 572 573#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 574 575/* HWPARAMS1 */ 576#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 577 578/* HWPARAMS3 */ 579#define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 580#define DWC3_NUM_EPS_MASK (0x3f << 12) 581#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 582 (DWC3_NUM_EPS_MASK)) >> 12) 583#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 584 (DWC3_NUM_IN_EPS_MASK)) >> 18) 585 586/* HWPARAMS7 */ 587#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 588 589struct dwc3_request { 590 struct usb_request request; 591 struct list_head list; 592 struct dwc3_ep *dep; 593 u32 start_slot; 594 595 u8 epnum; 596 struct dwc3_trb *trb; 597 dma_addr_t trb_dma; 598 599 unsigned direction:1; 600 unsigned mapped:1; 601 unsigned queued:1; 602}; 603 604/* 605 * struct dwc3_scratchpad_array - hibernation scratchpad array 606 * (format defined by hw) 607 */ 608struct dwc3_scratchpad_array { 609 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 610}; 611 612/** 613 * struct dwc3 - representation of our controller 614 * @ctrl_req: usb control request which is used for ep0 615 * @ep0_trb: trb which is used for the ctrl_req 616 * @ep0_bounce: bounce buffer for ep0 617 * @setup_buf: used while precessing STD USB requests 618 * @ctrl_req_addr: dma address of ctrl_req 619 * @ep0_trb: dma address of ep0_trb 620 * @ep0_usb_req: dummy req used while handling STD USB requests 621 * @ep0_bounce_addr: dma address of ep0_bounce 622 * @scratch_addr: dma address of scratchbuf 623 * @lock: for synchronizing 624 * @dev: pointer to our struct device 625 * @xhci: pointer to our xHCI child 626 * @event_buffer_list: a list of event buffers 627 * @gadget: device side representation of the peripheral controller 628 * @gadget_driver: pointer to the gadget driver 629 * @regs: base address for our registers 630 * @regs_size: address space size 631 * @nr_scratch: number of scratch buffers 632 * @num_event_buffers: calculated number of event buffers 633 * @u1u2: only used on revisions <1.83a for workaround 634 * @maximum_speed: maximum speed requested (mainly for testing purposes) 635 * @revision: revision register contents 636 * @dr_mode: requested mode of operation 637 * @usb2_phy: pointer to USB2 PHY 638 * @usb3_phy: pointer to USB3 PHY 639 * @usb2_generic_phy: pointer to USB2 PHY 640 * @usb3_generic_phy: pointer to USB3 PHY 641 * @dcfg: saved contents of DCFG register 642 * @gctl: saved contents of GCTL register 643 * @isoch_delay: wValue from Set Isochronous Delay request; 644 * @u2sel: parameter from Set SEL request. 645 * @u2pel: parameter from Set SEL request. 646 * @u1sel: parameter from Set SEL request. 647 * @u1pel: parameter from Set SEL request. 648 * @num_out_eps: number of out endpoints 649 * @num_in_eps: number of in endpoints 650 * @ep0_next_event: hold the next expected event 651 * @ep0state: state of endpoint zero 652 * @link_state: link state 653 * @speed: device speed (super, high, full, low) 654 * @mem: points to start of memory which is used for this struct. 655 * @hwparams: copy of hwparams registers 656 * @root: debugfs root folder pointer 657 * @regset: debugfs pointer to regdump file 658 * @test_mode: true when we're entering a USB test mode 659 * @test_mode_nr: test feature selector 660 * @delayed_status: true when gadget driver asks for delayed status 661 * @ep0_bounced: true when we used bounce buffer 662 * @ep0_expect_in: true when we expect a DATA IN transfer 663 * @has_hibernation: true when dwc3 was configured with Hibernation 664 * @is_selfpowered: true when we are selfpowered 665 * @needs_fifo_resize: not all users might want fifo resizing, flag it 666 * @pullups_connected: true when Run/Stop bit is set 667 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 668 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 669 * @start_config_issued: true when StartConfig command has been issued 670 * @three_stage_setup: set if we perform a three phase setup 671 */ 672struct dwc3 { 673 struct usb_ctrlrequest *ctrl_req; 674 struct dwc3_trb *ep0_trb; 675 void *ep0_bounce; 676 void *scratchbuf; 677 u8 *setup_buf; 678 dma_addr_t ctrl_req_addr; 679 dma_addr_t ep0_trb_addr; 680 dma_addr_t ep0_bounce_addr; 681 dma_addr_t scratch_addr; 682 struct dwc3_request ep0_usb_req; 683 684 /* device lock */ 685 spinlock_t lock; 686 687 struct device *dev; 688 689 struct platform_device *xhci; 690 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 691 692 struct dwc3_event_buffer **ev_buffs; 693 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 694 695 struct usb_gadget gadget; 696 struct usb_gadget_driver *gadget_driver; 697 698 struct usb_phy *usb2_phy; 699 struct usb_phy *usb3_phy; 700 701 struct phy *usb2_generic_phy; 702 struct phy *usb3_generic_phy; 703 704 void __iomem *regs; 705 size_t regs_size; 706 707 enum usb_dr_mode dr_mode; 708 709 /* used for suspend/resume */ 710 u32 dcfg; 711 u32 gctl; 712 713 u32 nr_scratch; 714 u32 num_event_buffers; 715 u32 u1u2; 716 u32 maximum_speed; 717 u32 revision; 718 719#define DWC3_REVISION_173A 0x5533173a 720#define DWC3_REVISION_175A 0x5533175a 721#define DWC3_REVISION_180A 0x5533180a 722#define DWC3_REVISION_183A 0x5533183a 723#define DWC3_REVISION_185A 0x5533185a 724#define DWC3_REVISION_187A 0x5533187a 725#define DWC3_REVISION_188A 0x5533188a 726#define DWC3_REVISION_190A 0x5533190a 727#define DWC3_REVISION_194A 0x5533194a 728#define DWC3_REVISION_200A 0x5533200a 729#define DWC3_REVISION_202A 0x5533202a 730#define DWC3_REVISION_210A 0x5533210a 731#define DWC3_REVISION_220A 0x5533220a 732#define DWC3_REVISION_230A 0x5533230a 733#define DWC3_REVISION_240A 0x5533240a 734#define DWC3_REVISION_250A 0x5533250a 735#define DWC3_REVISION_260A 0x5533260a 736#define DWC3_REVISION_270A 0x5533270a 737#define DWC3_REVISION_280A 0x5533280a 738 739 enum dwc3_ep0_next ep0_next_event; 740 enum dwc3_ep0_state ep0state; 741 enum dwc3_link_state link_state; 742 743 u16 isoch_delay; 744 u16 u2sel; 745 u16 u2pel; 746 u8 u1sel; 747 u8 u1pel; 748 749 u8 speed; 750 751 u8 num_out_eps; 752 u8 num_in_eps; 753 754 void *mem; 755 756 struct dwc3_hwparams hwparams; 757 struct dentry *root; 758 struct debugfs_regset32 *regset; 759 760 u8 test_mode; 761 u8 test_mode_nr; 762 763 unsigned delayed_status:1; 764 unsigned ep0_bounced:1; 765 unsigned ep0_expect_in:1; 766 unsigned has_hibernation:1; 767 unsigned is_selfpowered:1; 768 unsigned needs_fifo_resize:1; 769 unsigned pullups_connected:1; 770 unsigned resize_fifos:1; 771 unsigned setup_packet_pending:1; 772 unsigned start_config_issued:1; 773 unsigned three_stage_setup:1; 774}; 775 776/* -------------------------------------------------------------------------- */ 777 778/* -------------------------------------------------------------------------- */ 779 780struct dwc3_event_type { 781 u32 is_devspec:1; 782 u32 type:7; 783 u32 reserved8_31:24; 784} __packed; 785 786#define DWC3_DEPEVT_XFERCOMPLETE 0x01 787#define DWC3_DEPEVT_XFERINPROGRESS 0x02 788#define DWC3_DEPEVT_XFERNOTREADY 0x03 789#define DWC3_DEPEVT_RXTXFIFOEVT 0x04 790#define DWC3_DEPEVT_STREAMEVT 0x06 791#define DWC3_DEPEVT_EPCMDCMPLT 0x07 792 793/** 794 * struct dwc3_event_depvt - Device Endpoint Events 795 * @one_bit: indicates this is an endpoint event (not used) 796 * @endpoint_number: number of the endpoint 797 * @endpoint_event: The event we have: 798 * 0x00 - Reserved 799 * 0x01 - XferComplete 800 * 0x02 - XferInProgress 801 * 0x03 - XferNotReady 802 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 803 * 0x05 - Reserved 804 * 0x06 - StreamEvt 805 * 0x07 - EPCmdCmplt 806 * @reserved11_10: Reserved, don't use. 807 * @status: Indicates the status of the event. Refer to databook for 808 * more information. 809 * @parameters: Parameters of the current event. Refer to databook for 810 * more information. 811 */ 812struct dwc3_event_depevt { 813 u32 one_bit:1; 814 u32 endpoint_number:5; 815 u32 endpoint_event:4; 816 u32 reserved11_10:2; 817 u32 status:4; 818 819/* Within XferNotReady */ 820#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 821 822/* Within XferComplete */ 823#define DEPEVT_STATUS_BUSERR (1 << 0) 824#define DEPEVT_STATUS_SHORT (1 << 1) 825#define DEPEVT_STATUS_IOC (1 << 2) 826#define DEPEVT_STATUS_LST (1 << 3) 827 828/* Stream event only */ 829#define DEPEVT_STREAMEVT_FOUND 1 830#define DEPEVT_STREAMEVT_NOTFOUND 2 831 832/* Control-only Status */ 833#define DEPEVT_STATUS_CONTROL_DATA 1 834#define DEPEVT_STATUS_CONTROL_STATUS 2 835 836 u32 parameters:16; 837} __packed; 838 839/** 840 * struct dwc3_event_devt - Device Events 841 * @one_bit: indicates this is a non-endpoint event (not used) 842 * @device_event: indicates it's a device event. Should read as 0x00 843 * @type: indicates the type of device event. 844 * 0 - DisconnEvt 845 * 1 - USBRst 846 * 2 - ConnectDone 847 * 3 - ULStChng 848 * 4 - WkUpEvt 849 * 5 - Reserved 850 * 6 - EOPF 851 * 7 - SOF 852 * 8 - Reserved 853 * 9 - ErrticErr 854 * 10 - CmdCmplt 855 * 11 - EvntOverflow 856 * 12 - VndrDevTstRcved 857 * @reserved15_12: Reserved, not used 858 * @event_info: Information about this event 859 * @reserved31_25: Reserved, not used 860 */ 861struct dwc3_event_devt { 862 u32 one_bit:1; 863 u32 device_event:7; 864 u32 type:4; 865 u32 reserved15_12:4; 866 u32 event_info:9; 867 u32 reserved31_25:7; 868} __packed; 869 870/** 871 * struct dwc3_event_gevt - Other Core Events 872 * @one_bit: indicates this is a non-endpoint event (not used) 873 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 874 * @phy_port_number: self-explanatory 875 * @reserved31_12: Reserved, not used. 876 */ 877struct dwc3_event_gevt { 878 u32 one_bit:1; 879 u32 device_event:7; 880 u32 phy_port_number:4; 881 u32 reserved31_12:20; 882} __packed; 883 884/** 885 * union dwc3_event - representation of Event Buffer contents 886 * @raw: raw 32-bit event 887 * @type: the type of the event 888 * @depevt: Device Endpoint Event 889 * @devt: Device Event 890 * @gevt: Global Event 891 */ 892union dwc3_event { 893 u32 raw; 894 struct dwc3_event_type type; 895 struct dwc3_event_depevt depevt; 896 struct dwc3_event_devt devt; 897 struct dwc3_event_gevt gevt; 898}; 899 900/** 901 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 902 * parameters 903 * @param2: third parameter 904 * @param1: second parameter 905 * @param0: first parameter 906 */ 907struct dwc3_gadget_ep_cmd_params { 908 u32 param2; 909 u32 param1; 910 u32 param0; 911}; 912 913/* 914 * DWC3 Features to be used as Driver Data 915 */ 916 917#define DWC3_HAS_PERIPHERAL BIT(0) 918#define DWC3_HAS_XHCI BIT(1) 919#define DWC3_HAS_OTG BIT(3) 920 921/* prototypes */ 922void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 923int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 924 925#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 926int dwc3_host_init(struct dwc3 *dwc); 927void dwc3_host_exit(struct dwc3 *dwc); 928#else 929static inline int dwc3_host_init(struct dwc3 *dwc) 930{ return 0; } 931static inline void dwc3_host_exit(struct dwc3 *dwc) 932{ } 933#endif 934 935#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 936int dwc3_gadget_init(struct dwc3 *dwc); 937void dwc3_gadget_exit(struct dwc3 *dwc); 938int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 939int dwc3_gadget_get_link_state(struct dwc3 *dwc); 940int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 941int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 942 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 943int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 944#else 945static inline int dwc3_gadget_init(struct dwc3 *dwc) 946{ return 0; } 947static inline void dwc3_gadget_exit(struct dwc3 *dwc) 948{ } 949static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 950{ return 0; } 951static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 952{ return 0; } 953static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 954 enum dwc3_link_state state) 955{ return 0; } 956 957static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 958 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 959{ return 0; } 960static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 961 int cmd, u32 param) 962{ return 0; } 963#endif 964 965/* power management interface */ 966#if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 967int dwc3_gadget_prepare(struct dwc3 *dwc); 968void dwc3_gadget_complete(struct dwc3 *dwc); 969int dwc3_gadget_suspend(struct dwc3 *dwc); 970int dwc3_gadget_resume(struct dwc3 *dwc); 971#else 972static inline int dwc3_gadget_prepare(struct dwc3 *dwc) 973{ 974 return 0; 975} 976 977static inline void dwc3_gadget_complete(struct dwc3 *dwc) 978{ 979} 980 981static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 982{ 983 return 0; 984} 985 986static inline int dwc3_gadget_resume(struct dwc3 *dwc) 987{ 988 return 0; 989} 990#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 991 992#endif /* __DRIVERS_USB_DWC3_CORE_H */ 993