| e12892070184ee782c207f09722a93d0236be955 |
|
19-May-2014 |
Xiubo Li <Li.Xiubo@freescale.com> |
regmap: irq: Fix possible ZERO_SIZE_PTR pointer dereferencing error.
Since we cannot make sure the 'chip->num_regs' will always be none zero
from the users, and then if 'chip->num_regs' equals to zero by mistake
or other reasons, the kzalloc() will return ZERO_SIZE_PTR, which equals
to ((void *)16).
So this patch fix this with just checking the 'chip->num_regs' before
calling kzalloc().
This also sorts the header files in alphabetical order at the same time.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| 72a6a5df2c6c06e1a2504a6272d722e435a93bcb |
|
13-Mar-2014 |
Krzysztof Kozlowski <k.kozlowski@samsung.com> |
regmap: irq: Set data pointer only on regmap_add_irq_chip success
After setting the 'data' pointer (wchich is returned to the caller for
freeing later) the regmap_add_irq_chip() could still fail for various
reasons (ENOMEM, regmap_read or regmap_write failure). In such case the
memory under 'data' was freed in error path and error value was returned
but the 'data' variable was not changed.
This could lead to errors if the caller passed such 'data' to
regmap_del_irq_chip().
The 'data' pointer should be changed atomically from the caller
perspective - set it only on regmap_add_irq_chip() success.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| b5ab3e5cae097642480b7983c13ff9d3ea21d0de |
|
22-Jan-2014 |
Mark Brown <broonie@linaro.org> |
regmap: irq: Remove domain on exit
irqdomain now supports removal of domains on exit so we can properly clean
up on deletion of a regmap irqchip.
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| d3233433356aa1965b60b08ee61465b20e50474b |
|
15-Dec-2013 |
Alexander Shiyan <shc_work@mail.ru> |
regmap: irq: Allow using zero value for ack_base
In some cases, clear interrupt register may be at address 0.
This patch allows to use such configurations by adding additional
configuration bit to indicate this.
[With doc fix from Levente Kurusa <levex@linux.com> -- broonie]
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| 4bd7145b194af7cd96fc56d2ebee583b3edf03d3 |
|
22-Oct-2013 |
Yi Zhang <yizhang@marvell.com> |
regmap: irq: clear status when disable irq
clear the status bit if the mask register doesn't prevent
the chip level irq from being asserted
OR in the following sequence, there will be irq storm happens:
1) interrupt is triggered;
2) another thread disables it(the mask bit is set);
3) _Then_ the interrupt thread is not ACKed(the status bit is not cleared),
and it's ignored;
4) if the irq is still asserted because of the uncleared status bit,
the irq storm happens;
Signed-off-by: Yi Zhang <yizhang@marvell.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| 2753e6f8207355ab72574d48287cec187272a151 |
|
22-Jul-2013 |
Philipp Zabel <p.zabel@pengutronix.de> |
regmap: irq: Allow to acknowledge masked interrupts during initialization
In case the hardware interrupt mask register does not prevent the chip level
irq from being asserted by the corresponding interrupt status bit, already
set interrupt bits should to be cleared once after masking them during
initialization. Add a flag to let drivers enable this behavior.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
|
| eed456f93d01e9476a1e777d22ae8a8382546ab7 |
|
19-Mar-2013 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Clarify error message when we fail to request primary IRQ
Display the name for the chip rather than just the primary IRQ so it is
clearer what exactly has failed.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 283189d3be56aa6db6f192bb255df68493cd79ac |
|
28-Feb-2013 |
Li Fei <fei.li@intel.com> |
regmap: irq: call pm_runtime_put in pm_runtime_get_sync failed case
Even in failed case of pm_runtime_get_sync, the usage_count
is incremented. In order to keep the usage_count with correct
value and runtime power management to behave correctly, call
pm_runtime_put(_sync) in such case.
Signed-off-by Liu Chuansheng <chuansheng.liu@intel.com>
Signed-off-by: Li Fei <fei.li@intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 9442490a02867088bcd5ed6231fa3b35a733c2b8 |
|
04-Jan-2013 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Support wake IRQ mask inversion
Support devices which have an enable rather than mask register for wake
sources.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 33be49324f7f3e9dff10d3d07a5c78ee82f8d54e |
|
04-Jan-2013 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Fix sync of wake statuses to hardware
This wasn't implemented but happened to work on test systems due to lack
of wake mask inversion support.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| a7440eaa90cf2659920b9b28973cc1a13a2b331f |
|
03-Jan-2013 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Use a bulk read for interrupt status where possible
If the interrupt status registers are a single block of registers and the
chip supports bulk reads then do a single bulk read rather than pay the
extra I/O cost. This restores the original behaviour which was lost when
support for register striding was added.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| bbae92ca49f77898277576e3377b09e1391a3271 |
|
03-Jan-2013 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Factor register read out of the IRQ parsing loop
In preparation for adding back support for block reads.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 55ac85e942c6783e728964861df36fc80e8ced93 |
|
19-Dec-2012 |
Laxman Dewangan <ldewangan@nvidia.com> |
regmap: irq: enable wake support by default
regmap-irq framework is used vastly by mfd drivers and some of
devices like TPS65910, TPS80036 do not support the wake base
register to enable wake.
Currently wake in regmap-irq only supported if client driver
passes the wake base register.
As the regmap-irq is mostly used by mfd devices and it is require
to have wake support from these devices in most of use cases,
enabling wake support by default in regmap-irq.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 90f790d2dc96f5a61855ae65b90e30c40c893a20 |
|
20-Aug-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Allow users to retrieve the irq_domain
This is useful for integration with other subsystems, especially MFD,
and provides an alternative API for users that request their own IRQs.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 81380739516730124067576c9cc9f2418be5bf36 |
|
08-Sep-2012 |
Yunfan Zhang <yfzhang@marvell.com> |
regmap: no need primary handler for nested irq
The primary handler will NOT be called if the interrupt nests into
another interrupt thread. Remove it to avoid confusing.
Signed-off-by: Yunfan Zhang <yfzhang@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 36ac914ba2a5f1a14c5e0bf5d33bc20016d50940 |
|
30-Aug-2012 |
Xiaofan Tian <tianxf@marvell.com> |
regmap: irq: Add mask invert flag for enable register
Currently, regmap will write 1 to mask_base to mask
an interrupt and write 0 to unmask it.
But some chips do not have an interrupt mask register,
and only have interrupt enable register.
Then we should write 0 to disable interrupt and 1 to enable.
So add an mask_invert flag to handle this.
If it is not set, behavior is same as previous.
If set it to 1, the mask value will be inverted
before written to mask_base
Signed-off-by: Xiaofan Tian <tianxf@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 0c00c50b41a9a6ee83eb16fb5c6c22e5115391b8 |
|
24-Jul-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Enable devices for runtime PM while handling interrupts
Some devices need to have a runtime PM reference while handling interrupts
to ensure that the register I/O is available. Support this with a flag in
the chip.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 40052ca0c243d101cfadd65936f60ef81df10b02 |
|
01-Aug-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: irq: initialize all irqs to wake disabled
The kerneldoc for irq_set_irq_wake() says:
Enable/disable power management wakeup mode, which is
disabled by default.
regmap_irq_set_wake() clears bits to enable wake for an interrupt,
and sets bits to disable wake. Hence, we should set all bits in
wake_buf initially, to mirror the expected disabled state.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 685879f4b2036e58c1a0cdaaee2b155d3c965461 |
|
01-Aug-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: set MASK_ON_SUSPEND/SKIP_SET_WAKE if no wake_base
If a regmap-irq chip has no wake base:
* There's no point calling .irq_set_wake, hence IRQCHIP_SKIP_SET_WAKE.
* If some IRQs in the chip are enabled for wake and some aren't, we
should mask those interrupts that are not wake enabled, so that if
they occur during suspend, the system is not awoken. Hence,
IRQCHIP_MASK_ON_SUSPEND.
Note that IRQCHIP_MASK_ON_SUSPEND is handled by check_wakeup_irqs(),
which always iterates over every single interrupt in the system,
irrespective of whether an interrupt is a child of a controller whose
output interrupt has no wake-enabled inputs and hence is presumably
masked itself. Hence this change might cause interrupt unnecessary
masking operations and associated register I/O.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| ca142750f8ac3d01e45909e624ca783779894640 |
|
01-Aug-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: name irq_chip based on regmap_irq_chip's name
This is intended to give each irq_chip a useful name, rather than hard-
coding them all as "regmap".
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 7ac140ec426ed304237205be77f99eedfc1186b5 |
|
01-Aug-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: store irq_chip inside regmap_irq_chip_data
This will allow later patches to adjust portions of the irq_chip
individually for each regmap_irq_chip that is created.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 0eb46ad0c8d60943c1f46cef795fc537fbffd177 |
|
01-Aug-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: irq: Only update mask bits when doing initial mask
Don't write the full register, it's possible there's bits other than the
masks in the same register which we shouldn't be changing.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
|
| 16032624f511b2fac0671cba5e7da40aa7e73a66 |
|
27-Jul-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: fix some error messages to take account of irq_reg_stride
A number of places in the code were printing error messages that included
the address of a register, but were not calculating the register address
in the same way as the access to the register. Use a temporary to solve
this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| a43fd50dc99a5f65505f174eca5a421707d73b4c |
|
05-Jun-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Implement support for wake IRQs
Allow chips to provide a bank of registers for controlling the wake state
in a similar fashion to the masks and propagate the wake count to the
parent interrupt controller.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| bfd6185ddecc6e6f6bd654c053c307c9e49ca391 |
|
05-Jun-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Don't try to map non-existant IRQs
If the driver supplied an empty entry in the array of IRQs then return
an error rather than trying to do the mapping. This is intended for use
with handling chip variants and similar situations.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| b026ddbbd25e3560c8d69beb96a5980d96c59b43 |
|
31-May-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Constify regmap_irq_chip
We should never be modifying it and it lets drivers declare it const.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 38e7f5d1b73e71f87745a9c3e5806a6c28c34a53 |
|
17-May-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Fix typo in IRQ register striding
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 022f926a2401c80ed36ebb48a1bffbac08f34d98 |
|
14-May-2012 |
Graeme Gregory <gg@slimlogic.co.uk> |
regmap: add support for non contiguous status to regmap-irq
In some chips the IRQ status registers are not contiguous in the register
map but spaced at even spaces. This is an easy case to handle with minor
changes. It is assume for this purpose that the stride for status is
equal to the stride for mask/ack registers as well.
Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 4af8be67fd9989f4e63a8d1defc1895ed0f7d341 |
|
13-May-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Convert regmap_irq to use irq_domain
This gets us up to date with the recommended current kernel infrastructure
and should transparently give us device tree interrupt bindings for any
devices using the framework. If an explicit IRQ mapping is passed in then
a legacy interrupt range is created, otherwise a simple linear mapping is
used. Previously a mapping was mandatory so existing drivers should not
be affected.
A function regmap_irq_get_virq() is provided to allow drivers to map
individual IRQs which should be used in preference to the existing
regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is
provided.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 2431d0a1d68aabefeee02b93971ee73e8b215697 |
|
13-May-2012 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Pass back the allocated regmap IRQ controller data
It's needed for freeing and for obtaining the IRQ base later on.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| a21361b9b9e0d9436a37951a2b0f25b022136fbb |
|
11-Apr-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: fix compile errors in regmap-irq.c due to stride changes
Commit f01ee60fffa4 ("regmap: implement register striding") caused the
compile errors below. Fix them.
drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_sync_unlock':
drivers/base/regmap/regmap-irq.c:62:12: error: 'map' undeclared (first use in this function)
drivers/base/regmap/regmap-irq.c:62:12: note: each undeclared identifier is reported only once for each function it appears in
drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_enable':
drivers/base/regmap/regmap-irq.c:77:37: error: 'map' undeclared (first use in this function)
drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_disable':
drivers/base/regmap/regmap-irq.c:85:37: error: 'map' undeclared (first use in this function)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| edc9ae420f98dd094e47f8b2d33652858bdc830b |
|
09-Apr-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: implement register striding
regmap_config.reg_stride is introduced. All extant register addresses
are a multiple of this value. Users of serial-oriented regmap busses will
typically set this to 1. Users of the MMIO regmap bus will typically set
this based on the value size of their registers, in bytes, so 4 for a
32-bit register.
Throughout the regmap code, actual register addresses are used. Wherever
the register address is used to index some array of values, the address
is divided by the stride to determine the index, or vice-versa. Error-
checking is added to all entry-points for register address data to ensure
that register addresses actually satisfy the specified stride. The MMIO
bus ensures that the specified stride is large enough for the register
size.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 56806555de5485d6786bf0f8df01b8ed9fc5d006 |
|
11-Apr-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: fix compile errors in regmap-irq.c due to stride changes
Commit f01ee60fffa4 ("regmap: implement register striding") caused the
compile errors below. Fix them.
drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_sync_unlock':
drivers/base/regmap/regmap-irq.c:62:12: error: 'map' undeclared (first use in this function)
drivers/base/regmap/regmap-irq.c:62:12: note: each undeclared identifier is reported only once for each function it appears in
drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_enable':
drivers/base/regmap/regmap-irq.c:77:37: error: 'map' undeclared (first use in this function)
drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_disable':
drivers/base/regmap/regmap-irq.c:85:37: error: 'map' undeclared (first use in this function)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| f01ee60fffa4dc6c77122121233a793f7f696e67 |
|
09-Apr-2012 |
Stephen Warren <swarren@nvidia.com> |
regmap: implement register striding
regmap_config.reg_stride is introduced. All extant register addresses
are a multiple of this value. Users of serial-oriented regmap busses will
typically set this to 1. Users of the MMIO regmap bus will typically set
this based on the value size of their registers, in bytes, so 4 for a
32-bit register.
Throughout the regmap code, actual register addresses are used. Wherever
the register address is used to index some array of values, the address
is divided by the stride to determine the index, or vice-versa. Error-
checking is added to all entry-points for register address data to ensure
that register addresses actually satisfy the specified stride. The MMIO
bus ensures that the specified stride is large enough for the register
size.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| 51990e825431089747f8896244b5c17d3a6423f1 |
|
22-Jan-2012 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
device.h: cleanup users outside of linux/include (C files)
For files that are actively using linux/device.h, make sure
that they call it out. This will allow us to clean up some
of the implicit uses of linux/device.h within include/*
without introducing build regressions.
Yes, this was created by "cheating" -- i.e. the headers were
cleaned up, and then the fallout was found and fixed, and then
the two commits were reordered. This ensures we don't introduce
build regressions into the git history.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
|
| 209a600623cf13a8168b2f6b83643db7825abb9a |
|
05-Dec-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Add irq_base accessor to regmap_irq
Allows devices to discover their own interrupt without having to remember
it themselves.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| d23511f9590870effa5ace575b59aac18c47175f |
|
28-Nov-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Report if we actually handled an interrupt in regmap-irq
While the IRQ core doesn't currently support shared threaded interrupts
that's no reason for drivers not to do their bit and report IRQ_NONE when
they don't get an interrupt. This allows the core spurious/wedget interrupt
detection support to do its thing.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| f8beab2bb611d735767871e0e1a12dc6a0def7b1 |
|
28-Oct-2011 |
Mark Brown <broonie@opensource.wolfsonmicro.com> |
regmap: Add a reusable irq_chip for regmap based interrupt controllers
There seem to be lots of regmap-using devices with very similar interrupt
controllers with a small bank of interrupt registers and mask registers
with an interrupt per bit. This won't cover everything but it's a good
start.
Each chip supplies a base for the status registers, a base for the mask
registers, an optional base for writing acknowledgements (which may be the
same as the status registers) and an array of bits within each of these
register banks which indicate the interrupt.
There is an assumption that the bit for each interrupt will be the same
in each of the register bank.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|