| /drivers/staging/rtl8188eu/include/ |
| H A D | pwrseq.h | 80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \
89 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
122 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
125 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \
133 PWR_CMD_WRITE, BIT4,
[all...] |
| H A D | rtw_sreset.h | 37 #define WIFI_TX_HANG BIT4
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| H A D | odm_debug.h | 64 #define ODM_COMP_RSSI_MONITOR BIT4
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| H A D | rtl8188e_spec.h | 30 #define BIT4 0x00000010 macro
486 #define CmdEERPOMSEL BIT4
487 #define Cmd9346CR_9356SEL BIT4
544 #define CMD_INIT_LLT_ERR BIT4
555 #define RRSR_6M BIT4
638 #define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */
701 #define StopMgt BIT4
728 #define RCR_ADD3 BIT4 /* Accept address 3 match pkt */
1204 #define SDIO_HIMR_TXFOVW_MSK BIT4
1230 #define SDIO_HISR_TXFOVW BIT4
[all...] |
| H A D | Hal8188EPhyCfg.h | 95 WIRELESS_MODE_N_5G = BIT4,
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| H A D | odm.h | 421 ODM_BB_RSSI_MONITOR = BIT4,
441 #define ODM_RTL8188E BIT4
461 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
467 ODM_RF_RX_A = BIT4,
505 ODM_AP_MODE = BIT4,
519 ODM_WM_N5G = BIT4,
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| H A D | osdep_service.h | 111 #define BIT4 0x00000010 macro
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| /drivers/staging/vt6655/ |
| H A D | hostap.h | 38 #define WLAN_RATE_6M BIT4
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| H A D | 80211hdr.h | 41 #define BIT4 0x00000010 macro
160 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
179 #define WLAN_GET_CAP_INFO_PRIVACY(n) ((((n) >> 8) & BIT4) >> 4)
193 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
212 #define WLAN_GET_CAP_INFO_PRIVACY(n) (((n) & BIT4) >> 4)
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| H A D | bssdb.h | 58 #define WLAN_STA_PERM BIT4
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| /drivers/scsi/ |
| H A D | tmscsim.h | 188 #define BIT4 0x00000010 macro
211 #define SRB_MSGIN_MULTI BIT4
228 #define PARITY_ERROR BIT4
243 #define ENABLE_TIMER BIT4
283 #define EN_TAG_QUEUEING BIT4
338 #define TAG_QUEUEING_ BIT4
345 #define NO_SEEK BIT4
393 #define COUNT_2_ZERO BIT4
402 #define SERVICE_REQUEST BIT4
425 #define PARITY_ERR_REPO BIT4
[all...] |
| H A D | dc395x.h | 71 #define BIT4 0x00000010 macro
132 #define PARITY_ERROR BIT4
139 #define ENABLE_TIMER BIT4
177 #define WIDE_NEGO_STATE BIT4
633 #define NO_SEEK BIT4
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| /drivers/net/wireless/rtlwifi/rtl8821ae/ |
| H A D | pwrseq.h | 121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT
[all...] |
| /drivers/net/wireless/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 52 #define BIT4 0x00000010 macro
|
| H A D | halbtc8723b2ant.h | 36 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
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| H A D | halbtc8821a2ant.h | 33 #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
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| H A D | halbtc8192e2ant.h | 33 #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
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| H A D | halbtc8723b1ant.h | 33 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
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| H A D | halbtc8821a1ant.h | 35 #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
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| H A D | halbtcoutsrc.h | 105 #define ALGO_TRACE_FW BIT4
117 #define WIFI_P2P_GC_CONNECTED BIT4
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| /drivers/staging/rtl8192e/rtl8192e/ |
| H A D | rtl_pci.c | 43 tmp |= BIT4;
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| H A D | r8192E_hw.h | 115 #define EPROM_CMD_9356SEL BIT4
219 #define SCR_SKByA2 BIT4
238 #define IMR_BKDOK BIT4
249 #define TPPoll_BQ BIT4
289 #define AcmHw_BeqStatus BIT4
379 #define RRSR_6M BIT4
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| /drivers/staging/rtl8188eu/hal/ |
| H A D | odm_RTL8188E.c | 50 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
64 BIT5|BIT4|BIT3, 0);
82 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
169 phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0);
208 BIT5|BIT4|BIT3, default_ant);
217 BIT5|BIT4|BIT3, default_ant);
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| /drivers/staging/rtl8192u/ |
| H A D | r8192U_hw.h | 187 #define SCR_SKByA2 BIT4 //Search kEY BY A2
233 #define AcmHw_BeqStatus BIT4
311 #define RRSR_6M BIT4
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| /drivers/video/fbdev/via/ |
| H A D | dvi.c | 75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
340 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
361 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
|