[go: nahoru, domu]

Searched refs:REG_READ (Results 1 - 25 of 64) sorted by relevance

123

/drivers/gpu/drm/gma500/
H A Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON);
42 pp_status = REG_READ(PP_STATUS);
46 if (REG_READ(PP_STATUS) & PP_ON) {
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON);
58 pp_status = REG_READ(PP_STATUS);
H A Dcdv_device.c47 REG_READ(vga_reg);
62 if (REG_READ(SDVOB) & SDVO_DETECTED) {
64 if (REG_READ(DP_B) & DP_DETECTED)
68 if (REG_READ(SDVOC) & SDVO_DETECTED) {
70 if (REG_READ(DP_C) & DP_DETECTED)
86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
91 u32 max = REG_READ(BLC_PWM_CTL);
109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_
[all...]
H A Dmdfld_intel_display.c73 temp = REG_READ(map->conf);
101 temp = REG_READ(map->conf);
115 pfit_control = REG_READ(PFIT_CONTROL);
133 dspcntr = REG_READ(dspcntr_reg);
202 dspcntr = REG_READ(map->cntr);
225 REG_READ(map->linoff);
227 REG_READ(map->surf);
252 temp = REG_READ(map->cntr);
257 REG_WRITE(map->base, REG_READ(map->base));
258 REG_READ(ma
[all...]
H A Dgma_display.c88 dspcntr = REG_READ(map->cntr);
120 REG_READ(map->base);
123 REG_READ(map->base);
125 REG_READ(map->surf);
226 temp = REG_READ(map->dpll);
229 REG_READ(map->dpll);
233 REG_READ(map->dpll);
237 REG_READ(map->dpll);
243 temp = REG_READ(map->cntr);
248 REG_WRITE(map->base, REG_READ(ma
[all...]
H A Dintel_i2c.c39 val = REG_READ(chan->reg);
49 val = REG_READ(chan->reg);
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
H A Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL);
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL);
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
235 pp_status = REG_READ(PP_STATUS);
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
246 pp_status = REG_READ(PP_STATUS);
274 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON);
275 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF);
276 lvds_priv->saveLVDS = REG_READ(LVD
[all...]
H A Dcdv_intel_display.c143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
161 *val = REG_READ(SB_DATA);
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
212 REG_READ(DPIO_CFG);
479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
483 REG_READ(FW_BLC_SELF);
491 REG_READ(OV_OVAD
[all...]
H A Doaktrail_hdmi.c291 dpll = REG_READ(DPLL_CTRL);
307 dpll = REG_READ(DPLL_CTRL);
355 dspcntr = REG_READ(dspcntr_reg);
361 pipeconf = REG_READ(pipeconf_reg);
365 REG_READ(pipeconf_reg);
368 REG_READ(PCH_PIPEBCONF);
391 temp = REG_READ(DSPBCNTR);
394 REG_READ(DSPBCNTR);
396 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
397 REG_READ(DSPBSUR
[all...]
H A Dpsb_intel_display.c92 pfit_control = REG_READ(PFIT_CONTROL);
201 pipeconf = REG_READ(map->conf);
225 REG_READ(map->dpll);
234 u32 lvds = REG_READ(LVDS);
255 REG_READ(LVDS);
260 REG_READ(map->dpll);
267 REG_READ(map->dpll);
292 REG_READ(map->conf);
321 dpll = REG_READ(map->dpll);
323 fp = REG_READ(ma
[all...]
H A Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
59 pp_status = REG_READ(PP_STATUS);
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
70 pp_status = REG_READ(PP_STATUS);
112 lvds_port = (REG_READ(LVDS) &
174 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
187 ret = ((REG_READ(BLC_PWM_CTL) &
H A Dcdv_intel_crt.c45 temp = REG_READ(reg);
108 dpll_md = REG_READ(dpll_md_reg);
148 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN);
162 if (!(REG_READ(PORT_HOTPLUG_EN) &
169 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
H A Dmdfld_dsi_dpi.c46 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) {
63 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg)
80 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) &
98 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg)
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
158 REG_READ(dspbase_reg);
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT)
583 if (REG_READ(MIPI_INTR_STAT_RE
[all...]
H A Dmdfld_dsi_pkg_sender.c101 if ((mask & REG_READ(gen_fifo_stat_reg)) == mask)
105 DRM_ERROR("fifo is NOT empty 0x%08x\n", REG_READ(gen_fifo_stat_reg));
199 if (mask & REG_READ(intr_stat_reg))
214 intr_stat = REG_READ(intr_stat_reg);
556 if ((REG_READ(sender->mipi_intr_stat_reg) & BIT(29)))
563 while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) {
582 *(data_out + i) = REG_READ(gen_data_reg);
670 REG_READ(MIPI_PORT_CONTROL(pipe));
H A Dcdv_intel_dp.c196 pp = REG_READ(PP_CONTROL);
200 REG_READ(PP_CONTROL);
210 pp = REG_READ(PP_CONTROL);
214 REG_READ(PP_CONTROL);
229 pp = REG_READ(PP_CONTROL);
234 REG_READ(PP_CONTROL);
236 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
237 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
254 pp = REG_READ(PP_CONTROL);
267 REG_READ(PP_CONTRO
[all...]
/drivers/net/wireless/ath/
H A Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK;
151 cycles = REG_READ(ah, AR_CCCNT);
152 busy = REG_READ(ah, AR_RCCNT);
153 rx = REG_READ(ah, AR_RFCNT);
154 tx = REG_READ(ah, AR_TFCNT);
/drivers/media/usb/dvb-usb-v2/
H A Dce6230.h46 REG_READ = 0xde, /* rd e */ enumerator in enum:ce6230_cmd
/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
167 (int32_t) REG_READ(a
[all...]
H A Dar9002_mac.c43 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
44 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
46 isr = REG_READ(ah, AR_ISR);
50 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
59 isr = REG_READ(ah, AR_ISR);
65 isr2 = REG_READ(ah, AR_ISR_S2);
88 isr = REG_READ(ah, AR_ISR_RAC);
109 s0_s = REG_READ(ah, AR_ISR_S0_S);
110 s1_s = REG_READ(ah, AR_ISR_S1_S);
112 s0_s = REG_READ(a
[all...]
H A Dar9003_calib.c84 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
271 REG_READ(ah, offset_array[i]));
288 REG_READ(ah, offset_array[i]));
293 REG_READ(ah, offset_array[i]));
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
354 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
384 osdac_ch0 = (REG_READ(a
[all...]
H A Dar9003_mci.c38 if (!(REG_READ(ah, address) & bit_position)) {
70 REG_READ(ah, AR_MCI_INTERRUPT_RAW),
71 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
231 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
235 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
237 REG_READ(ah, AR_MCI_INTERRUPT_RAW));
350 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
374 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
375 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
386 mci->cont_status = REG_READ(a
[all...]
H A Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
241 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
442 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
480 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
483 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
490 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
493 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
527 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
544 regval = REG_READ(a
[all...]
H A Dar9003_mac.c195 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
198 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
200 isr = REG_READ(ah, AR_ISR);
204 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
214 isr2 = REG_READ(ah, AR_ISR_S2);
240 isr = REG_READ(ah, AR_ISR_RAC);
268 s0 = REG_READ(ah, AR_ISR_S0);
270 s1 = REG_READ(ah, AR_ISR_S1);
282 s5 = REG_READ(ah, AR_ISR_S5_S);
284 s5 = REG_READ(a
[all...]
H A Dmac.c48 return REG_READ(ah, AR_QTXDP(q));
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
114 txcfg = REG_READ(ah, AR_TXCFG);
659 reg = REG_READ(ah, AR_OBS_BUS_1);
716 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
720 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
736 REG_READ(ah, AR_CR),
737 REG_READ(ah, AR_DIAG_SW),
738 REG_READ(a
[all...]
H A Dhw.c82 if ((REG_READ(ah, reg) & mask) == val)
90 timeout, reg, REG_READ(ah, reg), mask, val);
235 val = REG_READ(ah, AR_SREV);
250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
253 val = REG_READ(ah, AR_SREV);
317 regHold[i] = REG_READ(ah, addr);
321 rdData = REG_READ(ah, addr);
332 rdData = REG_READ(ah, addr);
544 ah->WARegVal = REG_READ(ah, AR_WA);
575 ah->hw_version.phyRev = REG_READ(a
[all...]
/drivers/net/dsa/
H A Dmv88e6171.c45 ret = REG_READ(REG_PORT(i), 0x04);
58 ret = REG_READ(REG_GLOBAL, 0x00);
72 ret = REG_READ(REG_PORT(i), 0x04);
105 if (REG_READ(REG_PORT(0), 0x03) == 0x1710)
181 val = REG_READ(addr, 0x01);

Completed in 282 milliseconds

123