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android / platform / prebuilts / gcc / darwin-x86 / arm / arm-eabi-4.6 / 21b2cba584638ed5ffad8e3fd3e6808bfa299cf0 / . / lib / gcc / arm-eabi / 4.6.x-google / plugin / include / config / arm / arm.h
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Jing Yu21b2cba2012-04-24 14:08:37 -0700[diff] [blame^]1/* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
16
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26#ifndef GCC_ARM_H
27#define GCC_ARM_H
28
29/* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32#ifdef GENERATOR_FILE
33#define MACHMODE int
34#else
35#include "insn-modes.h"
36#define MACHMODE enum machine_mode
37#endif
38
39#include "config/vxworks-dummy.h"
40
41/* The architecture define. */
42extern char arm_arch_name[];
43
44/* Target CPU builtins. */
45#define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 if (TARGET_DSP_MULTIPLY) \
49 builtin_define ("__ARM_FEATURE_DSP"); \
50 /* Define __arm__ even when in thumb mode, for \
51 consistency with armcc. */ \
52 builtin_define ("__arm__"); \
53 builtin_define ("__APCS_32__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__thumb__"); \
56 if (TARGET_THUMB2) \
57 builtin_define ("__thumb2__"); \
58 \
59 if (TARGET_BIG_END) \
60 { \
61 builtin_define ("__ARMEB__"); \
62 if (TARGET_THUMB) \
63 builtin_define ("__THUMBEB__"); \
64 if (TARGET_LITTLE_WORDS) \
65 builtin_define ("__ARMWEL__"); \
66 } \
67 else \
68 { \
69 builtin_define ("__ARMEL__"); \
70 if (TARGET_THUMB) \
71 builtin_define ("__THUMBEL__"); \
72 } \
73 \
74 if (TARGET_SOFT_FLOAT) \
75 builtin_define ("__SOFTFP__"); \
76 \
77 if (TARGET_VFP) \
78 builtin_define ("__VFP_FP__"); \
79 \
80 if (TARGET_NEON) \
81 builtin_define ("__ARM_NEON__"); \
82 \
83 /* Add a define for interworking. \
84 Needed when building libgcc.a. */ \
85 if (arm_cpp_interwork) \
86 builtin_define ("__THUMB_INTERWORK__"); \
87 \
88 builtin_assert ("cpu=arm"); \
89 builtin_assert ("machine=arm"); \
90 \
91 builtin_define (arm_arch_name); \
92 if (arm_arch_cirrus) \
93 builtin_define ("__MAVERICK__"); \
94 if (arm_arch_xscale) \
95 builtin_define ("__XSCALE__"); \
96 if (arm_arch_iwmmxt) \
97 builtin_define ("__IWMMXT__"); \
98 if (TARGET_AAPCS_BASED) \
99 { \
100 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
101 builtin_define ("__ARM_PCS_VFP"); \
102 else if (arm_pcs_default == ARM_PCS_AAPCS) \
103 builtin_define ("__ARM_PCS"); \
104 builtin_define ("__ARM_EABI__"); \
105 } \
106 } while (0)
107
108/* The various ARM cores. */
109enum processor_type
110{
111#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
112 IDENT,
113#include "arm-cores.def"
114#undef ARM_CORE
115 /* Used to indicate that no processor has been specified. */
116 arm_none
117};
118
119enum target_cpus
120{
121#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
122 TARGET_CPU_##IDENT,
123#include "arm-cores.def"
124#undef ARM_CORE
125 TARGET_CPU_generic
126};
127
128/* The processor for which instructions should be scheduled. */
129extern enum processor_type arm_tune;
130
131enum arm_sync_generator_tag
132 {
133 arm_sync_generator_omn,
134 arm_sync_generator_omrn
135 };
136
137/* Wrapper to pass around a polymorphic pointer to a sync instruction
138 generator and. */
139struct arm_sync_generator
140{
141 enum arm_sync_generator_tag op;
142 union
143 {
144 rtx (* omn) (rtx, rtx, rtx);
145 rtx (* omrn) (rtx, rtx, rtx, rtx);
146 } u;
147};
148
149typedef enum arm_cond_code
150{
151 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
152 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
153}
154arm_cc;
155
156extern arm_cc arm_current_cc;
157
158#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
159
160extern int arm_target_label;
161extern int arm_ccfsm_state;
162extern GTY(()) rtx arm_target_insn;
163/* The label of the current constant pool. */
164extern rtx pool_vector_label;
165/* Set to 1 when a return insn is output, this means that the epilogue
166 is not needed. */
167extern int return_used_this_function;
168/* Callback to output language specific object attributes. */
169extern void (*arm_lang_output_object_attributes_hook)(void);
170
171/* Just in case configure has failed to define anything. */
172#ifndef TARGET_CPU_DEFAULT
173#define TARGET_CPU_DEFAULT TARGET_CPU_generic
174#endif
175
176
177#undef CPP_SPEC
178#define CPP_SPEC "%(subtarget_cpp_spec) \
179%{msoft-float:%{mhard-float: \
180 %e-msoft-float and -mhard_float may not be used together}} \
181%{mbig-endian:%{mlittle-endian: \
182 %e-mbig-endian and -mlittle-endian may not be used together}}"
183
184#ifndef CC1_SPEC
185#define CC1_SPEC ""
186#endif
187
188/* This macro defines names of additional specifications to put in the specs
189 that can be used in various specifications like CC1_SPEC. Its definition
190 is an initializer with a subgrouping for each command option.
191
192 Each subgrouping contains a string constant, that defines the
193 specification name, and a string constant that used by the GCC driver
194 program.
195
196 Do not define this macro if it does not need to do anything. */
197#define EXTRA_SPECS \
198 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
199 SUBTARGET_EXTRA_SPECS
200
201#ifndef SUBTARGET_EXTRA_SPECS
202#define SUBTARGET_EXTRA_SPECS
203#endif
204
205#ifndef SUBTARGET_CPP_SPEC
206#define SUBTARGET_CPP_SPEC ""
207#endif
208
209/* Run-time Target Specification. */
210#ifndef TARGET_VERSION
211#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
212#endif
213
214#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
215/* Use hardware floating point instructions. */
216#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
217/* Use hardware floating point calling convention. */
218#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
219#define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
220#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
221#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
222#define TARGET_IWMMXT (arm_arch_iwmmxt)
223#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
224#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
225#define TARGET_ARM (! TARGET_THUMB)
226#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
227#define TARGET_BACKTRACE (leaf_function_p () \
228 ? TARGET_TPCS_LEAF_FRAME \
229 : TARGET_TPCS_FRAME)
230#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
231#define TARGET_AAPCS_BASED \
232 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
233
234#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
235#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
236
237/* Only 16-bit thumb code. */
238#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
239/* Arm or Thumb-2 32-bit code. */
240#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
241/* 32-bit Thumb-2 code. */
242#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
243/* Thumb-1 only. */
244#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
245/* FPA emulator without LFM. */
246#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
247
248/* The following two macros concern the ability to execute coprocessor
249 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
250 only ever tested when we know we are generating for VFP hardware; we need
251 to be more careful with TARGET_NEON as noted below. */
252
253/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
254#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
255
256/* FPU supports VFPv3 instructions. */
257#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
258
259/* FPU only supports VFP single-precision instructions. */
260#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
261
262/* FPU supports VFP double-precision instructions. */
263#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
264
265/* FPU supports half-precision floating-point with NEON element load/store. */
266#define TARGET_NEON_FP16 \
267 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
268
269/* FPU supports VFP half-precision floating-point. */
270#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
271
272/* FPU supports Neon instructions. The setting of this macro gets
273 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
274 and TARGET_HARD_FLOAT to ensure that NEON instructions are
275 available. */
276#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
277 && TARGET_VFP && arm_fpu_desc->neon)
278
279/* "DSP" multiply instructions, eg. SMULxy. */
280#define TARGET_DSP_MULTIPLY \
281 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
282/* Integer SIMD instructions, and extend-accumulate instructions. */
283#define TARGET_INT_SIMD \
284 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
285
286/* Should MOVW/MOVT be used in preference to a constant pool. */
287#define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
288
289/* We could use unified syntax for arm mode, but for now we just use it
290 for Thumb-2. */
291#define TARGET_UNIFIED_ASM TARGET_THUMB2
292
293/* Nonzero if this chip provides the DMB instruction. */
294#define TARGET_HAVE_DMB (arm_arch7)
295
296/* Nonzero if this chip implements a memory barrier via CP15. */
297#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
298
299/* Nonzero if this chip implements a memory barrier instruction. */
300#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
301
302/* Nonzero if this chip supports ldrex and strex */
303#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
304
305/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
306#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
307
308/* True iff the full BPABI is being used. If TARGET_BPABI is true,
309 then TARGET_AAPCS_BASED must be true -- but the converse does not
310 hold. TARGET_BPABI implies the use of the BPABI runtime library,
311 etc., in addition to just the AAPCS calling conventions. */
312#ifndef TARGET_BPABI
313#define TARGET_BPABI false
314#endif
315
316/* Support for a compile-time default CPU, et cetera. The rules are:
317 --with-arch is ignored if -march or -mcpu are specified.
318 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
319 by --with-arch.
320 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
321 by -march).
322 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
323 specified.
324 --with-fpu is ignored if -mfpu is specified.
325 --with-abi is ignored is -mabi is specified. */
326#define OPTION_DEFAULT_SPECS \
327 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
328 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
329 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
330 {"float", \
331 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
332 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
333 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
334 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
335
336/* Which floating point model to use. */
337enum arm_fp_model
338{
339 ARM_FP_MODEL_UNKNOWN,
340 /* FPA model (Hardware or software). */
341 ARM_FP_MODEL_FPA,
342 /* Cirrus Maverick floating point model. */
343 ARM_FP_MODEL_MAVERICK,
344 /* VFP floating point model. */
345 ARM_FP_MODEL_VFP
346};
347
348enum vfp_reg_type
349{
350 VFP_NONE = 0,
351 VFP_REG_D16,
352 VFP_REG_D32,
353 VFP_REG_SINGLE
354};
355
356extern const struct arm_fpu_desc
357{
358 const char *name;
359 enum arm_fp_model model;
360 int rev;
361 enum vfp_reg_type regs;
362 int neon;
363 int fp16;
364} *arm_fpu_desc;
365
366/* Which floating point hardware to schedule for. */
367extern int arm_fpu_attr;
368
369enum float_abi_type
370{
371 ARM_FLOAT_ABI_SOFT,
372 ARM_FLOAT_ABI_SOFTFP,
373 ARM_FLOAT_ABI_HARD
374};
375
376extern enum float_abi_type arm_float_abi;
377
378#ifndef TARGET_DEFAULT_FLOAT_ABI
379#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
380#endif
381
382/* Which __fp16 format to use.
383 The enumeration values correspond to the numbering for the
384 Tag_ABI_FP_16bit_format attribute.
385 */
386enum arm_fp16_format_type
387{
388 ARM_FP16_FORMAT_NONE = 0,
389 ARM_FP16_FORMAT_IEEE = 1,
390 ARM_FP16_FORMAT_ALTERNATIVE = 2
391};
392
393extern enum arm_fp16_format_type arm_fp16_format;
394#define LARGEST_EXPONENT_IS_NORMAL(bits) \
395 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
396
397/* Which ABI to use. */
398enum arm_abi_type
399{
400 ARM_ABI_APCS,
401 ARM_ABI_ATPCS,
402 ARM_ABI_AAPCS,
403 ARM_ABI_IWMMXT,
404 ARM_ABI_AAPCS_LINUX
405};
406
407extern enum arm_abi_type arm_abi;
408
409#ifndef ARM_DEFAULT_ABI
410#define ARM_DEFAULT_ABI ARM_ABI_APCS
411#endif
412
413/* Which thread pointer access sequence to use. */
414enum arm_tp_type {
415 TP_AUTO,
416 TP_SOFT,
417 TP_CP15
418};
419
420extern enum arm_tp_type target_thread_pointer;
421
422/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
423extern int arm_arch3m;
424
425/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
426extern int arm_arch4;
427
428/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
429extern int arm_arch4t;
430
431/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
432extern int arm_arch5;
433
434/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
435extern int arm_arch5e;
436
437/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
438extern int arm_arch6;
439
440/* Nonzero if this chip supports the ARM Architecture 6k extensions. */
441extern int arm_arch6k;
442
443/* Nonzero if this chip supports the ARM Architecture 7 extensions. */
444extern int arm_arch7;
445
446/* Nonzero if instructions not present in the 'M' profile can be used. */
447extern int arm_arch_notm;
448
449/* Nonzero if instructions present in ARMv7E-M can be used. */
450extern int arm_arch7em;
451
452/* Nonzero if this chip can benefit from load scheduling. */
453extern int arm_ld_sched;
454
455/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
456extern int thumb_code;
457
458/* Nonzero if generating Thumb-1 code. */
459extern int thumb1_code;
460
461/* Nonzero if this chip is a StrongARM. */
462extern int arm_tune_strongarm;
463
464/* Nonzero if this chip is a Cirrus variant. */
465extern int arm_arch_cirrus;
466
467/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
468extern int arm_arch_iwmmxt;
469
470/* Nonzero if this chip is an XScale. */
471extern int arm_arch_xscale;
472
473/* Nonzero if tuning for XScale. */
474extern int arm_tune_xscale;
475
476/* Nonzero if tuning for stores via the write buffer. */
477extern int arm_tune_wbuf;
478
479/* Nonzero if tuning for Cortex-A9. */
480extern int arm_tune_cortex_a9;
481
482/* Nonzero if we should define __THUMB_INTERWORK__ in the
483 preprocessor.
484 XXX This is a bit of a hack, it's intended to help work around
485 problems in GLD which doesn't understand that armv5t code is
486 interworking clean. */
487extern int arm_cpp_interwork;
488
489/* Nonzero if chip supports Thumb 2. */
490extern int arm_arch_thumb2;
491
492/* Nonzero if chip supports integer division instruction. */
493extern int arm_arch_hwdiv;
494
495#ifndef TARGET_DEFAULT
496#define TARGET_DEFAULT (MASK_APCS_FRAME)
497#endif
498
499/* Nonzero if PIC code requires explicit qualifiers to generate
500 PLT and GOT relocs rather than the assembler doing so implicitly.
501 Subtargets can override these if required. */
502#ifndef NEED_GOT_RELOC
503#define NEED_GOT_RELOC 0
504#endif
505#ifndef NEED_PLT_RELOC
506#define NEED_PLT_RELOC 0
507#endif
508
509/* Nonzero if we need to refer to the GOT with a PC-relative
510 offset. In other words, generate
511
512 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
513
514 rather than
515
516 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
517
518 The default is true, which matches NetBSD. Subtargets can
519 override this if required. */
520#ifndef GOT_PCREL
521#define GOT_PCREL 1
522#endif
523
524/* Target machine storage Layout. */
525
526
527/* Define this macro if it is advisable to hold scalars in registers
528 in a wider mode than that declared by the program. In such cases,
529 the value is constrained to be within the bounds of the declared
530 type, but kept valid in the wider mode. The signedness of the
531 extension may differ from that of the type. */
532
533/* It is far faster to zero extend chars than to sign extend them */
534
535#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
536 if (GET_MODE_CLASS (MODE) == MODE_INT \
537 && GET_MODE_SIZE (MODE) < 4) \
538 { \
539 if (MODE == QImode) \
540 UNSIGNEDP = 1; \
541 else if (MODE == HImode) \
542 UNSIGNEDP = 1; \
543 (MODE) = SImode; \
544 }
545
546/* Define this if most significant bit is lowest numbered
547 in instructions that operate on numbered bit-fields. */
548#define BITS_BIG_ENDIAN 0
549
550/* Define this if most significant byte of a word is the lowest numbered.
551 Most ARM processors are run in little endian mode, so that is the default.
552 If you want to have it run-time selectable, change the definition in a
553 cover file to be TARGET_BIG_ENDIAN. */
554#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
555
556/* Define this if most significant word of a multiword number is the lowest
557 numbered.
558 This is always false, even when in big-endian mode. */
559#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
560
561/* Define this if most significant word of doubles is the lowest numbered.
562 The rules are different based on whether or not we use FPA-format,
563 VFP-format or some other floating point co-processor's format doubles. */
564#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
565
566#define UNITS_PER_WORD 4
567
568/* True if natural alignment is used for doubleword types. */
569#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
570
571#define DOUBLEWORD_ALIGNMENT 64
572
573#define PARM_BOUNDARY 32
574
575#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
576
577#define PREFERRED_STACK_BOUNDARY \
578 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
579
580#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
581
582/* The lowest bit is used to indicate Thumb-mode functions, so the
583 vbit must go into the delta field of pointers to member
584 functions. */
585#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
586
587#define EMPTY_FIELD_BOUNDARY 32
588
589#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
590
591/* XXX Blah -- this macro is used directly by libobjc. Since it
592 supports no vector modes, cut out the complexity and fall back
593 on BIGGEST_FIELD_ALIGNMENT. */
594#ifdef IN_TARGET_LIBS
595#define BIGGEST_FIELD_ALIGNMENT 64
596#endif
597
598/* Make strings word-aligned so strcpy from constants will be faster. */
599#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
600
601#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
602 ((TREE_CODE (EXP) == STRING_CST \
603 && !optimize_size \
604 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
605 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
606
607/* Align definitions of arrays, unions and structures so that
608 initializations and copies can be made more efficient. This is not
609 ABI-changing, so it only affects places where we can see the
610 definition. Increasing the alignment tends to introduce padding,
611 so don't do this when optimizing for size/conserving stack space. */
612#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
613 (((COND) && ((ALIGN) < BITS_PER_WORD) \
614 && (TREE_CODE (EXP) == ARRAY_TYPE \
615 || TREE_CODE (EXP) == UNION_TYPE \
616 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
617
618/* Align global data. */
619#define DATA_ALIGNMENT(EXP, ALIGN) \
620 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
621
622/* Similarly, make sure that objects on the stack are sensibly aligned. */
623#define LOCAL_ALIGNMENT(EXP, ALIGN) \
624 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
625
626/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
627 value set in previous versions of this toolchain was 8, which produces more
628 compact structures. The command line option -mstructure_size_boundary=<n>
629 can be used to change this value. For compatibility with the ARM SDK
630 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
631 0020D) page 2-20 says "Structures are aligned on word boundaries".
632 The AAPCS specifies a value of 8. */
633#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
634extern int arm_structure_size_boundary;
635
636/* This is the value used to initialize arm_structure_size_boundary. If a
637 particular arm target wants to change the default value it should change
638 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
639 for an example of this. */
640#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
641#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
642#endif
643
644/* Nonzero if move instructions will actually fail to work
645 when given unaligned data. */
646#define STRICT_ALIGNMENT 1
647
648/* wchar_t is unsigned under the AAPCS. */
649#ifndef WCHAR_TYPE
650#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
651
652#define WCHAR_TYPE_SIZE BITS_PER_WORD
653#endif
654
655#ifndef SIZE_TYPE
656#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
657#endif
658
659#ifndef PTRDIFF_TYPE
660#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
661#endif
662
663/* AAPCS requires that structure alignment is affected by bitfields. */
664#ifndef PCC_BITFIELD_TYPE_MATTERS
665#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
666#endif
667
668
669/* Standard register usage. */
670
671/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
672 (S - saved over call).
673
674 r0 * argument word/integer result
675 r1-r3 argument word
676
677 r4-r8 S register variable
678 r9 S (rfp) register variable (real frame pointer)
679
680 r10 F S (sl) stack limit (used by -mapcs-stack-check)
681 r11 F S (fp) argument pointer
682 r12 (ip) temp workspace
683 r13 F S (sp) lower end of current stack frame
684 r14 (lr) link address/workspace
685 r15 F (pc) program counter
686
687 f0 floating point result
688 f1-f3 floating point scratch
689
690 f4-f7 S floating point variable
691
692 cc This is NOT a real register, but is used internally
693 to represent things that use or set the condition
694 codes.
695 sfp This isn't either. It is used during rtl generation
696 since the offset between the frame pointer and the
697 auto's isn't known until after register allocation.
698 afp Nor this, we only need this because of non-local
699 goto. Without it fp appears to be used and the
700 elimination code won't get rid of sfp. It tracks
701 fp exactly at all times.
702
703 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
704
705/*
706 mvf0 Cirrus floating point result
707 mvf1-mvf3 Cirrus floating point scratch
708 mvf4-mvf15 S Cirrus floating point variable. */
709
710/* s0-s15 VFP scratch (aka d0-d7).
711 s16-s31 S VFP variable (aka d8-d15).
712 vfpcc Not a real register. Represents the VFP condition
713 code flags. */
714
715/* The stack backtrace structure is as follows:
716 fp points to here: | save code pointer | [fp]
717 | return link value | [fp, #-4]
718 | return sp value | [fp, #-8]
719 | return fp value | [fp, #-12]
720 [| saved r10 value |]
721 [| saved r9 value |]
722 [| saved r8 value |]
723 [| saved r7 value |]
724 [| saved r6 value |]
725 [| saved r5 value |]
726 [| saved r4 value |]
727 [| saved r3 value |]
728 [| saved r2 value |]
729 [| saved r1 value |]
730 [| saved r0 value |]
731 [| saved f7 value |] three words
732 [| saved f6 value |] three words
733 [| saved f5 value |] three words
734 [| saved f4 value |] three words
735 r0-r3 are not normally saved in a C function. */
736
737/* 1 for registers that have pervasive standard uses
738 and are not available for the register allocator. */
739#define FIXED_REGISTERS \
740{ \
741 0,0,0,0,0,0,0,0, \
742 0,0,0,0,0,1,0,1, \
743 0,0,0,0,0,0,0,0, \
744 1,1,1, \
745 1,1,1,1,1,1,1,1, \
746 1,1,1,1,1,1,1,1, \
747 1,1,1,1,1,1,1,1, \
748 1,1,1,1,1,1,1,1, \
749 1,1,1,1, \
750 1,1,1,1,1,1,1,1, \
751 1,1,1,1,1,1,1,1, \
752 1,1,1,1,1,1,1,1, \
753 1,1,1,1,1,1,1,1, \
754 1,1,1,1,1,1,1,1, \
755 1,1,1,1,1,1,1,1, \
756 1,1,1,1,1,1,1,1, \
757 1,1,1,1,1,1,1,1, \
758 1 \
759}
760
761/* 1 for registers not available across function calls.
762 These must include the FIXED_REGISTERS and also any
763 registers that can be used without being saved.
764 The latter must include the registers where values are returned
765 and the register where structure-value addresses are passed.
766 Aside from that, you can include as many other registers as you like.
767 The CC is not preserved over function calls on the ARM 6, so it is
768 easier to assume this for all. SFP is preserved, since FP is. */
769#define CALL_USED_REGISTERS \
770{ \
771 1,1,1,1,0,0,0,0, \
772 0,0,0,0,1,1,1,1, \
773 1,1,1,1,0,0,0,0, \
774 1,1,1, \
775 1,1,1,1,1,1,1,1, \
776 1,1,1,1,1,1,1,1, \
777 1,1,1,1,1,1,1,1, \
778 1,1,1,1,1,1,1,1, \
779 1,1,1,1, \
780 1,1,1,1,1,1,1,1, \
781 1,1,1,1,1,1,1,1, \
782 1,1,1,1,1,1,1,1, \
783 1,1,1,1,1,1,1,1, \
784 1,1,1,1,1,1,1,1, \
785 1,1,1,1,1,1,1,1, \
786 1,1,1,1,1,1,1,1, \
787 1,1,1,1,1,1,1,1, \
788 1 \
789}
790
791#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
792#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
793#endif
794
795/* These are a couple of extensions to the formats accepted
796 by asm_fprintf:
797 %@ prints out ASM_COMMENT_START
798 %r prints out REGISTER_PREFIX reg_names[arg] */
799#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
800 case '@': \
801 fputs (ASM_COMMENT_START, FILE); \
802 break; \
803 \
804 case 'r': \
805 fputs (REGISTER_PREFIX, FILE); \
806 fputs (reg_names [va_arg (ARGS, int)], FILE); \
807 break;
808
809/* Round X up to the nearest word. */
810#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
811
812/* Convert fron bytes to ints. */
813#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
814
815/* The number of (integer) registers required to hold a quantity of type MODE.
816 Also used for VFP registers. */
817#define ARM_NUM_REGS(MODE) \
818 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
819
820/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
821#define ARM_NUM_REGS2(MODE, TYPE) \
822 ARM_NUM_INTS ((MODE) == BLKmode ? \
823 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
824
825/* The number of (integer) argument register available. */
826#define NUM_ARG_REGS 4
827
828/* And similarly for the VFP. */
829#define NUM_VFP_ARG_REGS 16
830
831/* Return the register number of the N'th (integer) argument. */
832#define ARG_REGISTER(N) (N - 1)
833
834/* Specify the registers used for certain standard purposes.
835 The values of these macros are register numbers. */
836
837/* The number of the last argument register. */
838#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
839
840/* The numbers of the Thumb register ranges. */
841#define FIRST_LO_REGNUM 0
842#define LAST_LO_REGNUM 7
843#define FIRST_HI_REGNUM 8
844#define LAST_HI_REGNUM 11
845
846/* Overridden by config/arm/bpabi.h. */
847#ifndef ARM_UNWIND_INFO
848#define ARM_UNWIND_INFO 0
849#endif
850
851/* Use r0 and r1 to pass exception handling information. */
852#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
853
854/* The register that holds the return address in exception handlers. */
855#define ARM_EH_STACKADJ_REGNUM 2
856#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
857
858/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
859 as an invisible last argument (possible since varargs don't exist in
860 Pascal), so the following is not true. */
861#define STATIC_CHAIN_REGNUM 12
862
863/* Define this to be where the real frame pointer is if it is not possible to
864 work out the offset between the frame pointer and the automatic variables
865 until after register allocation has taken place. FRAME_POINTER_REGNUM
866 should point to a special register that we will make sure is eliminated.
867
868 For the Thumb we have another problem. The TPCS defines the frame pointer
869 as r11, and GCC believes that it is always possible to use the frame pointer
870 as base register for addressing purposes. (See comments in
871 find_reloads_address()). But - the Thumb does not allow high registers,
872 including r11, to be used as base address registers. Hence our problem.
873
874 The solution used here, and in the old thumb port is to use r7 instead of
875 r11 as the hard frame pointer and to have special code to generate
876 backtrace structures on the stack (if required to do so via a command line
877 option) using r11. This is the only 'user visible' use of r11 as a frame
878 pointer. */
879#define ARM_HARD_FRAME_POINTER_REGNUM 11
880#define THUMB_HARD_FRAME_POINTER_REGNUM 7
881
882#define HARD_FRAME_POINTER_REGNUM \
883 (TARGET_ARM \
884 ? ARM_HARD_FRAME_POINTER_REGNUM \
885 : THUMB_HARD_FRAME_POINTER_REGNUM)
886
887#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
888#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
889
890#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
891
892/* Register to use for pushing function arguments. */
893#define STACK_POINTER_REGNUM SP_REGNUM
894
895/* ARM floating pointer registers. */
896#define FIRST_FPA_REGNUM 16
897#define LAST_FPA_REGNUM 23
898#define IS_FPA_REGNUM(REGNUM) \
899 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
900
901#define FIRST_IWMMXT_GR_REGNUM 43
902#define LAST_IWMMXT_GR_REGNUM 46
903#define FIRST_IWMMXT_REGNUM 47
904#define LAST_IWMMXT_REGNUM 62
905#define IS_IWMMXT_REGNUM(REGNUM) \
906 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
907#define IS_IWMMXT_GR_REGNUM(REGNUM) \
908 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
909
910/* Base register for access to local variables of the function. */
911#define FRAME_POINTER_REGNUM 25
912
913/* Base register for access to arguments of the function. */
914#define ARG_POINTER_REGNUM 26
915
916#define FIRST_CIRRUS_FP_REGNUM 27
917#define LAST_CIRRUS_FP_REGNUM 42
918#define IS_CIRRUS_REGNUM(REGNUM) \
919 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
920
921#define FIRST_VFP_REGNUM 63
922#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
923#define LAST_VFP_REGNUM \
924 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
925
926#define IS_VFP_REGNUM(REGNUM) \
927 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
928
929/* VFP registers are split into two types: those defined by VFP versions < 3
930 have D registers overlaid on consecutive pairs of S registers. VFP version 3
931 defines 16 new D registers (d16-d31) which, for simplicity and correctness
932 in various parts of the backend, we implement as "fake" single-precision
933 registers (which would be S32-S63, but cannot be used in that way). The
934 following macros define these ranges of registers. */
935#define LAST_LO_VFP_REGNUM 94
936#define FIRST_HI_VFP_REGNUM 95
937#define LAST_HI_VFP_REGNUM 126
938
939#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
940 ((REGNUM) <= LAST_LO_VFP_REGNUM)
941
942/* DFmode values are only valid in even register pairs. */
943#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
944 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
945
946/* Neon Quad values must start at a multiple of four registers. */
947#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
948 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
949
950/* Neon structures of vectors must be in even register pairs and there
951 must be enough registers available. Because of various patterns
952 requiring quad registers, we require them to start at a multiple of
953 four. */
954#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
955 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
956 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
957
958/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
959/* + 16 Cirrus registers take us up to 43. */
960/* Intel Wireless MMX Technology registers add 16 + 4 more. */
961/* VFP (VFP3) adds 32 (64) + 1 more. */
962#define FIRST_PSEUDO_REGISTER 128
963
964#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
965
966/* Value should be nonzero if functions must have frame pointers.
967 Zero means the frame pointer need not be set up (and parms may be accessed
968 via the stack pointer) in functions that seem suitable.
969 If we have to have a frame pointer we might as well make use of it.
970 APCS says that the frame pointer does not need to be pushed in leaf
971 functions, or simple tail call functions. */
972
973#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
974#define SUBTARGET_FRAME_POINTER_REQUIRED 0
975#endif
976
977/* Return number of consecutive hard regs needed starting at reg REGNO
978 to hold something of mode MODE.
979 This is ordinarily the length in words of a value of mode MODE
980 but can be less for certain modes in special long registers.
981
982 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
983 mode. */
984#define HARD_REGNO_NREGS(REGNO, MODE) \
985 ((TARGET_32BIT \
986 && REGNO >= FIRST_FPA_REGNUM \
987 && REGNO != FRAME_POINTER_REGNUM \
988 && REGNO != ARG_POINTER_REGNUM) \
989 && !IS_VFP_REGNUM (REGNO) \
990 ? 1 : ARM_NUM_REGS (MODE))
991
992/* Return true if REGNO is suitable for holding a quantity of type MODE. */
993#define HARD_REGNO_MODE_OK(REGNO, MODE) \
994 arm_hard_regno_mode_ok ((REGNO), (MODE))
995
996/* Value is 1 if it is a good idea to tie two pseudo registers
997 when one has mode MODE1 and one has mode MODE2.
998 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
999 for any hard reg, then this must be 0 for correct output. */
1000#define MODES_TIEABLE_P(MODE1, MODE2) \
1001 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1002
1003#define VALID_IWMMXT_REG_MODE(MODE) \
1004 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1005
1006/* Modes valid for Neon D registers. */
1007#define VALID_NEON_DREG_MODE(MODE) \
1008 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1009 || (MODE) == V2SFmode || (MODE) == DImode)
1010
1011/* Modes valid for Neon Q registers. */
1012#define VALID_NEON_QREG_MODE(MODE) \
1013 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1014 || (MODE) == V4SFmode || (MODE) == V2DImode)
1015
1016/* Structure modes valid for Neon registers. */
1017#define VALID_NEON_STRUCT_MODE(MODE) \
1018 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1019 || (MODE) == CImode || (MODE) == XImode)
1020
1021/* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1022extern int arm_regs_in_sequence[];
1023
1024/* The order in which register should be allocated. It is good to use ip
1025 since no saving is required (though calls clobber it) and it never contains
1026 function parameters. It is quite good to use lr since other calls may
1027 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1028 least likely to contain a function parameter; in addition results are
1029 returned in r0.
1030 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1031 then D8-D15. The reason for doing this is to attempt to reduce register
1032 pressure when both single- and double-precision registers are used in a
1033 function. */
1034
1035#define REG_ALLOC_ORDER \
1036{ \
1037 3, 2, 1, 0, 12, 14, 4, 5, \
1038 6, 7, 8, 10, 9, 11, 13, 15, \
1039 16, 17, 18, 19, 20, 21, 22, 23, \
1040 27, 28, 29, 30, 31, 32, 33, 34, \
1041 35, 36, 37, 38, 39, 40, 41, 42, \
1042 43, 44, 45, 46, 47, 48, 49, 50, \
1043 51, 52, 53, 54, 55, 56, 57, 58, \
1044 59, 60, 61, 62, \
1045 24, 25, 26, \
1046 95, 96, 97, 98, 99, 100, 101, 102, \
1047 103, 104, 105, 106, 107, 108, 109, 110, \
1048 111, 112, 113, 114, 115, 116, 117, 118, \
1049 119, 120, 121, 122, 123, 124, 125, 126, \
1050 78, 77, 76, 75, 74, 73, 72, 71, \
1051 70, 69, 68, 67, 66, 65, 64, 63, \
1052 79, 80, 81, 82, 83, 84, 85, 86, \
1053 87, 88, 89, 90, 91, 92, 93, 94, \
1054 127 \
1055}
1056
1057/* Use different register alloc ordering for Thumb. */
1058#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1059
1060/* Tell IRA to use the order we define rather than messing it up with its
1061 own cost calculations. */
1062#define HONOR_REG_ALLOC_ORDER
1063
1064/* Interrupt functions can only use registers that have already been
1065 saved by the prologue, even if they would normally be
1066 call-clobbered. */
1067#define HARD_REGNO_RENAME_OK(SRC, DST) \
1068 (! IS_INTERRUPT (cfun->machine->func_type) || \
1069 df_regs_ever_live_p (DST))
1070
1071/* Register and constant classes. */
1072
1073/* Register classes: used to be simple, just all ARM regs or all FPA regs
1074 Now that the Thumb is involved it has become more complicated. */
1075enum reg_class
1076{
1077 NO_REGS,
1078 FPA_REGS,
1079 CIRRUS_REGS,
1080 VFP_D0_D7_REGS,
1081 VFP_LO_REGS,
1082 VFP_HI_REGS,
1083 VFP_REGS,
1084 IWMMXT_GR_REGS,
1085 IWMMXT_REGS,
1086 LO_REGS,
1087 STACK_REG,
1088 BASE_REGS,
1089 HI_REGS,
1090 CC_REG,
1091 VFPCC_REG,
1092 GENERAL_REGS,
1093 CORE_REGS,
1094 ALL_REGS,
1095 LIM_REG_CLASSES
1096};
1097
1098#define N_REG_CLASSES (int) LIM_REG_CLASSES
1099
1100/* Give names of register classes as strings for dump file. */
1101#define REG_CLASS_NAMES \
1102{ \
1103 "NO_REGS", \
1104 "FPA_REGS", \
1105 "CIRRUS_REGS", \
1106 "VFP_D0_D7_REGS", \
1107 "VFP_LO_REGS", \
1108 "VFP_HI_REGS", \
1109 "VFP_REGS", \
1110 "IWMMXT_GR_REGS", \
1111 "IWMMXT_REGS", \
1112 "LO_REGS", \
1113 "STACK_REG", \
1114 "BASE_REGS", \
1115 "HI_REGS", \
1116 "CC_REG", \
1117 "VFPCC_REG", \
1118 "GENERAL_REGS", \
1119 "CORE_REGS", \
1120 "ALL_REGS", \
1121}
1122
1123/* Define which registers fit in which classes.
1124 This is an initializer for a vector of HARD_REG_SET
1125 of length N_REG_CLASSES. */
1126#define REG_CLASS_CONTENTS \
1127{ \
1128 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1129 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1130 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1131 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1132 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1133 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1134 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1135 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1136 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1137 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1138 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1139 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1140 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1141 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1142 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1143 { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1144 { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1145 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1146}
1147
1148/* Any of the VFP register classes. */
1149#define IS_VFP_CLASS(X) \
1150 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1151 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1152
1153/* The same information, inverted:
1154 Return the class number of the smallest class containing
1155 reg number REGNO. This could be a conditional expression
1156 or could index an array. */
1157#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1158
1159/* The following macro defines cover classes for Integrated Register
1160 Allocator. Cover classes is a set of non-intersected register
1161 classes covering all hard registers used for register allocation
1162 purpose. Any move between two registers of a cover class should be
1163 cheaper than load or store of the registers. The macro value is
1164 array of register classes with LIM_REG_CLASSES used as the end
1165 marker. */
1166
1167#define IRA_COVER_CLASSES \
1168{ \
1169 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1170 LIM_REG_CLASSES \
1171}
1172
1173/* FPA registers can't do subreg as all values are reformatted to internal
1174 precision. VFP registers may only be accessed in the mode they
1175 were set. */
1176#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1177 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1178 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1179 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1180 : 0)
1181
1182/* The class value for index registers, and the one for base regs. */
1183#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1184#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1185
1186/* For the Thumb the high registers cannot be used as base registers
1187 when addressing quantities in QI or HI mode; if we don't know the
1188 mode, then we must be conservative. */
1189#define MODE_BASE_REG_CLASS(MODE) \
1190 (TARGET_32BIT ? CORE_REGS : \
1191 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1192
1193/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1194 instead of BASE_REGS. */
1195#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1196
1197/* When this hook returns true for MODE, the compiler allows
1198 registers explicitly used in the rtl to be used as spill registers
1199 but prevents the compiler from extending the lifetime of these
1200 registers. */
1201#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1202 arm_small_register_classes_for_mode_p
1203
1204/* Given an rtx X being reloaded into a reg required to be
1205 in class CLASS, return the class of reg to actually use.
1206 In general this is just CLASS, but for the Thumb core registers and
1207 immediate constants we prefer a LO_REGS class or a subset. */
1208#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1209 (TARGET_32BIT ? (CLASS) : \
1210 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1211 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1212 ? LO_REGS : (CLASS)))
1213
1214/* Must leave BASE_REGS reloads alone */
1215#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1216 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1217 ? ((true_regnum (X) == -1 ? LO_REGS \
1218 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1219 : NO_REGS)) \
1220 : NO_REGS)
1221
1222#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1223 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1224 ? ((true_regnum (X) == -1 ? LO_REGS \
1225 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1226 : NO_REGS)) \
1227 : NO_REGS)
1228
1229/* Return the register class of a scratch register needed to copy IN into
1230 or out of a register in CLASS in MODE. If it can be done directly,
1231 NO_REGS is returned. */
1232#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1233 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1234 ((TARGET_VFP && TARGET_HARD_FLOAT \
1235 && IS_VFP_CLASS (CLASS)) \
1236 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1237 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1238 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1239 : TARGET_32BIT \
1240 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1241 ? GENERAL_REGS : NO_REGS) \
1242 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1243
1244/* If we need to load shorts byte-at-a-time, then we need a scratch. */
1245#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1246 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1247 ((TARGET_VFP && TARGET_HARD_FLOAT \
1248 && IS_VFP_CLASS (CLASS)) \
1249 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1250 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1251 coproc_secondary_reload_class (MODE, X, TRUE) : \
1252 /* Cannot load constants into Cirrus registers. */ \
1253 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1254 && (CLASS) == CIRRUS_REGS \
1255 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1256 ? GENERAL_REGS : \
1257 (TARGET_32BIT ? \
1258 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1259 && CONSTANT_P (X)) \
1260 ? GENERAL_REGS : \
1261 (((MODE) == HImode && ! arm_arch4 \
1262 && (GET_CODE (X) == MEM \
1263 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1264 && true_regnum (X) == -1))) \
1265 ? GENERAL_REGS : NO_REGS) \
1266 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1267
1268/* Try a machine-dependent way of reloading an illegitimate address
1269 operand. If we find one, push the reload and jump to WIN. This
1270 macro is used in only one place: `find_reloads_address' in reload.c.
1271
1272 For the ARM, we wish to handle large displacements off a base
1273 register by splitting the addend across a MOV and the mem insn.
1274 This can cut the number of reloads needed. */
1275#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1276 do \
1277 { \
1278 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1279 goto WIN; \
1280 } \
1281 while (0)
1282
1283/* XXX If an HImode FP+large_offset address is converted to an HImode
1284 SP+large_offset address, then reload won't know how to fix it. It sees
1285 only that SP isn't valid for HImode, and so reloads the SP into an index
1286 register, but the resulting address is still invalid because the offset
1287 is too big. We fix it here instead by reloading the entire address. */
1288/* We could probably achieve better results by defining PROMOTE_MODE to help
1289 cope with the variances between the Thumb's signed and unsigned byte and
1290 halfword load instructions. */
1291/* ??? This should be safe for thumb2, but we may be able to do better. */
1292#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1293do { \
1294 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1295 if (new_x) \
1296 { \
1297 X = new_x; \
1298 goto WIN; \
1299 } \
1300} while (0)
1301
1302#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1303 if (TARGET_ARM) \
1304 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1305 else \
1306 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1307
1308/* Return the maximum number of consecutive registers
1309 needed to represent mode MODE in a register of class CLASS.
1310 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1311#define CLASS_MAX_NREGS(CLASS, MODE) \
1312 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1313
1314/* If defined, gives a class of registers that cannot be used as the
1315 operand of a SUBREG that changes the mode of the object illegally. */
1316
1317/* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1318 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1319 it is typically more expensive than a single memory access. We set
1320 the cost to less than two memory accesses so that floating
1321 point to integer conversion does not go through memory. */
1322#define REGISTER_MOVE_COST(MODE, FROM, TO) \
1323 (TARGET_32BIT ? \
1324 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1325 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1326 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1327 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1328 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1329 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1330 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1331 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1332 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1333 2) \
1334 : \
1335 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1336
1337/* Stack layout; function entry, exit and calling. */
1338
1339/* Define this if pushing a word on the stack
1340 makes the stack pointer a smaller address. */
1341#define STACK_GROWS_DOWNWARD 1
1342
1343/* Define this to nonzero if the nominal address of the stack frame
1344 is at the high-address end of the local variables;
1345 that is, each additional local variable allocated
1346 goes at a more negative offset in the frame. */
1347#define FRAME_GROWS_DOWNWARD 1
1348
1349/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1350 When present, it is one word in size, and sits at the top of the frame,
1351 between the soft frame pointer and either r7 or r11.
1352
1353 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1354 and only then if some outgoing arguments are passed on the stack. It would
1355 be tempting to also check whether the stack arguments are passed by indirect
1356 calls, but there seems to be no reason in principle why a post-reload pass
1357 couldn't convert a direct call into an indirect one. */
1358#define CALLER_INTERWORKING_SLOT_SIZE \
1359 (TARGET_CALLER_INTERWORKING \
1360 && crtl->outgoing_args_size != 0 \
1361 ? UNITS_PER_WORD : 0)
1362
1363/* Offset within stack frame to start allocating local variables at.
1364 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1365 first local allocated. Otherwise, it is the offset to the BEGINNING
1366 of the first local allocated. */
1367#define STARTING_FRAME_OFFSET 0
1368
1369/* If we generate an insn to push BYTES bytes,
1370 this says how many the stack pointer really advances by. */
1371/* The push insns do not do this rounding implicitly.
1372 So don't define this. */
1373/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1374
1375/* Define this if the maximum size of all the outgoing args is to be
1376 accumulated and pushed during the prologue. The amount can be
1377 found in the variable crtl->outgoing_args_size. */
1378#define ACCUMULATE_OUTGOING_ARGS 1
1379
1380/* Offset of first parameter from the argument pointer register value. */
1381#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1382
1383/* Define how to find the value returned by a library function
1384 assuming the value has mode MODE. */
1385#define LIBCALL_VALUE(MODE) \
1386 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1387 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1388 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1389 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1390 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1391 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1392 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1393 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1394 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1395 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1396
1397/* 1 if REGNO is a possible register number for a function value. */
1398#define FUNCTION_VALUE_REGNO_P(REGNO) \
1399 ((REGNO) == ARG_REGISTER (1) \
1400 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1401 && TARGET_VFP && TARGET_HARD_FLOAT \
1402 && (REGNO) == FIRST_VFP_REGNUM) \
1403 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1404 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1405 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1406 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1407 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1408
1409/* Amount of memory needed for an untyped call to save all possible return
1410 registers. */
1411#define APPLY_RESULT_SIZE arm_apply_result_size()
1412
1413/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1414 values must be in memory. On the ARM, they need only do so if larger
1415 than a word, or if they contain elements offset from zero in the struct. */
1416#define DEFAULT_PCC_STRUCT_RETURN 0
1417
1418/* These bits describe the different types of function supported
1419 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1420 normal function and an interworked function, for example. Knowing the
1421 type of a function is important for determining its prologue and
1422 epilogue sequences.
1423 Note value 7 is currently unassigned. Also note that the interrupt
1424 function types all have bit 2 set, so that they can be tested for easily.
1425 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1426 machine_function structure is initialized (to zero) func_type will
1427 default to unknown. This will force the first use of arm_current_func_type
1428 to call arm_compute_func_type. */
1429#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1430#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1431#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1432#define ARM_FT_ISR 4 /* An interrupt service routine. */
1433#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1434#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1435
1436#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1437
1438/* In addition functions can have several type modifiers,
1439 outlined by these bit masks: */
1440#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1441#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1442#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1443#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1444#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1445
1446/* Some macros to test these flags. */
1447#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1448#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1449#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1450#define IS_NAKED(t) (t & ARM_FT_NAKED)
1451#define IS_NESTED(t) (t & ARM_FT_NESTED)
1452#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1453
1454
1455/* Structure used to hold the function stack frame layout. Offsets are
1456 relative to the stack pointer on function entry. Positive offsets are
1457 in the direction of stack growth.
1458 Only soft_frame is used in thumb mode. */
1459
1460typedef struct GTY(()) arm_stack_offsets
1461{
1462 int saved_args; /* ARG_POINTER_REGNUM. */
1463 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1464 int saved_regs;
1465 int soft_frame; /* FRAME_POINTER_REGNUM. */
1466 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1467 int outgoing_args; /* STACK_POINTER_REGNUM. */
1468 unsigned int saved_regs_mask;
1469}
1470arm_stack_offsets;
1471
1472#ifndef GENERATOR_FILE
1473/* A C structure for machine-specific, per-function data.
1474 This is added to the cfun structure. */
1475typedef struct GTY(()) machine_function
1476{
1477 /* Additional stack adjustment in __builtin_eh_throw. */
1478 rtx eh_epilogue_sp_ofs;
1479 /* Records if LR has to be saved for far jumps. */
1480 int far_jump_used;
1481 /* Records if ARG_POINTER was ever live. */
1482 int arg_pointer_live;
1483 /* Records if the save of LR has been eliminated. */
1484 int lr_save_eliminated;
1485 /* The size of the stack frame. Only valid after reload. */
1486 arm_stack_offsets stack_offsets;
1487 /* Records the type of the current function. */
1488 unsigned long func_type;
1489 /* Record if the function has a variable argument list. */
1490 int uses_anonymous_args;
1491 /* Records if sibcalls are blocked because an argument
1492 register is needed to preserve stack alignment. */
1493 int sibcall_blocked;
1494 /* The PIC register for this function. This might be a pseudo. */
1495 rtx pic_reg;
1496 /* Labels for per-function Thumb call-via stubs. One per potential calling
1497 register. We can never call via LR or PC. We can call via SP if a
1498 trampoline happens to be on the top of the stack. */
1499 rtx call_via[14];
1500 /* Set to 1 when a return insn is output, this means that the epilogue
1501 is not needed. */
1502 int return_used_this_function;
1503 /* When outputting Thumb-1 code, record the last insn that provides
1504 information about condition codes, and the comparison operands. */
1505 rtx thumb1_cc_insn;
1506 rtx thumb1_cc_op0;
1507 rtx thumb1_cc_op1;
1508 /* Also record the CC mode that is supported. */
1509 enum machine_mode thumb1_cc_mode;
1510}
1511machine_function;
1512#endif
1513
1514/* As in the machine_function, a global set of call-via labels, for code
1515 that is in text_section. */
1516extern GTY(()) rtx thumb_call_via_label[14];
1517
1518/* The number of potential ways of assigning to a co-processor. */
1519#define ARM_NUM_COPROC_SLOTS 1
1520
1521/* Enumeration of procedure calling standard variants. We don't really
1522 support all of these yet. */
1523enum arm_pcs
1524{
1525 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1526 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1527 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1528 /* This must be the last AAPCS variant. */
1529 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1530 ARM_PCS_ATPCS, /* ATPCS. */
1531 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1532 ARM_PCS_UNKNOWN
1533};
1534
1535/* Default procedure calling standard of current compilation unit. */
1536extern enum arm_pcs arm_pcs_default;
1537
1538/* A C type for declaring a variable that is used as the first argument of
1539 `FUNCTION_ARG' and other related values. */
1540typedef struct
1541{
1542 /* This is the number of registers of arguments scanned so far. */
1543 int nregs;
1544 /* This is the number of iWMMXt register arguments scanned so far. */
1545 int iwmmxt_nregs;
1546 int named_count;
1547 int nargs;
1548 /* Which procedure call variant to use for this call. */
1549 enum arm_pcs pcs_variant;
1550
1551 /* AAPCS related state tracking. */
1552 int aapcs_arg_processed; /* No need to lay out this argument again. */
1553 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1554 this argument, or -1 if using core
1555 registers. */
1556 int aapcs_ncrn;
1557 int aapcs_next_ncrn;
1558 rtx aapcs_reg; /* Register assigned to this argument. */
1559 int aapcs_partial; /* How many bytes are passed in regs (if
1560 split between core regs and stack.
1561 Zero otherwise. */
1562 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1563 int can_split; /* Argument can be split between core regs
1564 and the stack. */
1565 /* Private data for tracking VFP register allocation */
1566 unsigned aapcs_vfp_regs_free;
1567 unsigned aapcs_vfp_reg_alloc;
1568 int aapcs_vfp_rcount;
1569 MACHMODE aapcs_vfp_rmode;
1570} CUMULATIVE_ARGS;
1571
1572#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1573 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1574
1575#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1576 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1577
1578/* For AAPCS, padding should never be below the argument. For other ABIs,
1579 * mimic the default. */
1580#define PAD_VARARGS_DOWN \
1581 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1582
1583/* Initialize a variable CUM of type CUMULATIVE_ARGS
1584 for a call to a function whose data type is FNTYPE.
1585 For a library call, FNTYPE is 0.
1586 On the ARM, the offset starts at 0. */
1587#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1588 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1589
1590/* 1 if N is a possible register number for function argument passing.
1591 On the ARM, r0-r3 are used to pass args. */
1592#define FUNCTION_ARG_REGNO_P(REGNO) \
1593 (IN_RANGE ((REGNO), 0, 3) \
1594 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1595 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1596 || (TARGET_IWMMXT_ABI \
1597 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1598
1599
1600/* If your target environment doesn't prefix user functions with an
1601 underscore, you may wish to re-define this to prevent any conflicts. */
1602#ifndef ARM_MCOUNT_NAME
1603#define ARM_MCOUNT_NAME "*mcount"
1604#endif
1605
1606/* Call the function profiler with a given profile label. The Acorn
1607 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1608 On the ARM the full profile code will look like:
1609 .data
1610 LP1
1611 .word 0
1612 .text
1613 mov ip, lr
1614 bl mcount
1615 .word LP1
1616
1617 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1618 will output the .text section.
1619
1620 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1621 ``prof'' doesn't seem to mind about this!
1622
1623 Note - this version of the code is designed to work in both ARM and
1624 Thumb modes. */
1625#ifndef ARM_FUNCTION_PROFILER
1626#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1627{ \
1628 char temp[20]; \
1629 rtx sym; \
1630 \
1631 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1632 IP_REGNUM, LR_REGNUM); \
1633 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1634 fputc ('\n', STREAM); \
1635 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1636 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1637 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1638}
1639#endif
1640
1641#ifdef THUMB_FUNCTION_PROFILER
1642#define FUNCTION_PROFILER(STREAM, LABELNO) \
1643 if (TARGET_ARM) \
1644 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1645 else \
1646 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1647#else
1648#define FUNCTION_PROFILER(STREAM, LABELNO) \
1649 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1650#endif
1651
1652/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1653 the stack pointer does not matter. The value is tested only in
1654 functions that have frame pointers.
1655 No definition is equivalent to always zero.
1656
1657 On the ARM, the function epilogue recovers the stack pointer from the
1658 frame. */
1659#define EXIT_IGNORE_STACK 1
1660
1661#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1662
1663/* Determine if the epilogue should be output as RTL.
1664 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1665#define USE_RETURN_INSN(ISCOND) \
1666 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1667
1668/* Definitions for register eliminations.
1669
1670 This is an array of structures. Each structure initializes one pair
1671 of eliminable registers. The "from" register number is given first,
1672 followed by "to". Eliminations of the same "from" register are listed
1673 in order of preference.
1674
1675 We have two registers that can be eliminated on the ARM. First, the
1676 arg pointer register can often be eliminated in favor of the stack
1677 pointer register. Secondly, the pseudo frame pointer register can always
1678 be eliminated; it is replaced with either the stack or the real frame
1679 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1680 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1681
1682#define ELIMINABLE_REGS \
1683{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1684 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1685 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1686 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1687 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1688 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1689 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1690
1691/* Define the offset between two registers, one to be eliminated, and the
1692 other its replacement, at the start of a routine. */
1693#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1694 if (TARGET_ARM) \
1695 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1696 else \
1697 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1698
1699/* Special case handling of the location of arguments passed on the stack. */
1700#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1701
1702/* Initialize data used by insn expanders. This is called from insn_emit,
1703 once for every function before code is generated. */
1704#define INIT_EXPANDERS arm_init_expanders ()
1705
1706/* Length in units of the trampoline for entering a nested function. */
1707#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1708
1709/* Alignment required for a trampoline in bits. */
1710#define TRAMPOLINE_ALIGNMENT 32
1711
1712/* Addressing modes, and classification of registers for them. */
1713#define HAVE_POST_INCREMENT 1
1714#define HAVE_PRE_INCREMENT TARGET_32BIT
1715#define HAVE_POST_DECREMENT TARGET_32BIT
1716#define HAVE_PRE_DECREMENT TARGET_32BIT
1717#define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1718#define HAVE_POST_MODIFY_DISP TARGET_32BIT
1719#define HAVE_PRE_MODIFY_REG TARGET_32BIT
1720#define HAVE_POST_MODIFY_REG TARGET_32BIT
1721
1722/* Macros to check register numbers against specific register classes. */
1723
1724/* These assume that REGNO is a hard or pseudo reg number.
1725 They give nonzero only if REGNO is a hard reg of the suitable class
1726 or a pseudo reg currently allocated to a suitable hard reg.
1727 Since they use reg_renumber, they are safe only once reg_renumber
1728 has been allocated, which happens in local-alloc.c. */
1729#define TEST_REGNO(R, TEST, VALUE) \
1730 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1731
1732/* Don't allow the pc to be used. */
1733#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1734 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1735 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1736 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1737
1738#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1739 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1740 || (GET_MODE_SIZE (MODE) >= 4 \
1741 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1742
1743#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1744 (TARGET_THUMB1 \
1745 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1746 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1747
1748/* Nonzero if X can be the base register in a reg+reg addressing mode.
1749 For Thumb, we can not use SP + reg, so reject SP. */
1750#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1751 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1752
1753/* For ARM code, we don't care about the mode, but for Thumb, the index
1754 must be suitable for use in a QImode load. */
1755#define REGNO_OK_FOR_INDEX_P(REGNO) \
1756 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1757 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1758
1759/* Maximum number of registers that can appear in a valid memory address.
1760 Shifts in addresses can't be by a register. */
1761#define MAX_REGS_PER_ADDRESS 2
1762
1763/* Recognize any constant value that is a valid address. */
1764/* XXX We can address any constant, eventually... */
1765/* ??? Should the TARGET_ARM here also apply to thumb2? */
1766#define CONSTANT_ADDRESS_P(X) \
1767 (GET_CODE (X) == SYMBOL_REF \
1768 && (CONSTANT_POOL_ADDRESS_P (X) \
1769 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1770
1771/* True if SYMBOL + OFFSET constants must refer to something within
1772 SYMBOL's section. */
1773#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1774
1775/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1776#ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1777#define TARGET_DEFAULT_WORD_RELOCATIONS 0
1778#endif
1779
1780/* Nonzero if the constant value X is a legitimate general operand.
1781 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1782
1783 On the ARM, allow any integer (invalid ones are removed later by insn
1784 patterns), nice doubles and symbol_refs which refer to the function's
1785 constant pool XXX.
1786
1787 When generating pic allow anything. */
1788#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1789
1790#define THUMB_LEGITIMATE_CONSTANT_P(X) \
1791 ( GET_CODE (X) == CONST_INT \
1792 || GET_CODE (X) == CONST_DOUBLE \
1793 || CONSTANT_ADDRESS_P (X) \
1794 || flag_pic)
1795
1796#define LEGITIMATE_CONSTANT_P(X) \
1797 (!arm_cannot_force_const_mem (X) \
1798 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1799 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1800
1801#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1802#define SUBTARGET_NAME_ENCODING_LENGTHS
1803#endif
1804
1805/* This is a C fragment for the inside of a switch statement.
1806 Each case label should return the number of characters to
1807 be stripped from the start of a function's name, if that
1808 name starts with the indicated character. */
1809#define ARM_NAME_ENCODING_LENGTHS \
1810 case '*': return 1; \
1811 SUBTARGET_NAME_ENCODING_LENGTHS
1812
1813/* This is how to output a reference to a user-level label named NAME.
1814 `assemble_name' uses this. */
1815#undef ASM_OUTPUT_LABELREF
1816#define ASM_OUTPUT_LABELREF(FILE, NAME) \
1817 arm_asm_output_labelref (FILE, NAME)
1818
1819/* Output IT instructions for conditionally executed Thumb-2 instructions. */
1820#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1821 if (TARGET_THUMB2) \
1822 thumb2_asm_output_opcode (STREAM);
1823
1824/* The EABI specifies that constructors should go in .init_array.
1825 Other targets use .ctors for compatibility. */
1826#ifndef ARM_EABI_CTORS_SECTION_OP
1827#define ARM_EABI_CTORS_SECTION_OP \
1828 "\t.section\t.init_array,\"aw\",%init_array"
1829#endif
1830#ifndef ARM_EABI_DTORS_SECTION_OP
1831#define ARM_EABI_DTORS_SECTION_OP \
1832 "\t.section\t.fini_array,\"aw\",%fini_array"
1833#endif
1834#define ARM_CTORS_SECTION_OP \
1835 "\t.section\t.ctors,\"aw\",%progbits"
1836#define ARM_DTORS_SECTION_OP \
1837 "\t.section\t.dtors,\"aw\",%progbits"
1838
1839/* Define CTORS_SECTION_ASM_OP. */
1840#undef CTORS_SECTION_ASM_OP
1841#undef DTORS_SECTION_ASM_OP
1842#ifndef IN_LIBGCC2
1843# define CTORS_SECTION_ASM_OP \
1844 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1845# define DTORS_SECTION_ASM_OP \
1846 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1847#else /* !defined (IN_LIBGCC2) */
1848/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1849 so we cannot use the definition above. */
1850# ifdef __ARM_EABI__
1851/* The .ctors section is not part of the EABI, so we do not define
1852 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1853 from trying to use it. We do define it when doing normal
1854 compilation, as .init_array can be used instead of .ctors. */
1855/* There is no need to emit begin or end markers when using
1856 init_array; the dynamic linker will compute the size of the
1857 array itself based on special symbols created by the static
1858 linker. However, we do need to arrange to set up
1859 exception-handling here. */
1860# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1861# define CTOR_LIST_END /* empty */
1862# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1863# define DTOR_LIST_END /* empty */
1864# else /* !defined (__ARM_EABI__) */
1865# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1866# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1867# endif /* !defined (__ARM_EABI__) */
1868#endif /* !defined (IN_LIBCC2) */
1869
1870/* True if the operating system can merge entities with vague linkage
1871 (e.g., symbols in COMDAT group) during dynamic linking. */
1872#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1873#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1874#endif
1875
1876#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1877
1878/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1879 and check its validity for a certain class.
1880 We have two alternate definitions for each of them.
1881 The usual definition accepts all pseudo regs; the other rejects
1882 them unless they have been allocated suitable hard regs.
1883 The symbol REG_OK_STRICT causes the latter definition to be used.
1884 Thumb-2 has the same restrictions as arm. */
1885#ifndef REG_OK_STRICT
1886
1887#define ARM_REG_OK_FOR_BASE_P(X) \
1888 (REGNO (X) <= LAST_ARM_REGNUM \
1889 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1890 || REGNO (X) == FRAME_POINTER_REGNUM \
1891 || REGNO (X) == ARG_POINTER_REGNUM)
1892
1893#define ARM_REG_OK_FOR_INDEX_P(X) \
1894 ((REGNO (X) <= LAST_ARM_REGNUM \
1895 && REGNO (X) != STACK_POINTER_REGNUM) \
1896 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1897 || REGNO (X) == FRAME_POINTER_REGNUM \
1898 || REGNO (X) == ARG_POINTER_REGNUM)
1899
1900#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1901 (REGNO (X) <= LAST_LO_REGNUM \
1902 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1903 || (GET_MODE_SIZE (MODE) >= 4 \
1904 && (REGNO (X) == STACK_POINTER_REGNUM \
1905 || (X) == hard_frame_pointer_rtx \
1906 || (X) == arg_pointer_rtx)))
1907
1908#define REG_STRICT_P 0
1909
1910#else /* REG_OK_STRICT */
1911
1912#define ARM_REG_OK_FOR_BASE_P(X) \
1913 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1914
1915#define ARM_REG_OK_FOR_INDEX_P(X) \
1916 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1917
1918#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1919 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1920
1921#define REG_STRICT_P 1
1922
1923#endif /* REG_OK_STRICT */
1924
1925/* Now define some helpers in terms of the above. */
1926
1927#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1928 (TARGET_THUMB1 \
1929 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1930 : ARM_REG_OK_FOR_BASE_P (X))
1931
1932/* For 16-bit Thumb, a valid index register is anything that can be used in
1933 a byte load instruction. */
1934#define THUMB1_REG_OK_FOR_INDEX_P(X) \
1935 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1936
1937/* Nonzero if X is a hard reg that can be used as an index
1938 or if it is a pseudo reg. On the Thumb, the stack pointer
1939 is not suitable. */
1940#define REG_OK_FOR_INDEX_P(X) \
1941 (TARGET_THUMB1 \
1942 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1943 : ARM_REG_OK_FOR_INDEX_P (X))
1944
1945/* Nonzero if X can be the base register in a reg+reg addressing mode.
1946 For Thumb, we can not use SP + reg, so reject SP. */
1947#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1948 REG_OK_FOR_INDEX_P (X)
1949
1950#define ARM_BASE_REGISTER_RTX_P(X) \
1951 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1952
1953#define ARM_INDEX_REGISTER_RTX_P(X) \
1954 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1955
1956/* Specify the machine mode that this machine uses
1957 for the index in the tablejump instruction. */
1958#define CASE_VECTOR_MODE Pmode
1959
1960#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
1961 || (TARGET_THUMB1 \
1962 && (optimize_size || flag_pic)))
1963
1964#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
1965 (TARGET_THUMB1 \
1966 ? (min >= 0 && max < 512 \
1967 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
1968 : min >= -256 && max < 256 \
1969 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
1970 : min >= 0 && max < 8192 \
1971 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
1972 : min >= -4096 && max < 4096 \
1973 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
1974 : SImode) \
1975 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
1976 : (max >= 0x200) ? HImode \
1977 : QImode))
1978
1979/* signed 'char' is most compatible, but RISC OS wants it unsigned.
1980 unsigned is probably best, but may break some code. */
1981#ifndef DEFAULT_SIGNED_CHAR
1982#define DEFAULT_SIGNED_CHAR 0
1983#endif
1984
1985/* Max number of bytes we can move from memory to memory
1986 in one reasonably fast instruction. */
1987#define MOVE_MAX 4
1988
1989#undef MOVE_RATIO
1990#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
1991
1992/* Define if operations between registers always perform the operation
1993 on the full register even if a narrower mode is specified. */
1994#define WORD_REGISTER_OPERATIONS
1995
1996/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1997 will either zero-extend or sign-extend. The value of this macro should
1998 be the code that says which one of the two operations is implicitly
1999 done, UNKNOWN if none. */
2000#define LOAD_EXTEND_OP(MODE) \
2001 (TARGET_THUMB ? ZERO_EXTEND : \
2002 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2003 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2004
2005/* Nonzero if access to memory by bytes is slow and undesirable. */
2006#define SLOW_BYTE_ACCESS 0
2007
2008#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2009
2010/* Immediate shift counts are truncated by the output routines (or was it
2011 the assembler?). Shift counts in a register are truncated by ARM. Note
2012 that the native compiler puts too large (> 32) immediate shift counts
2013 into a register and shifts by the register, letting the ARM decide what
2014 to do instead of doing that itself. */
2015/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2016 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2017 On the arm, Y in a register is used modulo 256 for the shift. Only for
2018 rotates is modulo 32 used. */
2019/* #define SHIFT_COUNT_TRUNCATED 1 */
2020
2021/* All integers have the same format so truncation is easy. */
2022#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2023
2024/* Calling from registers is a massive pain. */
2025#define NO_FUNCTION_CSE 1
2026
2027/* The machine modes of pointers and functions */
2028#define Pmode SImode
2029#define FUNCTION_MODE Pmode
2030
2031#define ARM_FRAME_RTX(X) \
2032 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2033 || (X) == arg_pointer_rtx)
2034
2035/* Moves to and from memory are quite expensive */
2036#define MEMORY_MOVE_COST(M, CLASS, IN) \
2037 (TARGET_32BIT ? 10 : \
2038 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2039 * (CLASS == LO_REGS ? 1 : 2)))
2040
2041/* Try to generate sequences that don't involve branches, we can then use
2042 conditional instructions */
2043#define BRANCH_COST(speed_p, predictable_p) \
2044 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2045
2046/* Position Independent Code. */
2047/* We decide which register to use based on the compilation options and
2048 the assembler in use; this is more general than the APCS restriction of
2049 using sb (r9) all the time. */
2050extern unsigned arm_pic_register;
2051
2052/* The register number of the register used to address a table of static
2053 data addresses in memory. */
2054#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2055
2056/* We can't directly access anything that contains a symbol,
2057 nor can we indirect via the constant pool. One exception is
2058 UNSPEC_TLS, which is always PIC. */
2059#define LEGITIMATE_PIC_OPERAND_P(X) \
2060 (!(symbol_mentioned_p (X) \
2061 || label_mentioned_p (X) \
2062 || (GET_CODE (X) == SYMBOL_REF \
2063 && CONSTANT_POOL_ADDRESS_P (X) \
2064 && (symbol_mentioned_p (get_pool_constant (X)) \
2065 || label_mentioned_p (get_pool_constant (X))))) \
2066 || tls_mentioned_p (X))
2067
2068/* We need to know when we are making a constant pool; this determines
2069 whether data needs to be in the GOT or can be referenced via a GOT
2070 offset. */
2071extern int making_const_table;
2072
2073/* Handle pragmas for compatibility with Intel's compilers. */
2074/* Also abuse this to register additional C specific EABI attributes. */
2075#define REGISTER_TARGET_PRAGMAS() do { \
2076 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2077 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2078 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2079 arm_lang_object_attributes_init(); \
2080} while (0)
2081
2082/* Condition code information. */
2083/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2084 return the mode to be used for the comparison. */
2085
2086#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2087
2088#define REVERSIBLE_CC_MODE(MODE) 1
2089
2090#define REVERSE_CONDITION(CODE,MODE) \
2091 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2092 ? reverse_condition_maybe_unordered (code) \
2093 : reverse_condition (code))
2094
2095#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2096 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2097
2098/* The arm5 clz instruction returns 32. */
2099#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2100#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2101
2102#define CC_STATUS_INIT \
2103 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2104
2105#undef ASM_APP_OFF
2106#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2107 TARGET_THUMB2 ? "\t.thumb\n" : "")
2108
2109/* Output a push or a pop instruction (only used when profiling).
2110 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2111 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2112 that r7 isn't used by the function profiler, so we can use it as a
2113 scratch reg. WARNING: This isn't safe in the general case! It may be
2114 sensitive to future changes in final.c:profile_function. */
2115#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2116 do \
2117 { \
2118 if (TARGET_ARM) \
2119 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2120 STACK_POINTER_REGNUM, REGNO); \
2121 else if (TARGET_THUMB1 \
2122 && (REGNO) == STATIC_CHAIN_REGNUM) \
2123 { \
2124 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2125 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2126 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2127 } \
2128 else \
2129 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2130 } while (0)
2131
2132
2133/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2134#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2135 do \
2136 { \
2137 if (TARGET_ARM) \
2138 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2139 STACK_POINTER_REGNUM, REGNO); \
2140 else if (TARGET_THUMB1 \
2141 && (REGNO) == STATIC_CHAIN_REGNUM) \
2142 { \
2143 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2144 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2145 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2146 } \
2147 else \
2148 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2149 } while (0)
2150
2151/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2152#define ADDR_VEC_ALIGN(JUMPTABLE) 0
2153
2154/* This is how to output a label which precedes a jumptable. Since
2155 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2156#undef ASM_OUTPUT_CASE_LABEL
2157#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2158 do \
2159 { \
2160 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2161 ASM_OUTPUT_ALIGN (FILE, 2); \
2162 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2163 } \
2164 while (0)
2165
2166/* Make sure subsequent insns are aligned after a TBB. */
2167#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2168 do \
2169 { \
2170 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2171 ASM_OUTPUT_ALIGN (FILE, 1); \
2172 } \
2173 while (0)
2174
2175#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2176 do \
2177 { \
2178 if (TARGET_THUMB) \
2179 { \
2180 if (is_called_in_ARM_mode (DECL) \
2181 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2182 && cfun->is_thunk)) \
2183 fprintf (STREAM, "\t.code 32\n") ; \
2184 else if (TARGET_THUMB1) \
2185 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2186 else \
2187 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2188 } \
2189 if (TARGET_POKE_FUNCTION_NAME) \
2190 arm_poke_function_name (STREAM, (const char *) NAME); \
2191 } \
2192 while (0)
2193
2194/* For aliases of functions we use .thumb_set instead. */
2195#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2196 do \
2197 { \
2198 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2199 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2200 \
2201 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2202 { \
2203 fprintf (FILE, "\t.thumb_set "); \
2204 assemble_name (FILE, LABEL1); \
2205 fprintf (FILE, ","); \
2206 assemble_name (FILE, LABEL2); \
2207 fprintf (FILE, "\n"); \
2208 } \
2209 else \
2210 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2211 } \
2212 while (0)
2213
2214#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2215/* To support -falign-* switches we need to use .p2align so
2216 that alignment directives in code sections will be padded
2217 with no-op instructions, rather than zeroes. */
2218#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2219 if ((LOG) != 0) \
2220 { \
2221 if ((MAX_SKIP) == 0) \
2222 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2223 else \
2224 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2225 (int) (LOG), (int) (MAX_SKIP)); \
2226 }
2227#endif
2228
2229/* Add two bytes to the length of conditionally executed Thumb-2
2230 instructions for the IT instruction. */
2231#define ADJUST_INSN_LENGTH(insn, length) \
2232 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2233 length += 2;
2234
2235/* Only perform branch elimination (by making instructions conditional) if
2236 we're optimizing. For Thumb-2 check if any IT instructions need
2237 outputting. */
2238#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2239 if (TARGET_ARM && optimize) \
2240 arm_final_prescan_insn (INSN); \
2241 else if (TARGET_THUMB2) \
2242 thumb2_final_prescan_insn (INSN); \
2243 else if (TARGET_THUMB1) \
2244 thumb1_final_prescan_insn (INSN)
2245
2246#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2247 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2248 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2249 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2250 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2251 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2252 : 0))))
2253
2254/* A C expression whose value is RTL representing the value of the return
2255 address for the frame COUNT steps up from the current frame. */
2256
2257#define RETURN_ADDR_RTX(COUNT, FRAME) \
2258 arm_return_addr (COUNT, FRAME)
2259
2260/* Mask of the bits in the PC that contain the real return address
2261 when running in 26-bit mode. */
2262#define RETURN_ADDR_MASK26 (0x03fffffc)
2263
2264/* Pick up the return address upon entry to a procedure. Used for
2265 dwarf2 unwind information. This also enables the table driven
2266 mechanism. */
2267#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2268#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2269
2270/* Used to mask out junk bits from the return address, such as
2271 processor state, interrupt status, condition codes and the like. */
2272#define MASK_RETURN_ADDR \
2273 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2274 in 26 bit mode, the condition codes must be masked out of the \
2275 return address. This does not apply to ARM6 and later processors \
2276 when running in 32 bit mode. */ \
2277 ((arm_arch4 || TARGET_THUMB) \
2278 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2279 : arm_gen_return_addr_mask ())
2280
2281
2282/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2283 symbolic names defined here (which would require too much duplication).
2284 FIXME? */
2285enum arm_builtins
2286{
2287 ARM_BUILTIN_GETWCX,
2288 ARM_BUILTIN_SETWCX,
2289
2290 ARM_BUILTIN_WZERO,
2291
2292 ARM_BUILTIN_WAVG2BR,
2293 ARM_BUILTIN_WAVG2HR,
2294 ARM_BUILTIN_WAVG2B,
2295 ARM_BUILTIN_WAVG2H,
2296
2297 ARM_BUILTIN_WACCB,
2298 ARM_BUILTIN_WACCH,
2299 ARM_BUILTIN_WACCW,
2300
2301 ARM_BUILTIN_WMACS,
2302 ARM_BUILTIN_WMACSZ,
2303 ARM_BUILTIN_WMACU,
2304 ARM_BUILTIN_WMACUZ,
2305
2306 ARM_BUILTIN_WSADB,
2307 ARM_BUILTIN_WSADBZ,
2308 ARM_BUILTIN_WSADH,
2309 ARM_BUILTIN_WSADHZ,
2310
2311 ARM_BUILTIN_WALIGN,
2312
2313 ARM_BUILTIN_TMIA,
2314 ARM_BUILTIN_TMIAPH,
2315 ARM_BUILTIN_TMIABB,
2316 ARM_BUILTIN_TMIABT,
2317 ARM_BUILTIN_TMIATB,
2318 ARM_BUILTIN_TMIATT,
2319
2320 ARM_BUILTIN_TMOVMSKB,
2321 ARM_BUILTIN_TMOVMSKH,
2322 ARM_BUILTIN_TMOVMSKW,
2323
2324 ARM_BUILTIN_TBCSTB,
2325 ARM_BUILTIN_TBCSTH,
2326 ARM_BUILTIN_TBCSTW,
2327
2328 ARM_BUILTIN_WMADDS,
2329 ARM_BUILTIN_WMADDU,
2330
2331 ARM_BUILTIN_WPACKHSS,
2332 ARM_BUILTIN_WPACKWSS,
2333 ARM_BUILTIN_WPACKDSS,
2334 ARM_BUILTIN_WPACKHUS,
2335 ARM_BUILTIN_WPACKWUS,
2336 ARM_BUILTIN_WPACKDUS,
2337
2338 ARM_BUILTIN_WADDB,
2339 ARM_BUILTIN_WADDH,
2340 ARM_BUILTIN_WADDW,
2341 ARM_BUILTIN_WADDSSB,
2342 ARM_BUILTIN_WADDSSH,
2343 ARM_BUILTIN_WADDSSW,
2344 ARM_BUILTIN_WADDUSB,
2345 ARM_BUILTIN_WADDUSH,
2346 ARM_BUILTIN_WADDUSW,
2347 ARM_BUILTIN_WSUBB,
2348 ARM_BUILTIN_WSUBH,
2349 ARM_BUILTIN_WSUBW,
2350 ARM_BUILTIN_WSUBSSB,
2351 ARM_BUILTIN_WSUBSSH,
2352 ARM_BUILTIN_WSUBSSW,
2353 ARM_BUILTIN_WSUBUSB,
2354 ARM_BUILTIN_WSUBUSH,
2355 ARM_BUILTIN_WSUBUSW,
2356
2357 ARM_BUILTIN_WAND,
2358 ARM_BUILTIN_WANDN,
2359 ARM_BUILTIN_WOR,
2360 ARM_BUILTIN_WXOR,
2361
2362 ARM_BUILTIN_WCMPEQB,
2363 ARM_BUILTIN_WCMPEQH,
2364 ARM_BUILTIN_WCMPEQW,
2365 ARM_BUILTIN_WCMPGTUB,
2366 ARM_BUILTIN_WCMPGTUH,
2367 ARM_BUILTIN_WCMPGTUW,
2368 ARM_BUILTIN_WCMPGTSB,
2369 ARM_BUILTIN_WCMPGTSH,
2370 ARM_BUILTIN_WCMPGTSW,
2371
2372 ARM_BUILTIN_TEXTRMSB,
2373 ARM_BUILTIN_TEXTRMSH,
2374 ARM_BUILTIN_TEXTRMSW,
2375 ARM_BUILTIN_TEXTRMUB,
2376 ARM_BUILTIN_TEXTRMUH,
2377 ARM_BUILTIN_TEXTRMUW,
2378 ARM_BUILTIN_TINSRB,
2379 ARM_BUILTIN_TINSRH,
2380 ARM_BUILTIN_TINSRW,
2381
2382 ARM_BUILTIN_WMAXSW,
2383 ARM_BUILTIN_WMAXSH,
2384 ARM_BUILTIN_WMAXSB,
2385 ARM_BUILTIN_WMAXUW,
2386 ARM_BUILTIN_WMAXUH,
2387 ARM_BUILTIN_WMAXUB,
2388 ARM_BUILTIN_WMINSW,
2389 ARM_BUILTIN_WMINSH,
2390 ARM_BUILTIN_WMINSB,
2391 ARM_BUILTIN_WMINUW,
2392 ARM_BUILTIN_WMINUH,
2393 ARM_BUILTIN_WMINUB,
2394
2395 ARM_BUILTIN_WMULUM,
2396 ARM_BUILTIN_WMULSM,
2397 ARM_BUILTIN_WMULUL,
2398
2399 ARM_BUILTIN_PSADBH,
2400 ARM_BUILTIN_WSHUFH,
2401
2402 ARM_BUILTIN_WSLLH,
2403 ARM_BUILTIN_WSLLW,
2404 ARM_BUILTIN_WSLLD,
2405 ARM_BUILTIN_WSRAH,
2406 ARM_BUILTIN_WSRAW,
2407 ARM_BUILTIN_WSRAD,
2408 ARM_BUILTIN_WSRLH,
2409 ARM_BUILTIN_WSRLW,
2410 ARM_BUILTIN_WSRLD,
2411 ARM_BUILTIN_WRORH,
2412 ARM_BUILTIN_WRORW,
2413 ARM_BUILTIN_WRORD,
2414 ARM_BUILTIN_WSLLHI,
2415 ARM_BUILTIN_WSLLWI,
2416 ARM_BUILTIN_WSLLDI,
2417 ARM_BUILTIN_WSRAHI,
2418 ARM_BUILTIN_WSRAWI,
2419 ARM_BUILTIN_WSRADI,
2420 ARM_BUILTIN_WSRLHI,
2421 ARM_BUILTIN_WSRLWI,
2422 ARM_BUILTIN_WSRLDI,
2423 ARM_BUILTIN_WRORHI,
2424 ARM_BUILTIN_WRORWI,
2425 ARM_BUILTIN_WRORDI,
2426
2427 ARM_BUILTIN_WUNPCKIHB,
2428 ARM_BUILTIN_WUNPCKIHH,
2429 ARM_BUILTIN_WUNPCKIHW,
2430 ARM_BUILTIN_WUNPCKILB,
2431 ARM_BUILTIN_WUNPCKILH,
2432 ARM_BUILTIN_WUNPCKILW,
2433
2434 ARM_BUILTIN_WUNPCKEHSB,
2435 ARM_BUILTIN_WUNPCKEHSH,
2436 ARM_BUILTIN_WUNPCKEHSW,
2437 ARM_BUILTIN_WUNPCKEHUB,
2438 ARM_BUILTIN_WUNPCKEHUH,
2439 ARM_BUILTIN_WUNPCKEHUW,
2440 ARM_BUILTIN_WUNPCKELSB,
2441 ARM_BUILTIN_WUNPCKELSH,
2442 ARM_BUILTIN_WUNPCKELSW,
2443 ARM_BUILTIN_WUNPCKELUB,
2444 ARM_BUILTIN_WUNPCKELUH,
2445 ARM_BUILTIN_WUNPCKELUW,
2446
2447 ARM_BUILTIN_THREAD_POINTER,
2448
2449 ARM_BUILTIN_NEON_BASE,
2450
2451 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2452};
2453
2454/* Do emit .note.GNU-stack by default. */
2455#ifndef NEED_INDICATE_EXEC_STACK
2456#define NEED_INDICATE_EXEC_STACK 1
2457#endif
2458
2459/* The maximum number of parallel loads or stores we support in an ldm/stm
2460 instruction. */
2461#define MAX_LDM_STM_OPS 4
2462
2463#endif /* ! GCC_ARM_H */