MOSFET

Example of a MOSFET

The metal oxide semiconductor field-effect transistor (MOSFET), is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET. (The 'metal' in the name is an anachronism from early chips where gates were metal; modern chips use polysilicon gates, but are still called MOSFETs).

Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably IBM, have begun to use a mixture of silicon and germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good gate oxides and thus are not suitable for MOSFETs. IGFET is a related term meaning insulated-gate field-effect transistor, and is almost synonymous with "MOSFET", though it can refer to FETs with a gate insulator that is not oxide.

The gate terminal is a layer of polysilicon (polycrystalline silicon; why polysilicon is used will be explained below) placed over the channel, but separated from the channel by a thin insulating layer of what was traditionally silicon dioxide, but more advanced technologies used silicon oxynitride. When a voltage is applied between the gate and source terminals, the electric field generated penetrates through the oxide and creates a so-called "inversion channel" in the channel underneath. The inversion channel is of the same type—p-type or n-type—as the source and drain, so it provides a conduit through which current can pass. Varying the voltage between the gate and body modulates the conductivity of this layer and makes it possible to control the current flow between drain and source.

Circuit symbols

Enhancement-mode MOSFET symbols

A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back into the same direction as the channel. Sometimes a broken line is used for enhancement mode and a solid one for depletion mode, but the awkwardness of drawing broken lines means this distinction is often ignored. Another line is drawn parallel to the channel for the gate.

The bulk connection, if shown, is shown connected to the back of the channel with an arrow indicating PMOS or NMOS. Arrows always point from P to N, so an NMOS (N-channel) has the arrow pointing in. If the bulk is connected to the source (as is generally the case with discrete devices) it is angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS.

MOSFET operation

Metal Oxide Semiconductor structure

Metal Oxide Semiconductor structure

A Metal Oxide Semiconductor (MOS) structure is obtained by depositing a layer of Silicon dioxide ($SiO_{2}$) and a layer of metal (polycristalline silicon is actually used instead of metal) on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a plane capacitor, with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with $N_{A}$ the density of holes), a positive $V_{GB}$ (see figure) tends to reduce the concentration of holes and increase the concentration of electrons. If $V_{GB}$ is high enough, the concentration of negative charge carriers is more than that of positive charges.

MOSFET Structure

Cross Section of an NMOS

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is based on the modulation of charge concentration caused by a MOS capacitance. It is basically constituted of two electrodes (source and drain) each connected to a highly doped N region. These two regions are separated by a P-doped zone. This latter zone constitutes a MOS capacitance with a third electrode (the gate), located above.

When a positive Gate-Body voltage is applied, it creates a N-channel at the surface of the P region, just under the oxide. This channel spreads from the source to the drain and provides conductivity of the transistor. When no or a negative voltage is applied between gate and body, the channel disappears and the transistor blocated.

Body Effect

The body effect describes the changes in the threshold voltage by the change in the source-bulk voltage, using the following equation.

$V_{TN}=V_{TO}+\gamma ({\sqrt {(}}V_{SB}+2\phi )+{\sqrt {(}}2\phi ))$,

where $V_{TO}$ is the zero substrate bias, $\gamma$ is the body effect parameter, and $2\phi$ is the surface potential parameter.

The body can be operating as a second gate. (http://equars.com/~marco/poli/phd/node20.html)

Modes of Operation

Evolution of the drain current of a MOSFET with the drain-to-source voltage for several $V_{GS}-V_{th}$ values.

Cross section of a MOSFET operating in the linear region

Cross section of a MOSFET operating in the saturation region

The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. For an enhancement mode, n-channel MOSFET the modes are:

1. Cut-off or sub-threshold mode: When $V_{GS}<V_{th}$ where $V_{th}$ is the threshold voltage of the device.

The transistor is turned off, and there is no conduction between drain and source. While the current between drain and source should ideally be zero since the switch is turned off, there is a weak-inversion current, or subthreshold leakage.

2. Triode or linear region: When $V_{GS}>V_{th}$ and $V_{DS}<V_{GS}-V_{th}$

The transistor is turned on, and a channel has been created which allows current to flow between the drain and source. The MOSFET operates like a resistor, controlled by the gate voltage. The current from drain to source is,
$I_{D}={\frac {\mu _{n}C_{ox}}{2}}{\frac {W}{L}}(2(V_{GS}-V_{th})V_{DS}-V_{DS}^{2})$

where $\mu _{n}$ is the charge-carrier mobility, $W$ is the gate width, $L$ is the gate length and $C_{ox}$ is the capacitance at the gate.

3. Saturation: When $V_{GS}>V_{th}$ and $V_{DS}>V_{GS}-V_{th}$

The switch is turned on, and a channel has been created which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, a portion of the channel is turned off. The onset of this region is also known as pinch-off. The drain current is now relatively independent of the drain voltage (in a first-order approximation) and the current is only controlled by the gate voltage such that,
$I_{D}={\frac {\mu _{n}C_{ox}}{2}}{\frac {W}{L}}(V_{GS}-V_{th})^{2}$

this equation can be multiplied by $(1+\lambda V_{DS})$ to take into account the channel length modulation ($\lambda$).

In digital circuits MOSFETs are operated in cut-off and linear mode. The saturation mode is mainly used in analog circuit applications

The primacy of MOSFETs

In 1960, Martin Atalla at Bell Labs invented the metal oxide semiconductor field-effect transistor (MOSFET). Theoretically different from Shockley's transistor, the MOSFET was structured by putting an insulating layer on the surface of the semiconductor and then placing a metallic gate electrode on that. It used crystalline silicon for the semiconductor and a thermally oxidized layer of silicon dioxide for the insulator. Not only did it possess such technical attractions as low cost of production and ease of integration, the silicon MOSFET serendipitously did not generate localized electron traps (interface states) at the interface between the silicon and its native oxide layer, and thus was free of the characteristic that had impeded the performance of earlier transistors. Buoyed by this stroke of good fortune, the MOSFET has achieved electronic hegemony. It is this serendipity that sustains the large-scale integrated circuits (LSIs) underlying today's information society.

The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor. The principal reason for the success of the MOSFET was the development of digital CMOS logic, (see article on CMOS) which uses p- and n-channel MOSFETs as building blocks. The great advantage of CMOS logic is that they allow no current to flow (ideally), and thus no power to be consumed, except when the inputs to logic gates are being switched. CMOS accomplishes this by complementing every nMOSFET with a pMOSFET and connecting both gates in such a way that whenever one is conducting, the other is not. This arrangement greatly reduces power consumption and heat generation. Overheating is a major concern in integrated circuits, since ever more transistors are packed into ever smaller chips.

Another advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic state from earlier and consequent stages, which allows to drive a considerable number of MOSFET inputs from a single MOSFET output. Bipolar transistor-based logics (such as TTL) do not have such a high fanout capacity. This isolation also makes it easier for the designers to ignore to some extent loading effects between logic stages independently. That extent is defined by the operating frequency: as frequencies increase, the input impedance of the MOSFETs decreases.

The MOSFET's strengths as the workhorse transistor in most digital circuits do not translate into supremacy in analog circuits. The bipolar junction transistor (BJT) has traditionally been the analog designer's transistor of choice, due largely to its high transconductance and unique properties. Nevertheless, MOSFETs are widely relied upon for analog purposes as well. One advantage of MOSFETs is that due to their positive temperature coefficient, they do not suffer from thermal runaway as BJTs do. Some analog circuits are designed solely using MOSFETs in a fabrication process specialized for digital circuits because it is advantageous to incorporate digital and analog circuits onto the same chip and digital fabrication processes are less expensive. Fabrication processes exist that incorporate BJTs and MOSFETs onto the same die, these mixed-transistor circuits are called BiCMOS (bipolar-CMOS) circuits. Ironically, the BJT has some advantages over the MOSFET in certain digital circuits; digital circuit designs can incorporate BJTs to speed signals in critical locations.

MOSFET scaling

Over the past decades, the MOSFET has continually been scaled down in size; typical MOSFET channel lengths were once several micrometres, but modern integrated circuits are incorporating MOSFETs with channel lengths of less than a tenth of a micrometre. Indeed Intel will begin production of a process featuring a 65nm channel length in early 2006. Until the late 1990s, this size reduction resulted in great improvement to MOSFET operation with no deleterious consequences. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process.

Reasons for MOSFET scaling

Smaller MOSFETs are desirable for three reasons. First, smaller MOSFETs allow more current to pass. Conceptually, MOSFETs are like resistors in the on-state, and shorter resistors have less resistance. Second, smaller MOSFETs have smaller gates, and thus lower gate capacitance. These first two factors contribute to lower switching times, and thus higher processing speeds. A third reason for MOSFET scaling is reduced area, leading to reduced cost. Smaller MOSFETs can be packed more densely, resulting in either smaller chips or chips with more computing power in the same area. Because the cost of fabricating a semiconductor wafer is relatively fixed, the cost of the individual integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip.

Difficulties arising due to MOSFET scaling

Producing MOSFETs with channel lengths smaller than a micrometre is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. Recently, the small size of the MOSFET has created operational problems.

Subthreshold leakage

Because of small MOSFET geometries, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be completely turned off, resulting in a weak-inversion layer which consumes power in the form of subthreshold leakage when the transistor should not be conducting. Subthreshold leakage, which was ignored in the past, now can consume upwards of half of the total power consumption of the chip.

Interconnect capacitance

Traditionally switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the wires connecting different parts of the chip) is becoming a large percentage of capacitance. Signals have to travel through the interconnect, which leads to increased delay and lower performance.

Heat production

The ever-increasing density of MOSFETs on an integrated circuit is creating problems of substantial localized heat generation that can impair circuit operation. Circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors.

Power MOSFETs are at risk of thermal runaway. As their on-state resistance rises with temperature, the power loss on the junction rises correspondingly, generating further heat. When the heatsink is not able to keep the temperature low enough, the junction temperature may quickly and uncontrollably rise, resulting in destruction of the device.

Gate oxide leakage

The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the phenomenon of tunneling leakage occurs between the gate and channel, leading to increased power consumption.

Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides, are now being researched to reduce the gate leakage. Increasing the dielectric constant of the gate oxide material allows a thicker layer while maintaining a high capacitance. The higher thickness reduces the tunneling current between the gate and the channel. An important consideration is the barrier height of the new gate oxide; the difference in conduction band energy between the semiconductor and the oxide (and the corresponding difference in valence band energy) will also affect the leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, somewhat negating the advantage of higher dielectric constant.

Process variations

With MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer. During chip manufacturing, random process variation can affect the size of the transistor, which becomes a greater percentage of the overall transistor size as the transistor shrinks. The transistor characteristics become less deterministic, but more statistical. This statistical variation increases design difficulty.

MOSFET construction

Gate material

The primary criterion for the gate material is that it is a good conductor. Highly-doped polycrystalline silicon is an acceptable, but certainly not ideal conductor, and it also suffers from some more technical deficiencies in its role as the standard gate material. There are a few reasons why polysilicon is preferable to a metal gate:

1. The threshold voltage (and consequently the drain to source on-current) is determined by the work function difference between the gate material and channel material. When metal was used as gate material, gate voltages were large (in the order of 3V to 5V), the threshold voltage (resulting from the work function difference between a metal gate and silicon channel) could still be overcome by the applied gate voltage (i.e. |Vg - Vt| > 0). As transistor sizes were scaled down, the applied signal voltages were also brought down (to avoid gate oxide breakdown, hot-electron reduction, power consumption reduction, etc). A transistor with a high threshold voltage would become non-operational under these new conditions. Thus, poly-crystalline silicon (polysilicon) became the modern gate material because it is the same chemical composition as the silicon channel beneath the gate oxide. In inversion, the work-function difference is close to zero, making the threshold voltage lower and ensuring the transistor can be turned on.
2. In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better performing transistors. Unfortunately these high temperatures would melt metal gates, thus a high melting point material such as poly-crystalline silicon is preferable to metal as gate material. However, polysilicon is highly resistive (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. To lower the resistivity, dopants are added to the polysilicon. Sometimes additionally, high temperature metal such as tungsten, titanium, cobalt, and more recently nickel, is layered onto the top of the polysilicon (as a side effect of layering metal on the source and drain contacts) and alloyed with the polysilicon to decreases the resistivity. Such a blended material is called silicide. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide, self-aligned silicide.
3. When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the so-called poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem a metal gate is desired. A variety of metal gates such as tantalum, tungsten, tantalum nitride, and titanium nitride, usually in conjunction with high-k dielectrics. An alternative is to use fully-silicided polysilicon gates, and the prosess is refered to as FUSI.

Other MOSFET types

Depletion mode MOSFETs

There are depletion mode MOSFET devices, which are less commonly used than the standard enhancement mode devices already described. These are MOSFET devices which are doped so that a channel exists even without any voltage applied to the gate. In order to control the channel, a negative voltage is applied to the gate, depleting the channel which reduces the current flow through the device. In essence, the depletion mode device is equivalent to a normally closed switch, while the enhancement mode device is equivalent to a normally open switch.[1]

NMOS logic

n-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced NMOS logic in the 1980s to become the preferred process for digital chips.

Power MOSFET

Cross section of a Power MOSFET, with square cells. A typical transistor is constituted of several thousand cells

Main article: Power MOSFET

Power MOSFETs have a different structure than the one presented above. As with all power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N epitaxial layer (see cross section), while the current rating is a function of the chanel width (the wider the chanel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.

It is worth noting that power MOSFETs with lateral structure exist. They are mainly used in high-end audio amplifiers. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications, so they are only used in On or Off states.

References

Power MOSFET

• "Power Semiconductor Devices", B. Jayant Baliga, PWS publishing Company, Boston. ISBN 0-534-94098-6

External links

• Lessons In Electric Circuits - INSULATED-GATE FIELD-EFFECT TRANSISTORS
• MOSFET Switching, Turn-ON, Hard Switching
• MOSFET models Diagrams and mathematical derivation.