Created attachment 58627 [details] -freport-bug output zvl512b We're seeing an ICE when building glibc for rv64gcv with zvl512b and zvl1024b on our postcommit https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1318 Haven't bisected down to which commit but it's still present on trunk as of r15-1952-g0c27eade475 during RTL pass: combine malloc.c: In function '__libc_mallinfo': malloc.c:5367:1: internal compiler error: in smallest_mode_for_size, at stor-layout.cc:356 5367 | } | ^ 0x2da7802 internal_error(char const*, ...) ../../../gcc/gcc/diagnostic-global-context.cc:491 0xc708d8 fancy_abort(char const*, int, char const*) ../../../gcc/gcc/diagnostic.cc:1725 0x139f897 smallest_mode_for_size(poly_int<2u, unsigned long>, mode_class) ../../../gcc/gcc/stor-layout.cc:356 0x124f2ea smallest_int_mode_for_size(poly_int<2u, unsigned long>) ../../../gcc/gcc/machmode.h:916 0x124f2ea get_best_extraction_insn ../../../gcc/gcc/optabs-query.cc:208 0x267a8e4 make_extraction ../../../gcc/gcc/combine.cc:7779 0x267bbcf make_compound_operation_int ../../../gcc/gcc/combine.cc:8186 0x267cc0f make_compound_operation(rtx_def*, rtx_code) ../../../gcc/gcc/combine.cc:8471 0x268095e simplify_set ../../../gcc/gcc/combine.cc:6975 0x268095e combine_simplify_rtx ../../../gcc/gcc/combine.cc:6374 0x2682bff subst ../../../gcc/gcc/combine.cc:5630 0x2686c91 try_combine ../../../gcc/gcc/combine.cc:3312 0x268bee1 combine_instructions ../../../gcc/gcc/combine.cc:1264 0x268bee1 rest_of_handle_combine ../../../gcc/gcc/combine.cc:15127 0x268bee1 execute ../../../gcc/gcc/combine.cc:15171 Please submit a full bug report, with preprocessed source. Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions.
Created attachment 58631 [details] Reduced a lot `-march=rv64gcv_zvl512b -O2`
Created attachment 58632 [details] Reduced all the way
Trying 21 -> 29: 21: r149:DI=r139:V8SI#0 0>>0x20 29: [r136:DI+0x4]=r149:DI#0 REG_DEAD r149:DI (insn 21 20 29 2 (set (reg:DI 149) (lshiftrt:DI (subreg:DI (reg:V8SI 139 [ vect__2.14_29 ]) 0) (const_int 32 [0x20]))) "/app/example.cpp":36:12 299 {lshrdi3} (nil)) (insn 29 21 30 2 (set (mem/c:SI (plus:DI (reg/f:DI 136 [ .result_ptrD.2808 ]) (const_int 4 [0x4])) [3 MEM <vector(8) intD.1> [(intD.1 *)&<retval>]+4 S4 A32]) (subreg:SI (lshiftrt:DI (subreg:DI (reg:V8SI 139 [ vect__2.14_29 ]) 0) (const_int 32 [0x20])) 0)) "/app/example.cpp":36:12 276 {*movsi_internal} (expr_list:REG_DEAD (reg:DI 149) (nil))) Confirmed.
*** Bug 115794 has been marked as a duplicate of this bug. ***
Confirmed via dupe.
The master branch has been updated by Li Xu <xuli@gcc.gnu.org>: https://gcc.gnu.org/g:63d7d5998e3768f6e3703c29e8774e8b54af108c commit r15-1993-g63d7d5998e3768f6e3703c29e8774e8b54af108c Author: xuli <xuli1@eswincomputing.com> Date: Thu Jul 11 04:29:11 2024 +0000 RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862] The reason is that in the following code, icode = movmisalignv8si has already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is allowed by targetm.slow_unaligned_access,which is contradictory. (((icode = optab_handler (movmisalign_optab, mode)) != CODE_FOR_nothing) || targetm.slow_unaligned_access (mode, align)) misaligned vector access should be enabled by -mno-vector-strict-align option. PR target/115862 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable vector misalign. Signed-off-by: Li Xu <xuli1@eswincomputing.com>