This code implements a design controller circuit for the SRAM memory chip on the DE2 board. This circuit connects the SRAM chip to the Avalon interconnect fabric. The verilog code for the controller has been added to the NIOS II based SOPC system as a custom component. We then write a piece of C code that communicates with the SRAM to implement it's behaviour.

More details can be found in the individual files. Enjoy!