Starred repositories
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
AMBA bus generator including AXI4, AXI3, AHB, and APB
体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
RISC-V Cores, SoC platforms and SoCs
1
Updated Sep 9, 2020
Mẫu luận văn tốt nghiệp trường Đại học Cần Thơ soạn thảo bằng LaTeX
yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
The root repo for lowRISC project and FPGA demos.
Design and Verification of AMBA APB slave
Collection of IPs based on AMBA (AHB, APB, AXI) protocols
AXI Adapter(s) for RISC-V Atomic Operations
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
RISC-V RV32IM compatible CPU created from scratch. Includes MMU and D/I-Caches
A Verilog implementation of a RISC-V CPU, supporting RV32IM instruction set with cache & memory module
Worked on a team of 3 to complete a pipelined RISC-V processor from scratch in System Verilog, complete with dual L1 Caches, a L2 cache, prefetching, and a branch predictor.
A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch prediction and cache.
RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System