[go: nahoru, domu]

Skip to content
View Satvik3799's full-sized avatar
Block or Report

Block or report Satvik3799

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Satvik3799/README.md

About Me:

I used to be an Embedded Hardware Design Engineer at a Start-up company.
I am a PG student at IIT Bombay
I’m interested in Computer Architecture, Digital IC Design and Embedded Systems.

Socials:

LinkedIn

Tech Stack:

Arduino Raspberry Pi Notion Trello LINUX C++ Python

GitHub Stats:



GitHub Trophies


Pinned Loading

  1. Physical-design-with-OpenLANE-using-Sky130-PDK Physical-design-with-OpenLANE-using-Sky130-PDK Public

    This is the repository for the workshop conducted by Mr. Krunal Ghosh from VSD.

    Tcl 5 1

  2. RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-Satvik3799 RISCV-MYTH-WORKSHOP/riscv-myth-workshop-sep23-Satvik3799 Public

    riscv-myth-workshop-sep23-Satvik3799 created by GitHub Classroom

    TL-Verilog

  3. Brent-Kung-Adder Brent-Kung-Adder Public

    Hardware description of a 32-bit Brent Kung adder, with a test bench.

    VHDL

  4. Pipelined-Multiplier Pipelined-Multiplier Public

    Try this example to understand how Pipelining is done in Hardware Designs.

    Verilog