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PES University
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Fork-PROBE-3.0-v.0 Public
Forked from ABKGroup/PROBE3.0Perl BSD 3-Clause "New" or "Revised" License UpdatedApr 28, 2024 -
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Memory-Design-And-Testing Public
The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
6 UpdatedMar 21, 2024 -
SCL-Design-Workshop-24 Public
Welcome to the Standard Cell Design Workshop repository. Here, you'll find all the necessary files and resources for a hands-on learning experience.
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GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
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VLSI-ASIC-Design-Flow Public
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally …
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VLSI-Physical-Design-Flow Public
This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of OpenLANE. This repo is the continuity of VLSI ASIC Design Flow
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eUVM_worskshop_avst_adder Public
Forked from euvm/avst_adderExample setup for UVM driven Icarus Verilog Simulation
D UpdatedJun 13, 2023