Name		Name	Last commit message	Last commit date
Latest commit History 61 Commits
Adder-Subtractor		Adder-Subtractor
Adder		Adder
Basic_Gates		Basic_Gates
Code-Converter		Code-Converter
Comparator		Comparator
Counter		Counter
FlipFlops		FlipFlops
Multiplexer		Multiplexer
Multiplier		Multiplier
Subtractor		Subtractor
README.md		README.md

Repository files navigation

Digital-System-Design

Digital System Design Lab verilog codes

Basic Gates

Code Converter

Adder

Subtractor

Adder-Subtractor

4 bit adder subtractor

Comparator

2 bit comparator

Multiplexer

Multiplier

2x2 Array Multiplier

Flip Flops

Counters

Synchronous
- 4 bit random sequence
- 3 Bit Synchronous Up/Down
Asynchronous
- 4 bit ripple counter or mod-16 counter
- Mod - 10 Counter

About

Digital System Design Lab Codes using Verilog

verilog adder half-adder d-flipflop full-adder flipflop ripple-carry-adder jk-flipflop t-flipflop

Report repository

Releases

No releases published

Packages

No packages published

Languages