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Question about and2_output_verilog.v in full_testbench #1585

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Lukemagik opened this issue Feb 27, 2024 · 2 comments
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Question about and2_output_verilog.v in full_testbench #1585

Lukemagik opened this issue Feb 27, 2024 · 2 comments

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@Lukemagik
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Hello, I'm new to this software and I'm going through the initial tutorials.
I have a question regarding the file _output_verilog.v that is generated in the full testbench tutorial.
and2

Shouldn't this be the netlist? Why is it implemented using shifts rather than with a LUT?
@yunuseryilmaz18
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@Lukemagik sorry for the late answer. This is a synthesized netlist from yosys to check whether FPGA is programmed correctly in the testbenches. The BLIF file in the folder can be more useful if you're searching how a LUT formed in this task.

@tangxifan
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Thanks @yunuseryilmaz18 for the prompt answer. The verilog is an output from yosys, which is a rewrite for your original RTL. We use this file as a reference in openfpga_flow to validate the correctness of FPGA fabric.

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@tangxifan @yunuseryilmaz18 @Lukemagik