Describe the bug
Modelsim simulation shows undefined output for FPGA output lines.

To Reproduce
Steps to reproduce the behavior:

1. Clone OpenFPGA repository
2. Execute OpenFPGA task or your own example:
   python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain
   <task.config>

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Configuration file for running experiments

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

timeout_each_job : FPGA Task script splits fpga flow into multiple jobs

Each job execute fpga_flow script on combination of architecture & benchmark

timeout_each_job is timeout for each job

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 10*10
fpga_flow=yosys_vpr
#fpga_flow=yosys

[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
#openfpga_vpr_device_layout=
openfpga_vpr_device_layout=--device auto
openfpga_fast_configuration=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0 =${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common =
bench0_chan_width = 300
bench0_top = or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=

3. See error - Follow steps for modelsim simulation under Manual Methods in https://openfpga.readthedocs.io/en/latest/tutorials/design_flow/verilog2verification/
   use -suppress 2892 as compiling option.

Expected behavior
When I ran iverilog simulation, simulation ran successfully. With modelsim I got undefined output lines on FPGA_out
Screenshots
If applicable, add screenshots to help explain your problem.

Enviornment (please complete the following information):

• OS:
  Red Hat 11.4.1-2
• Compiler:
  gcc version 11.4.1 20230605

Additional context

Image1 - iverilog simulation wave

Image2- Simulation using modelsim