Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• RR GSB only outputs rr_graph attributes, which is hard for PD team to sign-off.

What does this pull request change?

This PR improves in the following aspects:

• Now GSB XML contains routing segment name from architecture file for X-direction and Y-direction routing tracks
• Now GSB XML contains pin name (seen in SB module) from architecture file for X-direction and Y-direction routing tracks
• Now GSB XML contains pin name (seen in SB module) from architecture file for output pins

An example output:

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.