This repository features an RFSoC SD-FEC design that is compatible with PYNQ image v2.7 and greater for the following RFSoC development boards:

• ZCU208,
• ZCU111,
• RFSoC4x2,
• RFSoC2x2.

Follow the instructions below to install the Python package now. You will need to give your board access to the internet.

• Power on your RFSoC development board with an SD Card containing a fresh PYNQ v2.7 or greater image.
• Navigate to Jupyter Labs by opening a browser (preferably Chrome) and connecting to http://<board_ip_address>:9090/lab.
• We need to open a terminal in Jupyter Lab. Firstly, open a launcher window as shown in the figure below:

• Now open a terminal in Jupyter as illustrated below:

Run the code below in the jupyter terminal to install the Python package.

pip3 install https://github.com/strath-sdr/rfsoc_sdfec/releases/download/v1.1.0/rfsoc_sdfec.tar.gz

This repository currently has no Jupyter notebooks. See https://github.com/strath-sdr/RFSoC-Book for compatible notebooks.

The following software is required to use the project files in this repository.

• Vivado Design Suite 2020.2
• System Generator for DSP
• MATLAB R2020a

This project can be built with Vivado from the command line. Open Vivado 2020.2 and execute the following into the tcl console:

cd /<repository-location>/boards/<board-name>/strath_sdfec/

Now that we have moved into the correct directory, make the Vivado project by running the make commands below sequentially.

make block_design
make bitstream

Alternatively, you can run the entire project build by executing the following into the tcl console:

make all

BSD 3-Clause