This repository is my entry into scripting using TCL and it's nuances in physical design flow in VLSI. The project's objective is to read through a typical timing report generated by a STA tool and extract useful information from it. This is extremely useful in complex designs that may contain ennormous amounts of critical timing paths. Going throigh the entire report becomes complicated due to the sheer volume of logic depth across paths.
Thus a summary report that provides a overview of the timing report is vital. Although the insights extracted could vary depending on the complexity of the timing report, for the sake of this project the timing report used consists of a single path and the intel gathered from the report are dumped into a txt file named 'timing_rpt_summary.txt' consisting of the under :
- Start Point
- End Point
- Number of Inverters and Buffers used in the path
- Logic Depth in the path
- Data Path Delay
- Slack (Violated only)
The above insights are standard in order to understand the report.
This project consists of creation of a Shell Script (tcsh based script) that serves as the way for the user to communicate and interact with the main tcl script. It's close to a user-interface for the ease of operating the TCL script. Next is the development of the main TCL script that will take in the timing report through the shell script and dump out a timing summary report named : 'timing_rpt_summary.txt'.
Important
- Linux users can simply import the shell script and tcl script in their directory and execute the shell script via :
./tcl_parser <full_path_to_timing_report> - Windows users need to avoid using the shell script and simply run the tcl script directly by providing the full path to the timing report. Make sure that tcl shell or
tclshis installed and functional in the windows power shell. Please visit the tcl websire to download the necessary dependencies. Run the tcl script via :tclsh tcl_parse <full_path_to_timing_report
Note
This project is a segment of a task provided to me by my manager while working as a Physical Design Intern at 7Rays Semiconductors.
Hence, the timing report provided is sanitized to remove sensitive information. The report is modified to contain dummy information in order to protect the integrity of the proprietary information of the design and ensure compliance with the NDA.