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openlane
openlane PublicForked from The-OpenROAD-Project/OpenLane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Verilog
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RapidWright
RapidWright PublicForked from Xilinx/RapidWright
Build Customized FPGA Implementations for Vivado
Java
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nextpnr-xilinx
nextpnr-xilinx PublicForked from gatecat/nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
C++
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