Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
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Updated
Jun 24, 2021 - Verilog
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
FPGA implementation of the popular logic game using VHDL and Altera DE1
Graph Processing Framework that supports || OpenMP || CAPI
An 8-bit processor in VHDL based on a simple instruction set
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
Research & Development FPGA projects for different boards
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
Implementation of an Edge Detection Filter Using the Avalon Interface
Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract
This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6
Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.
Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
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