An abstraction library for interfacing EDA tools
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Updated
Jul 8, 2024 - Python
An abstraction library for interfacing EDA tools
Repurposing existing HDL tools to help writing better code
A Python-based IP Core Management Infrastructure.
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
Example of Python and PyTest powered workflow for a HDL simulation
An assembler that transfers your assembly code into .mem files for simulation in modelsim. Instruction set, opcodes assignment, and sample files included.
🪀 Tool to play with HDL (inspired by EdaPlayground)
SublimeLinter plugin for linting VHDL with Modelsim vcom
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