Micro-Programmed Multi-Cycle Processor
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Updated
Sep 9, 2020 - SystemVerilog
Micro-Programmed Multi-Cycle Processor
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
Mips Multi-Cycle, Computer Architecture course, University of Tehran
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