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tiny-gpu Public
Forked from adam-maj/tiny-gpuA minimal GPU design in Verilog to learn how GPUs work from the ground up
SystemVerilog UpdatedApr 27, 2024 -
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nanoGPT Public
Forked from karpathy/nanoGPTThe simplest, fastest repository for training/finetuning medium-sized GPTs.
Python MIT License UpdatedJul 23, 2023 -
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CatSlaveSaver Public
Ball pick-up robot to save your life when playing with your cat.
UpdatedMay 21, 2023 -
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drawio Public
Forked from jgraph/drawiodraw.io is a JavaScript, client-side editor for general diagramming and whiteboarding
JavaScript Apache License 2.0 UpdatedFeb 3, 2023 -
siphash-verilog Public
Forked from eupn/siphash-verilogVerilog implementation of pipelined 64-bit SipHash2-4 hash function
Verilog MIT License UpdatedJan 17, 2023 -
cppsiphash Public
Forked from melver/cppsiphashSipHash C++11 header-only library
C++ UpdatedDec 5, 2022 -
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verible Public
Forked from chipsalliance/veribleVerible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++ Apache License 2.0 UpdatedSep 26, 2022 -
pyxsi Public
Forked from gsmecher/pyxsiPython/C/RTL cosimulation with Xilinx's xsim simulator
C++ Other UpdatedApr 26, 2022 -
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DirectNVM Public archive
An open-source RTL NVMe controller IP for Xilinx FPGA.
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rtl_template Public
A template folder for Vivado RTL project, including .gitignore.
1 UpdatedOct 27, 2020 -
hls_template Public
A template folder for Vivado HLS project including .gitignore.
UpdatedOct 13, 2020 -
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getgist Public
Forked from cuducos/getgist🖥️ Easily download any file from a GitHub Gist, with one single command.
Python MIT License UpdatedApr 15, 2020 -
rosetta Public
Forked from cornell-zhang/rosettaRosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
C++ BSD 3-Clause "New" or "Revised" License UpdatedMar 17, 2020 -
fpga-drive-aximm-pcie Public
Forked from fpgadeveloper/fpga-drive-aximm-pcieExample designs for FPGA Drive FMC
Tcl MIT License UpdatedFeb 11, 2020 -
vtr-verilog-to-routing Public
Forked from verilog-to-routing/vtr-verilog-to-routingVerilog to Routing -- Open Source CAD Flow for FPGA Research
C Other UpdatedNov 5, 2019 -
CTREncryption Public
Cache-enabled counter encryption, written in Vivado HLS.
Ada UpdatedApr 24, 2019 -
LRUCache Public
Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.
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hexo-theme-Wikitten Public
Forked from zthxxx/hexo-theme-WikittenA theme of Hexo for Wiki seem like Wikitten style.
CSS MIT License UpdatedFeb 14, 2019 -
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