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Duţu et al., 2020 - Google Patents

Independent forward progress of work-groups

Duţu et al., 2020

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Document ID
11742995730204164897
Author
Duţu A
Sinclair M
Beckmann B
Wood D
Chow M
Publication year
Publication venue
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

External Links

Snippet

GPUs have evolved from providing highly-constrained programmability for a single kernel to using pre-emption to ensure independent forward progress for concurrently executing kernels. However, modern GPUs do not ensure independent forward progress for kernels …
Continue reading at www.cs.ucr.edu (PDF) (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
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    • G06F9/46—Multiprogramming arrangements
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    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
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    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F9/00—Arrangements for programme control, e.g. control unit
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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