MXPA00006842A - Video program bearing transport stream remultiplexer - Google Patents

Abstract

A method and system (30, 30', 100, 100', 100'', 100''') remultiplex video program bearing data (TS1-TS5, TS10-TS20), using a descriptor based system (122, 124, 129-4) for timely outputting transport packets, using a descriptor and transport packet caching technique (116, 122, 124, 114) for decoupling the synchronous receipt and transmission of transport packets from any asynchronous processing (160, 120, 130, S2, 402, S4, 404), using descriptors for managing scrambling and descrambling control words (129-9), optimizing bandwidth of transport streams by replacing null transport packets with transport packet data, and using a technique (180) for locking multiple internal reference clock generators (113).

Description

REMOTEPLEXOR OF TRANSPORT CURRENTS CARRYING VIDEO PROGRAMS FIELD OF THE INVENTION The present invention pertains to communication systems. Particularly, the present invention relates to the selective multiplexing of bitstreams containing one or more programs, such as, for example, real-time audio-video programs. The information specific to the program and related to other programs is adjusted in order to allow the identification, extraction and reproduction in real time of the program at the receiving end of the bit streams. BACKGROUND OF THE INVENTION Recently, techniques have been proposed to efficiently compress digital audio-video programs for storage and transmission. See, for example, ISO \ IEC IS 13818-1,2,3: Information Technology - Generic Coding of Films and Associated Audio Information: Systems, Video and Audio ("MPEG-2"); ISO \ IEC IS 11172-1,2,3: Generic Coding of Films and Associated Audio for Digital Storage Media at up to approximately 1.5 Mbit / s: Systems, Video and Audio ("MPEG-1"); Dolby AC-3; Motion JPEG, etc. Here, the term program refers to a set of related audio-video signals that have a common temporal basis and are intended for synchronized presentation, according to the MPEG-2 jargon. MPEG-1 and MPEG-2 offer streams in hierarchical layers. That is to say, an audio-video program is composed of one or several streams of coded bits or "elementary currents" ("ES") such as an ES of coded video, and ES of coded audio, a second ES of audio encoded language, an ES of subtitle text, etc. Each ES, in particular, each of the audio and video ESs, is encoded separately. The encoded ESs are then combined in the system layer stream such as for example a program stream "PS", or a transport stream "TS". The purpose of the PS or the TS is to allow the extraction of the encoded ESs of a program, separation, and separate coding of each ES as well as synchronous presentation of the decoded ESs. The TS or PS may be encapsulated in a channel layer or higher storage format that offers a forward error correction. Element streams Audio ESs are typically encoded at a constant bit rate, for example, 384 kbps. The video ESs, on the other hand, are encoded by. MPEG-1 or MPEG-2 conformance at a variable bit rate. This means that the number of bits per compressed / encoded image varies from image to image (these images are displayed or displayed at constant speed). Video coding includes the steps of spatially and temporally encoding video images. The spatial coding includes a discrete cosine transformation, quantization, scanning (zig-zag), execution length coding and variable length coding blocks of luminance pixel data and cro nance. The temporal coding includes the estimation of the movement of macroblocks (for example, a set 4 x 4 of luminance blocks and each superimposed chrominance block) to identify motion vectors, compensating the movement of the macroblocks to form macroblocks of prediction errors, encoding especially the macroblocks of prediction errors and coding the variable length of the motion vectors. Some images, which are known as I images, are encoded only in spatial form, while other images, such as P images and B images are spatially encoded and motion compensated (that is, temporarily predicted from other images). The encoded I images typically have more bits than the encoded P images and that the encoded B images typically have more bits than the encoded B images. Either way, even encoded images of the same type tend to have different numbers of bits. MPEG-2 defines a buffer size limitation in encoded video ESs. Particularly, it is considered that a decoder has a buffer with a predefined maximum storage capacity. The encoded video ES should not cause the decoder buffer to overflow (and in some cases, should not cause the decoder buffer subflow). MPEG-2 specifically defines the moments at which the compressed data of each decoder buffer image is removed in relation to the bit rate of the video ES, the speed of image display and certain limitations of the video. Image reordering imposed to allow the decoding of the predicted images (from the reference images from which they were predicted). Given these limitations, the number of bits produced in the compression of an image can be adjusted (as often as in a macroblock per macroblock basis) to ensure that the video ES does not cause overflow or subflow of the decoder buffer of It's video. Transport currents This invention is illustrated here for TSs. For the sake of brevity, comments on PSs are omitted. However, persons with certain knowledge in the art will note that certain aspects of this invention can be applied to PSs. The data of each ES are formed in elementary streams of variable length programs or "PES" packages. PES packets contain data for only a single ES, but may contain data for more than one decoding unit (for example, they may contain more than one compressed image, more than a compressed audio frame, etc.). In the case of a TS, the PES packets are first divided into several load units and inserted into fixed-length transport packets (188 bytes in length). Each transport packet can carry load data of only one type, for example, PES packet data for only one ES. Each TS has a four-byte header that includes a packet identifier or "PID". The PID is analogous to a marker that indicates only the content of the transport packet. Thus, a PID is assigned to an ES of video of a particular program, a second different PID is assigned to the audio ES of a particular program, etc. The ESs of each program are coded in relation to a single encoder system time clock. In the same way, the decoding and synchronized presentation of the ESs are synchronized, in turn, in relation to the same time clock of the encoder system. Accordingly, the decoder must be able to recover the original encoder system time clock in order to be able to decode each ES and present each decoded ES in a timely and mutually synchronized manner. For this purpose, time impressions of the system time clock are inserted, which are known as program clock reference or "PCRs" in the selected transport packet loads (specifically, in adaptation fields). The decoder extracts the PCRs from the transport packets and uses the PCRs to retrieve the encoder system time clock. The PES packets may contain decoding time impressions either "DST" and / or presentation time impressions or "PST". A DTs indicates the time relative to the recovered encoder system time clock, where the next decoding unit should be decoded (ie, compressed audio frame, compressed video image, etc.). The PTS indicates the time, in relation to the system time clock of the recovered encoder, where the next presentation unit should be presented or displayed (ie, uncompressed audio box, uncompressed image, etc.).

Unlike the PS, a TS can have transport packets that carry program data for more than one program. Each program may have been encoded in a different encoder relative to a different encoder system time clock. The TS allows the decoder to recover the specific system time clock of the program that the decoder wishes to decode. For this purpose, the TS must carry separate sets of PCRs, that is, a set of PCRs to retrieve the time clock from each program's encoder system. The TS also carries program-specific or well-defined information (PSI) in transport packages. PSI is to identify data from a desired program or other information to help decode a program. A program association table or "PAT" carried in a transport packet with the PID 0x0000 is provided. The PAT correlates each program number with the PID of transport packages that carry program definitions for this program. A program definition: (1) indicates which ESs constitute the program to which the program definition corresponds, (2) identifies the PIDs for each of these ESs, (3) indicates the PID of the transport packages that carry the PCRs of this program (4) identifies the PIDs of transport packets carrying ES-specific accreditation control messages (for example, decoding or coding keys) and other information. Collectively, all the program definitions of a TS are known as a program topography table (PMT). Thus, a decoder can extract the PAT data from the transport packets and use the PAT to identify the PID of the transport packets that carry the program definition of a defined program. The decoder can then extract from the transport packets the program definition data of the desired program and identify the PIDs of the transport packets carrying the ES data constituting the desired program and the transport packets carrying the PCRs. Using these identified PIDs, the decoder can then extract from the transport packets of the TSs the ES data of the ESs of the desired program and the PCRs of this program. The decoder recovers the decoder system time clock from the PCRs of the desired program and decodes and displays the ES data at times related to the recovered encoder system time clock. Other types of information optionally provided in a TS include accreditation control messages (ECMs), accreditation management messages (EMMs), a conditional access table (CAT) and a network information table (NIT) (CAT and NIT). they are also types of PSI). The ECMs are specific messages for ES to control the ability of a decoder to interpret the ES to which the ECM belongs. For example, an ES may be coded and the decoding key or control word may be an ECM. The ECMs associated with a particular ES are placed in their own transport packages and marked with a unique PID. EMMs, on the other hand, are system-scale messages for controlling the capacity of a set of decoders (said set is known in a system as a "conditional access system") for interpreting portions of a TS. The EMMs are placed in their own transport packages and are marked with a unique PID to the conditional access system to which the EMMs belong. A CAT is provided when EMMs are present to allow a decoder to locate the EMMs of the conditional access system of which the decoder is part (that is, the set of decoders of which the decoder is a member). The NIT maintains several network parameters. For example, if several TS are modulated at different carrier frequencies to which a decoder receiver can be tuned, the NIT can indicate in which carrier frequency (carrier TS) each program is modulated. Like the video ES, MPEG-2 requires that the TS be decoded by a decoder having the TS buffers of predefined sizes to store program ES and PSI data. MPEG-2 also defines the speed at which the data flows in said buffers and outside of said buffers. More importantly, MPEG-2 requires that TS does not cause overflow or subflow of TS buffers. To avoid overflow or subflow of buffers, MPEG-2 requires that data carried from an encoder to a decoder have a constant end-to-end delay, and that the program and the proper bit rate of ES be maintained. In addition, to ensure that the ESs are decoded and presented in a timely manner, the relative arrival time of the PCRs in the TS should not vary too much from the relative time indicated by said PCRs. Stated differently, each PCR indicates the time that the system time clock (retrieved in the decoder) should have when the last byte containing a portion of the PCR is received. Thus, the time of reception of successive PCRs must be correlated with the times indicated by each PCR. Remultiplexing It is often desired to "remultiplex" the TSs. Re-multiplexing includes the selective modification of the content of a TS, such as the addition of transport packets to a TS, the removal of transport packets from a TS, the rearrangement of the order of transport packets in a TS and / or the modification of the data contained in transport packages. For example, it is sometimes desirable to add transport packages that contain a first program to a TS that contains other programs. This operation includes more steps than simply adding the transport packages of the first program. At least, to PSI, as for example the PAT and the PMT must be modified in such a way that correctly references the contents of TS. However, the TS must be modified further to maintain the constant end-to-end delay of each transported program. Specifically, the bit rate of each program should not change to avoid overflow and buffer underflow of video decoder and TS. In addition, any temporary misalignment introduced in the TS PCRs, for example, as a result of changing the spacing / relative speed of receiving successive transport packets carrying PCRs from the same program, must be removed. The prior art has proposed a remultiplexer for MPEG-2 TSs. The proposed remultiplexer is a dedicated, sophisticated equipment that offers complete synchrony between the point at which each of the TSs is received to remultiplex to the output point of the final remultiplexed TS produced - a single system time clock controls and synchronizes the reception, placement in buffer, modification, transfer, reassembly and removal of transport packages. While a remultiplexer of this type is capable of remultiplexing the TSs, the remultiplexer architecture is complicated and requires a dedicated platform that is uniformly synchronous. It is an object of the present invention to provide a flexible remultiplexing architecture which may, for example, be in contrast on an arbitrary, possibly asynchronous platform. A program code is known that compresses the video and audio of a single program and produces a single program that carries TS. As previously observed, MPEG-2 imposes very strict limitations on the bit rate of the TS and on the number of bits that may be present in the video decoder buffer at any given time. It is difficult to code an ES, particularly an ES of video, and ensure that the transfer speed of the bits remains totally constant from one moment to another. On the contrary, a certain excess bandwidth must be allocated to each program in order to ensure that the ES data is not omitted as a result of the ES encoder producing an unexpectedly excessive amount of coded information. On the other hand, the program encoder does not occasionally have encoded program data to be produced in a particular transport packet time segment. This may occur because the program encoder has reduced the number of bits to be removed at this time to avoid a decoder buffer overflow.

Alternatively, this may occur because the program encoder requires a longer unanticipated time to code the ESs and therefore has no data available at this time. To maintain the bit rate of the TS and to avoid a TS decoder buffer subflow, a null transport packet is inserted into the transport packet time segment. The presence of empty transport packets in a TS to remultiplex is often an imposition that must be accepted. It is an object of the present invention to optimize the bandwidth of TSs containing empty transport packets. Sometimes, the TS or ES data is transferred through an asynchronous communication link. It is an object of the present invention to "resynchronize" this data transferred asynchronously or without synchronization. It is also an object of the present invention to minimize the fluctuation in transport packets transmitted from asynchronous communication links of this type by synchronizing the transmission of such transport packets. It is also an object of the present invention to allow the user to dynamically change the remultiplexed content in the remultiplexed TS, that is, in real time without stopping the flow of transport packets in the extracted remultiplexed TS. It is a further object of the present invention to distribute the remultiplexing functions in a network. For example, it is an object to place one or several sources of TS or ES in arbitrary nodes of a communication network that can be asynchronous (such as an Ethernet LAN) and place a remultiplexer in another node of such a network. COMPENDIUM OF THE INVENTION These and other objects are achieved in accordance with the present invention. An illustrative application of the invention is the remultiplexing of one or several transport streams (TSs) that comply with MPEG-2. TSs are streams of bits that contain data from one or several compressed / encoded audio-video programs. Each TS is formed of a sequence of fixed-length transport packets. Each compressed program includes data for one or more compressed elementary streams (ESs), such as digital video signal and / or digital audio signal. The transport packets also carry program clock references, which are time impressions of an encoder system time clock to which the decoding and presentation of the respective program are synchronized. Each program has a predetermined bit rate and is intended to be decoded in a decoder having a TS buffer and a video decoder memory of predetermined sizes. Each program is coded in such a way that overflow and subflow of these buffers is avoided. A program-specific information (PSI) is illustratively also carried in transport packets selected from the TS to help decode the TS. According to one embodiment, a remultiplexer node is provided with one or more adapters, each adapter includes a cache, a data link control circuit connected to the cache, and a direct memory access circuit connected to the cache. The adapter is a synchronous interface with special features. The data link control circuit has an input port to receive transport current and an output port to transmit transport streams. The direct memory access circuit may be connected to an asynchronous communication link with a variable end-to-end communication delay, such as a bus of the remultiplexer node. Using the asynchronous communication link, the direct memory access circuit can access a memory of the remultiplexer node. Memory can store one or more queues of descriptor storage locations, such as a queue assigned to an input port and a queue assigned to an output port. The memory may also store transport packets in storage locations of transport packets to which descriptors stored in said descriptor storage locations of each queue point. Illustratively, the remultiplexer node includes a processor, connected to the bus, for the processing of transport packets and descriptors. When an adapter is used to enter transport streams, the data link control circuit assigns each received transport packet to retain an unused descriptor in one of a sequence of descriptor storage locations, of a queue assigned to the port of entry. The assigned descriptor is in a descriptor storage location from which the cache has gained control. The data link control circuit stores each retained transport packet in a transport packet storage location from which the cache has gained control and indicated by the assigned descriptor. The direct memory access circuit gains control of one or more unused descriptor storage locations from the queue in memory after a last descriptor storage location from which the cache has already gained control. The direct memory access circuit also obtains control of the transport packet locations in the memory indicated by these descriptors in the location and storage of descriptors or in the various descriptor storage locations. When an adapter is used to produce transport packets, the data link control circuit retrieves from the cache each descriptor of a sequence of descriptor storage locations of a queue assigned to the output port. The descriptors are retrieved from the beginning of the sequence in order. The data link control circuit also retrieves from the cache the transport packets stored in the transport packet storage locations indicating the retrieved descriptors. The data link control circuit extracts each recovered transport packet in a single time segment (i.e., a transport packet per time segment) from a transport system produced from the output port. The direct memory access circuit obtains from the memory for caching, descriptors of the queue assigned to the output port in storage locations after the descriptor storage locations where a last cache descriptor of the sequence is stored . The direct memory access circuit also obtains each transport packet stored in a transport packet location indicated by the obtained descriptors. In accordance with another embodiment, each descriptor is used (also) to record a receipt-time impression, which indicates when a transport package is received at an entry port, or an exit-time impression, which indicates the time in which a transport package must be transmitted from an exit port. In the case of transport packets received at an input port, the data link control circuit records an impression of reception time in the descriptor assigned to each transport packet received and retained indicating the time at which it was received the transport package. The descriptors are kept in order of reception in the reception queue. In the case of the output of transport packets from an output port, the data link control circuit sequentially recovers each descriptor from the transmission queue, and the transport packet indicated by each recovered descriptor. At a time corresponding to an exit time recorded in each recovered descriptor, the data link control circuit transmits the recovered transport packet indicated by each recovered descriptor in a time segment of the transport current produced corresponding to the time of transmission registered in the recovered descriptor.

Illustratively, the remultiplexer node processor examines each descriptor in the receive queue, as well as other queues containing descriptors indicating transport packets to be sent. The processor allocates a descriptor of the transmission queue associated with an output port from which a transport packet indicated by each examined descriptor must be transmitted (eventually). The processor assigns a sending time to the assigned descriptor of the transmission queue, for example, according to a time of reception of the transport packet indicated by the descriptor and an internal buffer delay between the reception and the output of the transport packet. The processor also orders the descriptors of the transmission queue in order to increase the sending time. A single PCR normalization procedure is also provided. The processor programs each transport packet to be sent "in a time segment at a particular send time, which corresponds to a predetermined delay at the remultiplexer node.If the scheduled transport packet contains a PCR, the PCR is adjusted based on in a displacement of the local reference clock (s) (s) in relation to the program of the system time clock from which the PCR was generated, if there is a change. of data transmitted by said adjusted PCR carrying transport packets, further adjusts each adjusted PCR time print based on a difference between the scheduled send time of the transport packet and a real time in which the time segment with In an illustrative way, if more than one transport packet must be sent in the same time segment, each transport packet of this type is sent in a segment of time. or consecutive separate. The processor calculates an estimated fit for each PCR in a transport packet programmed to be sent in a time segment other than the time slot as determined by the use of the predetermined delay. The estimated setting is based on an output time difference between the time segment where the processor has actually programmed the transport of the packet carrying the PCR to be sent and the time segment according to that determined by a predetermined delay. The processor adjusts the PCRs in accordance with this estimated setting. According to one embodiment, the descriptors are also used to control the coding or decoding of transport packets. In the case of decoding, the processor defines a sequence of one or more processing steps to be carried out in each transport packet and orders the decoding processing within the sequence. The processor stores a control word information associated with the contents of the transport packet at the control word information storage location of the assigned descriptors. The data link control circuit allocates descriptors to each transport packet retained, received, said descriptors each include one or more processing indicia and a storage location for control word information. The data link control circuit establishes one or more of the processing indications. From the descriptor assigned to indicate that the next step of processing the sequence can be carried out in each of the assigned descriptors. A decoder is provided to sequentially access each assigned descriptor. If the processing indications of the descriptor to which one has access is established to indicate that the decoding processing must be carried out in the descriptor to which one has access (and transport package indicated by the descriptor to which one has access), then the decoder processes the descriptor and transport package it indicates. Specifically, if the descriptor indicates a transport packet to be decoded, the decoder decodes the transport packet using the control word information in the descriptor to which it is accessed.

The decoder can be located in the adapter (reception), in which case the decoder processing occurs after processing by the data link control circuit (e.g., descriptor assignment, reception time record, etc.), but before processing by the circuit direct access to memory (for example, transfer to memory). Alternatively, the decoder may be a separate device connected to the asynchronous communication interface in which case the decoder processing occurs after processing by the direct memory access circuit but before processing by the processor (e.g., estimated time calculation of output, PID reassignment, etc.). In each case, the control word information is a base address of a PID indexable control word table maintained by the processor. In the case of coding, the processor defines a sequence of one or more processing steps to be carried out in each transport packet and orders coding processing within the sequence. The processor allocates a transmit descriptor of a transmission queue to each transport packet to be transmitted and stores a control word information associated with the contents of the transport packet in the storage location of control word information of the selected descriptors. between the assigned descriptors. The processor then sets one or more processing indications of the descriptor to indicate that the next processing step of the sequence can be carried out in each of the assigned descriptors. An encoder is provided to sequentially access each assigned descriptor. The encoder processes each descriptor to which the transport packet is accessed and indicated by the descriptor to which it is accessed, but only if the processing indications of the descriptors to which it is accessed are established to indicate that the coding processing may be carried out in the descriptor to which you have access (and transport package that indicates the descriptor to which you have access). Specifically, if the descriptor to which it is accessed indicates a transport packet to be encoded, the encoder codes the transport packet indicated by the descriptor to which it is accessed by using the control word information in the descriptor to which it is accessed. The encoder can be located in the adapter (transmission), in which case the coding processing occurs after processing by the direct memory access circuit (for example, memory transfer to the cache memory, etc.), but before processing by the data link control circuit (e.g., output in the correct time segment, final PCR correction, etc.). Alternatively, the encoder may be a separate device connected to the asynchronous communication interface, in which case the decoder processing occurs after processing by the processor (e.g., allocation of transmission queue descriptor, dispatch time allocation, correction of PCR, etc.), but before processing by the direct memory access circuit. The control word information may be a base address of a PID indexable control word table maintained by the processor, as in the case of decoding. Preferably, however, the control word information is the control word itself, used to encode the transport packet. In addition, according to one embodiment, a method for resynchronizing data carrying a received video program through an asynchronous communication link is provided. An asynchronous interface (for example, an Ethernet interface, an ATM interface, etc.) is connected to the remultiplexer node processor (for example, through a bus) to receive a stream of bits carrying a video program from a communication link having a variable end-to-end transmission delay. The processor determines a time in which each of the packets or packets received (s) carrying (n) data of the same program of the received bit stream must appear in a TS extracted based on several impressions of the program time carried in the received bitstream. A synchronous interface, such as a transmission adapter, selectively transmits selected transport packets carrying received data in a TS sent with a constant end-to-end delay at times depending on the determined times. Illustratively, the remultiplexer node memory stores packets containing data received from the bitstream received in a receive queue. The processor identifies each packet containing data of a program stored in the receipt queue between a first particular packet and a second particular packet containing consecutive time impressions of this program. The processor determines a packet speed (transport) of the program based on a difference between the first time print and the second time print.

The processor assigns as the transmission time to each of the identified packets, the sum of a transmission time assigned to the first particular packet and a product of the packet speed and a packet offset identified from the first packet. According to another embodiment, a method is provided for dynamically varying and without suturing remultiplexing in accordance with a changed user specification. An interface, such as a first adapter, selectively removes only particular packets from the transport packets from a TS according to an initial user specification for remultiplexed TS content. A second interface, such as a second adapter, reassembles the selected packets between the extracted transport packets and the transport packets containing PSI, if they exist, in a remultiplexed TS produced in accordance with the initial user specification for remultiplexed content of TS. The second adapter also sends the re-multiplexed TS reassembled in the form of a bit stream. The processor dynamically receives one or more new user specifications for a remultiplexed TS content that specifies one or more of the following: (I) different transport packages to be extracted and / or (II) different transport packages to reassemble, while the first adapter and the second adapter extract transport packages and reassemble and send the remultiplexed TS. In response, the processor causes the first adapter and the second adapter to dynamically suspend the extraction or reassembly of the transport packets according to the initial user specification and dynamically begin to extract or reassemble transport packets according to the new user specification without introducing a discontinuity in the remultiplexed transport stream produced. For example, the processor may generate a substitute PSI that references different transport packets according to the new user specification, for reassembly by the second adapter. Illustratively, this technique of remultiplexing variation without sutures can be used to automatically ensure that the correct ES information of each selected program is always sent in the remultiplexed TS produced, in spite of possible changes in the constitution of ES of this program. A controller can be provided to generate a user specification indicating one or more programs of the TSs entered to be produced in the output TS. The first adapter continuously captures program definitions of an entered TS. The processor continuously determines from the captured program definitions which elementary streams constitute each program. The second adapter produces in the output TS each transport packet containing ES data of each ES determined to constitute each program indicated to be produced by the user specification without introducing discontinuity in the TS produced. Thus, even if the PIDs of the ESs that constitute each program change (in number or value), the correct and complete ES data for each program are nevertheless always produced in the output TS. According to another embodiment, a method is offered to optimize the bandwidth of a TS that has empty transport packets inserted. The first interface (adapter) receives a TS with a predetermined bit rate, said TS includes transport packets that carry program data in a variable manner and one or more empty transport packets. Each of the empty transport packets is inserted into a time segment of the received TS to maintain the transfer speed of the TS's default bits when none of the transport packets carrying compressed program data are available for insertion into the received TS in the respective transport packet time segment. The processor selectively replaces one or more of the empty transport packets with another of the transport packets that carry data to remultiplex. Such transport packets carrying replacement data may contain PSI data or even transaction data in bursts, said burst transaction data do not have requirements of bit rates or transmission latency to present the information continuously. Illustratively, the processor extracts the selected transport packets between the transport packets of the received TS and discards the unselected transport packets including the empty transport packets. The selected transport packets are stored in the memory through the processor and the first adapter. In accordance with what is described above, the processor programs each of the stored transport packets for output into an outgoing transport stream at a time that depends on the time at which each of the stored transport packets is received. A second interface (adapter) produces each of the transport packets stored in a time segment corresponding to the program. If there is no transport packet scheduled for output on one of the time slots of the outgoing TS, the second adapter sends an empty transport packet. However, empty transport packets occupy less bandwidth in the outgoing TS than in each TS entered. According to a further embodiment, a method is provided for opportunely producing bit streams that carry compressed program data in an asynchronous communication link. A synchronous interface (adapter) provides a stream of bits that contains transport packets. The processor allocates send times to each of the selected transport packets to maintain a predetermined bit rate of a program for which each selected transport packet carries data and to cause average latency for each selected transport packet. At times that depend on each of the sending times, the asynchronous communication interface receives one or several commands and responds by transmitting the corresponding selected transport packets approximately at the time of sending in order to minimize a fluctuation of the Selected transport packages. Illustratively, the commands are generated as follows. The processor queues the transmission descriptors that contain the previous sending times in a transmission queue. The processor assigns an adapter of the remultiplexer node to service the transmission queue by the asynchronous interface. The data link control circuit of the assigned adapter causes the issuance of each command when the dispatch times of the descriptors are equal to the time of the reference clock in the adapter. Several of these techniques can be used to allow distributed network remultiplexing. A network is provided with one or several communication links, and several nodes, interconnected by the communication links in a communication network. A destination node receives a first data stream containing data from one or more programs through one of the communication links, the first bit stream having one or more predetermined bit rates for portions thereof. The destination node may be a remultiplexer node in accordance with what is described above and in any way includes a processor. The processor selects at least part of the first bit stream received for transmission, and programs the transmission of the selected part of the first bit stream in order to send the selected part of the first bit stream in a TS at a speed which depends on a predetermined speed of the chosen part of said first bit stream. Alternatively, communication links collectively form a shared medium of communication. The nodes are divided into a first set of one or more nodes to transmit one or more streams of bits in the shared communication medium, and a second set of one or more nodes to receive the bit streams transmitted from the communication medium. shared. The nodes of the second set select portions of the transmitted bitstreams and transmit one or more remultiplexed TSs as a stream of bits containing the selected portions. Each of the remultiplexed TSs transmitted is different from the bit streams received from the transmitted bit streams. A controller node is provided to select the first set and the second set of nodes and to cause the selected nodes to communicate with the bit streams through the shared communication medium in accordance with one of several different signal flow patterns, including at least one signal flow pattern that is different from a topological connection of the nodes with the shared communication medium. Finally, a method is provided for synchronizing the reference clock in each of the multiple circuits that receive and transmit transport packets in a remultiplexing system. The reference clock in each circuit that receives transport packets is to indicate a time in which each transport packet is received. The reference clock in each circuit that transmits transport packets is to indicate when to transmit each transport packet from there. A master reference clock is designated, to which each of the reference clocks must be synchronized. The current time of the master reference clock is obtained periodically. Each reference clock is adjusted in accordance with a difference between the respective time in the other reference clocks and the current time of the master reference clock in order to equate a time of the respective reference clock with a corresponding time of the reference clock teacher. Thus, in accordance with the invention, a more flexible remultiplexing system is provided. Increased flexibility improves multiplexing and decreases the overall cost of the system. BRIEF DESCRIPTION OF THE DRAWING Figure 1 shows a remultiplexing environment in accordance with another embodiment of the present invention. Figure 2 shows a remultiplexer node employing an asynchronous platform in accordance with one embodiment of the present invention. Figure 3 shows a flow chart schematically illustrating how transport packets are processed according to their PIDs in a remultiplexing node in accordance with an embodiment of the present invention. Figure 4 shows a distributed network remultiplexer in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION For clarity, the description of the invention is divided into sections. Remultiplexer environment and generalities Figure 1 shows a basic remultiplexing environment 10 in accordance with one embodiment of the present invention. A controller 20 provides instructions to a remultiplexer 30 employing, for example, any remote procedure call (RPC) protocol. Examples of RPCs that can be used include the digital distributed computing environment (DCE) protocol and the open network calculation protocol (ONC). DCE and ONC are network protocols that use stacks of protocols that allow a client to execute a subroutine either locally on the same platform (for example, controller 20) or on a different remote platform (for example, on remultiplexer 30) . In other words, the client process can issue control instructions simply by subroutine call. The DCE or ONC processes send the appropriate signals and appropriate commands to the remultiplexer 30 to effect the desired control. The controller 20 can take the form of a computer, such as a computer compatible with a PC. The controller 20 includes a processor 21, for example one or more Intel® Pentium II® integrated circuits, a main memory 23, a disk memory 25, a monitor and a keyboard / mouse 27 and one or more input / output devices ( I / O) 29 connected to a bus 24. The input / output device 29 is any suitable input / output device 29 for communicating with the remultiplexer 30, according to the way in which the remultiplexer 30 is implemented. Examples of an E / device S 29 of this type include an RS-422 interface, an Ethernet interface, a modem, a USB interface. The remultiplexer 30 is implemented with one or several "electronic devices" connected in a network. In the remultiplexer architecture of the example described below, remultiplexer electronic devices 30 can be computers compatible with independent PCs interconnected through communication links such as Ethernet, ATM or DS3 communication links. For example, a remultiplexer 30 includes one or several electronic devices each one being compatible computers with independent PCs interconnected through an Ethernet network (10 BASE-T, 100 BASE-T, or 1000 BASE-T, etc.). As shown, one or more TSs to be remultiplexed, namely TS1, TS2 and TS3, are received in the remultiplexer 30. As a result of the remultiplexing operation of the remultiplexer 30, one or several TSs, namely TS4 and TS5, are sent from remultiplexer 30. Remotely reproduced TSs TS4 and TS5, illustratively, include at least some information (at least one transport packet) from the entered TSs, TS1, TS2 and TS3. At least one storage device 40 is also provided, for example a disk or server memory. The storage device 40 can produce TSs or data as information entered to be remultiplexed for remultiplexing in the TSs produced, TS4 or TS5 by the remultiplexer 30. In the same way, the storage device 40 can store information of TSs or data produced by the remultiplexer 30, such as for example transport packets extracted or copied from the entered TSs, TSl, TS2 or TS3, other information received in the remultiplexer 30 or else an information generated by the remultiplexer 30. One or several sources of data injection 50 and one or more data extraction destinations 60. These sources 50 and destinations 60 can be implemented as PC compatible computers. However, the sources 50 can also be devices such as cameras, video recorders, demodulators / communication receivers and the destinations can be display monitors, video recorders, communication modulators / transmitters, etc. The data injection sources 50 supply TS, ES or other data to the remultiplexer 30, for example, for remultiplexing in the output TSs TS4 and / or TS5. In the same way, the data extraction destinations 60 receive TS, ES or other data from the remultiplexer 30, for example, which is extracted from the entered TSs, TSl, TS2 and / or TS3. For example, a data injection source 50 can provide to produce each of the entered TSs, to remultiplex, TSl, TS2 and TS3, and a data extraction destination 60 can be provided to receive each remultiplexed TS produced TS4 and TS5 . The environment 10 can be considered as a network. In such a case, the controller 20, each data injection source 50, the storage device 40, the data extraction destination 60 and the electronic network devices of the remultiplexer 30 in the environment 10 can be considered as a node of the communications network. Each node can be connected through a synchronous or asynchronous communication link. In addition, the separation of the devices 20, 40, 50 and 60 from the remultiplexer 30 is simply for convenience. In an alternative embodiment, the devices 20, 40, 50 and 60 are part of the remultiplexer 30. Remultiplexer architecture Figure 2 shows a basic architecture for one of the electronic network devices or nodes 100 of the remultiplexer 30, which is known below as "a remultiplexer node" 100. The particular remultiplexer node 100 illustrated in FIG. 2 can serve as the entire remultiplexer 30. Alternatively, as will be apparent from the comments that follow, several portions of the remultiplexer node 100 can be distributed in separate nodes interconnected between them by synchronous or asynchronous communication links. In another embodiment, multiple remultiplexer nodes 100, which have the same architecture as illustrated in FIG. 2, are interconnected with each other through synchronous or asynchronous communication links and can be programmed to act in a common manner. These last two modalities are known here as remultiplexers distributed in a network. Illustratively, the remultiplexer node 100 is a PC computer platform compatible with Windows NT®. The remultiplexer node 100 includes one or more adapters 110. Each adapter 110 is connected to a bus 130, which illustratively is a bus compatible with PCI. A guest memory 120 is also connected to bus 130. A processor 160, such as an Intel® Pentium II® integrated circuit, is also connected to bus 130. It will be noted that the single bus architecture illustrated in FIG. 2 can be a simplified representation of a more complex bus structure. In addition, more than a processor 160 may be present which cooperate to carry out the processing functions described below. Illustratively, two interfaces 140 and 150 are provided. These interfaces 140 and 150 are connected to bus 130, although they may in fact be directly connected to an input / output expansion bus (not shown) connected in turn to bus 130 to through an entry / exit bridge (not illustrated). The interface 140 is illustratively an asynchronous interface, such as an Ethernet interface. This means that the data transmitted through the interface 140 is not guaranteed to occur at a precise time and may experience a variable end-to-end delay. On the other hand, interface 150 is a synchronous interface, such as an IT interface. The communication on the communication link connected to interface 150 is synchronized to a clock signal maintained at interface 150. Data is transmitted through interface 150 at a particular time and a constant end-to-end delay is experienced. Figure 2 also shows that the remultiplexer node 100 can have an optional encoder / decoder (which can be implemented as an encryption / decryption device) 170 and / or a satellite receiver 180 of global positioning (GPS). The encoder / decoder 170 is for encoding or decoding data in transport packets. The receiver of GPS 180 is for receiving a uniform clock signal for synchronization purposes of the remultiplexer node 100. The purpose and operation of these devices is described in more detail below. Each adapter 110 is a specialized type of synchronous interface. Each adapter 110 has one or more data link control circuits 112, a reference clock generator 113, one or more transport packet cache descriptor 114, an optional encoder / decoder 115 and one or more control circuits DMA 116. These circuits can be part of one or more processors. Preferably, they are implemented using finite-state automata, that is, as in one or more ASICs or sets of gates (PGAs, FPGAs, etc.). The purpose of each of these circuits is described below. The reference clock generator 113 is illustratively a 32-bit offset counter which counts at 27 MHz. The system time produced by the reference clock generator 113 may be received in the data link control circuit 112. In addition , the processor 160 may have direct access to the reference clock generator 113 in the following manner. The processor 160 can read the current time of the system from an input / output register of the reference clock generator 113. The processor 160 can load a particular value in this same input / output register of the reference clock generator 113. Finally, the processor 160 can set the count frequency of the reference clock generator in an adjustment register in such a way that the reference clock generator 113 counts at a frequency within a particular range.

The purpose of the cache 114 is to temporarily store the next transport packet to be sent or the next transport packets to be sent waiting for the output of the adapter 110 of the last transport packet or of the last transport packets recently received in the adapter 110. The use of the cache 114 allows the reception and storage of transport packets or their recovery and sending with a minimum latency (notably without incurring transfer latency on the bus 130). The cache 114 also stores descriptor data for each transport packet. The purpose and structure of such descriptors is described in more detail below. In addition, the cache 114 stores a filter map that can be downloaded and modified by the processor 170 in normal operation. Illustratively, cache 114 may also store control word information for use in encoding or decoding, in accordance with what is described in more detail below. In addition to the processor 160, the cache 114 is accessed through the data link control circuit 112, the DMA control circuit 116 and the optional encoder / decoder 115. As is known, the cache 114 may possess a facsimile copy. or modified the data in the guest memory 120. Similarly, when required, the cache 114 must obtain the modified copy of data in the guest memory and not an old copy in its possession. The same is true in the case of the guest memory 120. A "proprietary protocol" is used where only a single device, such as a cache 114 or a guest memory 120, is authorized to modify the contents of a storage location. of data at a given moment. Here, the cache 114 is said to gain control of the data storage location when the cache has sole control of modifying the content of such storage locations. Typically, the cache 114 obtains control of the storage location and a facsimile copy of the data stored there., modify its copy but postpone the writing of the modifications of the data to the guest memory until a later date. By implication, when the cache writes data to the storage location in a guest memory, the cache 114 leaves control to the guest memory 120. The DMA control circuit 116 is for transferring data from transport packets and descriptor data between the host memory 120 and the cache 114. The DMA control circuit 116 can maintain a sufficient number of transport packets (and descriptors thereof) in the cache 114 to allow the data link control circuit 112 to produce transport packets in the TS output continuously (ie, in segments of successive time). The DMA control circuit 116 may also obtain control of a sufficient number of descriptor storage locations, and packet storage locations indicating, in the cache 114. The DMA control circuit 116 obtains control of such transport packet storage locations and descriptors for the cache 114. This allows a continuous allocation of storage locations of transport packets and descriptors to incoming transport packets as they are received (ie, from successive time slots). The data link control circuit 112 is for receiving transport packets from an incoming TS or for transmitting transport packets at an outgoing TS. When transport packets are received, the data link control circuit 112 filters and retains only the selected transport packets received from the incoming TS as specified in a downloadable filter map (provided by the processor 160). The data link control circuit 112 discards the other transport paysels. The data link control circuit 112 assigns the next unused descriptor to the received transport packet and stores the transport packet received in the cache 114 for transfer to the storage location of transport packets indicated by the assigned descriptor. The data link control circuit 112 also obtains the reference time from the reference clock generator 113 which corresponds to the reception time of the transport packet. The data link control circuit 112 records this time as the reception time printout in the descriptor indicating the storage location of transport packets where the transport packet is stored. When packets are transmitted, the data link control circuit 112 retrieves descriptors for outbound transport packet from the cache 114 and transmits the corresponding transport packets in time segments of the outgoing TS that occur when the time of the Reference clock generator 113 is approximately equal to the shipping times indicated in the respective descriptors. The data link control circuit 112 further carries out the final PCR correction in transport packets extracted as necessary in such a manner that the PCR indicated in the transport packets is synchronized with the precise alignment of the transport packet in the transport packet. Exit TS The processor 160 is for receiving control instructions from the external controller 20 (FIG. 1) and for transmitting commands to the adapter 110, and the interfaces 140 and 150 for purposes of controlling them. In response, to said instructions, the processor 160 generates a PID filter map and downloads said map to the cache 114, or modifies the PID filter map already resident in the cache 114, for use by the PID filter control circuit. data link 112 in the selective extraction of the desired transport packets. In addition, the processor 160 generates receive interrupt handlers to process each transport packet received based on its PID. The receive interrupt handlers may cause the processor 160 to again topoize the PID of a transport packet, estimate the time of departure of a transport package, extract the information in a transport package for additional processing, etc. In addition, the processor 160 formulates and executes transmission interrupt handlers that cause the processor to properly sequence transport packets for output, generate send times for each transport packet, correct approximately the PCRs in transport packets, and insert PSI in a TS of exit. The processor 160 may also help to encode and decode according to what is described in more detail below. The guest memory 120 is for storing transport packets and descriptors associated therewith. The guest memory storage locations 120 are organized in the following manner. A buffer 122 is provided which contains multiple reusable transport packet storage locations for use as a set of transport packets. The descriptor storage locations 129 are organized into several rings 124. Each ring 124 is a sequence of descriptor storage locations 129 from an initial memory address or ring upper part 124-1 to a final memory address or ring bottom 124-2. A ring 124 is provided for each output TS transmitted from the remultiplexer node 100 and a ring 124 is provided for each incoming TS received at the remultiplexer node 100. Other rings 124 may be provided in accordance with that described in more detail then. A queue is implemented in each ring 124 by designating a pointer 124-3 towards a tail head or first descriptor storage location 129 assigned / used in the queue and a pointer 124-4 towards a rear of the queue or last descriptor storage location used / assigned 129 in the queue. The descriptor storage locations 129 are assigned to incoming transport packets starting with the unused / unassigned descriptor storage location 129 immediately after the rear 124-4. The descriptor storage locations 129 for producing transport packets are retrieved from the queue starting from the descriptor storage location 129 indicated by the head 124-3 and proceeding in sequence to the rear 124-4. When the Descriptor storage location descriptor 129 is reached at the end of the ring 124-2, the assignment or retrieval of descriptors from the descriptor storage locations 129 proceeds with the Descriptor storage location descriptor 129 that It is located on top of ring 124-1. As shown, each descriptor stored in each descriptor storage location 129 includes a number of fields 129-1, 129-2, 129-3, 129-4, 129-5, 129-6, 129-7, 129- 8, 129-9 and 129.10. Established briefly, the purpose of each of these fields is as follows. Field 129-1 is for storing command attributes. Processor 160 may employ individual bits of the command attribute field to control the transmission of transport packets and retrieval of descriptor data from adapter 110. For example, processor 160 may preset a bit in field 129-1 of a descriptor at the descriptor storage location 129 indicated by the background 124-2 of the ring 124 in order to indicate that the descriptor storage location 129 indicated by the top pointer 124-1 follows the descriptor storage location 129 indicated by the background pointer 124-2. Field 129-2 is for storing programmatic status bits. The adapter 110 does not have access to these bits or modify them and these bits can be used by the processor 160 for any purpose not involving the adapter 110. Field 129-3 is for storing the number of bytes of a transport packet. departure, to be sent (typically 188 bytes in the case of MPEG-2 transport packets but can be set as a greater or lesser number when the descriptor indicates packets according to a different transport protocol or to "join" and "disperse" the support, where packages are fragmented into multiple storage locations or assembled from fragments stored in multiple storage locations of packages). Field 129-4 is to store a pointer to the storage location of transport packets to which the descriptor corresponds. This is illustrated in Figure 2 through the arrows from the descriptors in the descriptor storage locations 129 in the ring 124 for specific storage locations of the transport packet set 122. The 129-5 field is for storing the time of receipt of an incoming received transport packet or to store the delivery time of a transport packet to be transmitted outgoing. Field 129-6 is for storing several exceptions / several errors that may have occurred. The bits of this field can be used to indicate a bus error 130, a data link error in the communication link to which the data link control circuit 112 is connected, the reception of a short or long packet ( that has less than 188 bytes or more than 188 bytes), etc. Field 129-7 is for storing status bits that indicate aspects of different states of a descriptor such as whether or not the descriptor is valid, invalid pointing to a packet with error, etc. For example, we assume that several devices must process the descriptor and / or package applied in succession. In this case, four status bits are preferably provided. The first two of these bits can be set to values 0, 1, 2 or 3. The value 0 indicates that the descriptor is invalid. The value 1 indicates that the descriptor is valid and can be processed by the last device that must process the descriptor and / or package to which it points. The value 2 indicates that the descriptor is valid and can be processed by the antepenultimate device that must process the descriptor and / or package to which it points. The value 3 indicates that the descriptor is valid and can be processed by the antepenultimate device that must process the descriptor and / or package to which it points. The last two bits indicate yes or no the descriptor has been obtained from the guest memory 120 towards the cache 114 and whether or not the descriptor has finished processing on the adapter 110 and can be stored in the guest memory 120. Other bits of status can be provided in accordance with what is described in more detail below. Field 129-8 contains a transfer account that indicates the number of bytes in an incoming transport packet received. Field 129-9 is for storing a coding / decoding control word or other information for use in coding or decoding. For example, the processor 160 may store a control word (encryption / decryption key) in a control word table stored in the cache 114 in this field 129-9. Field 129-10 is for storing a programmed estimated exit time, the actual exit time or the actual reception time. In accordance with what is described in more detail below, this field is employed by processor 160 to order incoming transport packets received for output or to record the time of reception of incoming transport packets. Illustratively, a data link control circuit 112, a DMA control circuit 116 and a ring 124 are required for the reception of transport packets in a single input port, and a data link control circuit 112, a DMA control circuit 116 and a ring 124 are required for the transmission of data packets from a single output port. The descriptors stored in queues associated with input ports are known here as receive descriptors and the descriptors stored in queues associated with output ports are referred to herein as transmission descriptors. As, as indicated above, the input and output ports mentioned above may be the input port or output port of the communication link to which the data link control circuit 112 is connected or the input port or output port of the data link control circuit 112. communication link of another interface 140 or 150 in the remultiplexer node 100. The adapter 110 is illustrated having only a single data link control circuit 112 and a. single DMA control circuit 116. This is merely to illustrate - since multiple data link control circuits 112 and multiple DMA control circuits 116 can be provided in the same adapter 110. Alternatively, or additionally, multiple adapters 110 in the remultiplexer node 100. Basic operation of transport packet reception, remultiplexing and transmission We now consider the basic operation of the remultiplexer node 100. The operator has a series of choices as to how to operate the remultiplexer node 100. In a first way of operating the remultiplexer node 100, we consider that the operator wishes to selectively combine program information of two TSs, namely, TSl and TS2, into a third TS namely, TS3. In this scenario, we will consider that the operator does not initially know which programs, ESs or PIDs are in the two TSs to be remultiplexed, TSl and TS2. In addition, the TS1 is received illustratively in a first adapter 110, the TS2 is received in an illustrative manner in a second adapter 100, and the TS3 is transmitted in an illustrative manner from a third adapter 110 in the same remultiplexer node 100. As will be seen from the following description, each of the TSl and TS2 can be received through synchronous or asynchronous interfaces in the same node or in different nodes, and the selected portions of TSl and TS2 can be communicated to a third node through a network of arbitrary configuration to selective combination to form TS3 in the third node.

The operation in accordance with this form can be summarized as (1) acquiring the content information (program, ES, PAT, PMT, CAT, NIT, etc., and PIDs) of the TSs entered, remultiplexing, TS1 and TS2; (2) report the content information to the operator in such a way that the operator can formulate a user specification; and (3) receive a user specification to build the remultiplexed TS produced, TS3, and dynamically build the remultiplexed TS, TS3, from the content of the TSs entered to remultiplex, TS1 and TS2, according to the user's specification. To allow acquisition of the content information, the transport processor 160 assigns a receive queue to each of the first adapter 110 and second adapter 110 that receive the TSs, TS1 and TS2, respectively. To acquire the content, of TSl and TS2, transport packets are not discarded in adapters 110 for TSl or TS2, initially. Thus, the processor 160 loads a map of filters in the caches 114 of each of the first adapter and second adapter 110 that receive the TSs, TSl and TS2, causing each transport packet to be retained and transferred to the guest memory 120. As each transport packet of a TS (for example, the TS1) is received in its respective adapter 110, the data link control circuit 112 allocates the following unused descriptor (following the descriptor stored in the storage location of descriptors in the back 124-4 of the receiving queue), to the incoming transport packet, received. The data link control circuit 112 stores each received transport packet in a transport packet storage location of the cache 114 to which the allocated descriptor points. The DMA control circuit 116 writes each transport packet to its corresponding storage location of the array 122 in the guest memory 120 and writes the descriptor data of the descriptors assigned to the transport packets at their respective descriptor storage locations. the reception queue. The DMA control circuit 116 may further obtain control of the following unassigned descriptor storage locations 129 of the reception queue (after the storage locations of the sequence of descriptors 129 for which the DMA control circuit 116 has previously obtained control), copies of the descriptors stored there and the storage locations of transport packages to which the descriptors point. Control of said storage locations of unassigned, unused transport packets and descriptors is provided to the cache 114 for use by the data link control circuit 112 (i.e., the assignment to future transport packets received. from TSl). After the DMA control circuit 116 has written i = l transport packets and descriptor data assigned to these in the array 122 and the receive queue, the DMA control circuit 116 generates an interrupt. Illustratively, the number i can be selected by the operator using the controller 20 and set by the processor 160. The interrupt causes the processor 160 to execute an appropriate "PID" handler subroutine for each received transport packet. Alternatively, another technique such as combination or a timer-based process may be employed to start the processor 160 to execute a receiving PID manipulator subroutine for each received transport packet. For clarity, an interruption paradigm is employed to illustrate the invention. With reference to Figure 3, the processor 160 illustratively has a set of PID manipulator subroutines for each adapter 110 (or other device) that receives or transmits a TS during a remultiplexing session. Figure 3 illustrates two types of PID manipulator subroutine sets, namely a receiver PID manipulator subroutine set and a transmission PID manipulator subroutine set. Each DMA control circuit 116 generates a different recognizable interrupt thus allowing the processor 160 to determine which set of PID manipulator subroutines to choose. In response to the interruption by the DMA control circuit 116, the processor 160 executes the step S2 according to which the processor 160 examines the PID of each transport packet pointed by a newly stored descriptor in the receiving queue of the processor. interrupt adapter 110. For each PID, processor 160 queries a table of pointers to reception PID manipulator 402 subroutines specific to adapter 110 (or other device) that interrupted processor 160. We consider the first adapter 110 as receives TSl interrupts processor 160, in such a case processor 160 determines to query a table of pointers to receive PID manipulator subroutines 402 specific to adapter 110 that received TS, TSl. The table of pointers to receiving PID manipulator subroutines includes 8192 entries, including an input indexed by each permissible PID (said PIDs have 13 bits according to MPEG-2). Each indexed entry contains a pointer to a subroutine or an address of a subroutine RIV0, RIV1, .... RIV8191, to be executed by the processor 160. Using the PID of each transport packet, the processor 160 indexes the input of the table of pointers to subroutines 402 of receiver PID manipulator in order to identify the pointer to the subroutine to execute for this particular transport packet. Each subroutine indicated by the respective pointer, and executed by the processor 160, is specifically topographed by each PID by virtue of the pointer table 402 to achieve the user specification. Each subroutine is profitably predefined and simply mapped by the pointer table 402 according to the user specification. Each subroutine is composed of a set of one or several basic building block processes. Some examples of basic building block processes include: (1) PAT acquisition: Initially, this process is included in the subroutine indicated by RIVO, the reception PID manipulator subroutine for PID 0x0000. In executing this process, processor 160 illustratively extracts the PAT section carried in the currently processed transport packet and loads the PAT section into the PAT maintained in memory. Note which multiple versions of the PAT can be used since the programs carried in the TS can change from time to time. The processor 160 may identify different versions of the PAT and separately add and maintain a copy of each version of the PAT in a guest memory 120. The processor 160 may also identify which version of the PAT is currently in use at any time based on the PAT. information contained in several sections of the PAT. The processor 160 also uses information carried in each updated PAT section to identify program numbers of programs ported in the TS at this time and the PIDs of the PMT sections or program definitions for these program numbers. Using such program numbers, the processor 160 can modify the pointer table 402 so that the receiving PID manipulator subroutine inserts an appropriate PID pointer (marking of transport packets carrying PMT sections) to execute a subroutine containing a process to acquire sections of PMT / program definitions. (2) Acquisition of PMT sections / program definitions: in this process, processor 160 extracts the PMT section or program definition contained in the currently processed transport packet and updates the respective portion of the PMT with the program definition extracted with the extracted PMT section data. Like the PAT, numerous versions of the PMT can be used and the processor 160 can determine in which PMT to store the extracted PMT section or the extracted program definition data. The processor 160 may employ PMT information to update a PID filter map used to discard program transport packets that should not be included in the remultiplexed TS, to identify control words to decode ESs and to select subroutines to process contained PCRs in transport packages that have PIDs in accordance with what was identified in the PMT. (3) PID re-mapping: this causes the processor 160 to overwrite the PID of the corresponding packet with a different PID. This is desirable to ensure the unique character of PID assignment. That is, MPEG-2 requires which transport packets that carry different contents, for example, data from different ESs, data from different PSI streams, etc., be marked with mutually different PIDs, if said transport packets carrying different contents they must be multiplexed in the same remultiplexed TS produced and carried in the same remultiplexed TS produced. Otherwise, a decoder or other device could not distinguish transport packets that carry different types of data for extraction, decoding, etc. It is possible that a certain PID is used in TSl to mark transport packets carrying a first data type and the same PID is used in TS2 to mark transport packets carrying a second type of data. If the transport packets of the first type and the second type must be included in the remultiplexed TS produced, TS3, then at least one of the two types of transport packets must be highlighted with a new PID to ensure their unique character. (4) Disposal of transport packages: as the name suggests, processor 160 simply discards the transport package. For this purpose, processor 160 allocates the descriptor that points to the discarded transport packet. The descriptor deallocation can be achieved by the fact that the processor 160 adjusts the sequence of descriptors resident in the descriptor storage locations 129 of the queue to remove the descriptor for the removed transport packet (eg, the processor identifies all the descriptors assigned which follows the descriptor of the transport packet to be deleted in ring 124 and moves them to the descriptor storage space of the immediately preceding descriptor). The deallocation of the descriptor creates a descriptor storage space 129 in the receive queue for reassignment. (5) Establishment of PCR marker: the PMT indicates, for each program, the PIDs of the transport packets carrying the PCRs. However, only some of these transport packages carry PCRs. This can be easily determined by the processor 160 which determines whether the appropriate indicators in the transport packet are set (the adaptation_field_ control bits in the transport packet header and the PCR_ marker bit in the adaptation field). If the processor 160 determines that a PCR is present, the processor 160 sets a PCR marker bit in the attribute field 129-1 of the descriptor 129 associated with the respective packet. The purpose of this attribute marker bit is described in more detail below. In addition, the processor 160 calculates in an illustrative manner the current displacement of the reference clock generators 113 relative to the program encoder time clock of the program of which the PCR is a sample. The displacement can be determined through the following formula: displacement =? RTS12 -? PCR12; ? RTS12 = RTS2 - RTS1; and? PCR12 = PCR1 - PCR2 where:? PCR12 is a difference in successive PCRs for this program, PCR2 is the PCR in the transport packet currently processed, PCR1 is the PCR previously received for this program,? RTS12 is a difference in impressions of successive reception time, RTS2 is the reception time print recorded for the currently processed transport packet containing PCR2, and RTS1 is a pre-reception time print for the transport packet containing PCR1. After calculating the shift, PCR1 and RTS1 are set to be equal to PCR2 and RTS2, respectively. The displacement is used to adjust the PCR (if necessary) according to what is described below. (6) Calculation of estimated exit time: according to this process, the processor 160 estimates the (ideal) exit time of the transport package. Illustratively, this process is included in the receiving interrupt handler for each incoming transport packet received to remultiplex in an outgoing TS. The estimated exit time can be estimated from the reception time of the transport packet (in the field 129-5) and the known internal buffer delay in the remultiplexing node 100. The processor 160 writes the expected departure time in the field 129-10. (7) Insertion of encoding / decoding control word information: typically, in a coding technique or in a decoding technique, a dynamically varying control word, such as an encryption or decryption key, is required to actually encode or decode data in the transport package.

Common coding and decoding techniques employ nones and even keys, according to which a key is used to decrypt ES data and the next key to be used subsequently is transferred contemporaneously to the TS. A signal is then transmitted indicating that the most recently transferred key should now be used. The encoding / decoding control words can be specific to ES or can be used for a group of ESs (in a complete "conditional access system"). The decoding or coding control words must be maintained in a PID indexable table in the remultiplexer node 100. In accordance with what is described in more detail below, the processor 160 executing this process may insert the base address for the control word table, or the control word itself, in field 129-9 of a descriptor. Initially, the processor 160 selects a PID handler to acquire the PAT of each received TS, TS1 and TS2, and then discards each processed transport packet. In the course of receiving the PAT, PIDs from other transport packages carrying PSI, such as program definitions / sections of PMT, NIT, and CAT, and PIDs from other streams such as ES currents, streams of ECM, EMM currents, etc., is obtained. The receive PID manipulator subroutine for the PID of the PAT illustratively selects reception PID manipulator subroutines to acquire PMT, NIT, CAT, etc. This can be easily accomplished by making such subroutines available and by simply changing the pointers of the entries (indexed by appropriately identified PIDs) in table 402 to point to such PID manipulator subroutines. Note that a simple PID manipulator subroutine selection process can be performed dynamically even when transport packets are received and processed for TSl and TS2. The advantages of this situation are described in more detail below. Eventually, a sufficient amount of PSI for each TS, TSl and TS2, is acquired to allow the operator to create a user specification of the information to be sent on the TS3 remultiplexed TS. The processor 160 illustratively transmits to the controller 20 the acquired PSI information, for example, by using the asynchronous interface 140. The controller 20 is transmitted sufficient information to select a user specification. This information can be selective, for example, only a channel map of each TS that shows the program numbers contained there and the different types of ESs (described with designations of descriptive services such as video, audio, second audio presentation, subtitled text, etc.). Alternatively, the information may be exhaustive, for example, including the PIDs of each program, ECMs of ESs thereof, etc., and the controller 20 simply presents the information to the operator in a coherent and useful manner. Using the information provided, the operator generates a user specification for the TS produced to remultiplex, TS3. This user specification may specify: (1) the program numbers in each TS, TSl and TS2 to be preserved and sent in the remultiplexed TS, TS3, (2) the ESs of programs retained to be retained or discarded, (3) ESs , groups of ESs, programs or groups of programs to be decoded and / or encoded, and the source of control words to be used in the coding of each ES, group of ESs, program or program groups, (4) any new ECMs or EMMs to be injected or included in the remultiplexed TS produced TS, TS3 and (5) any new PSI information not automatically implied from the previous selections such as a NIT or CAT to be placed on the TS produced, TS3, specific PIDs that must be retopographed and the new PIDs to which they must be reprogrammed, PIDs assigned to other information (for example, burst data, in accordance with what is described below), generated in the remultiplexing node and carried in the TS, TS3, etc. The user specification is then transmitted from the controller 20 to the remultiplexer node 100 as, for example, through the asynchronous interface 140. The processor 160 receives the user specification and responds by selecting the PID manipulator subroutines. reception for the appropriate PIDs of each TS, received to remultiplex, TSl and TS2. For example, for each PID that marks a transport packet containing data to be retained, the processor 160 selects a subroutine where the processor inserts the process to estimate the exit time. For each PID that marks a transport packet containing encoded data, the processor 160 selects a subroutine that contains a process for selecting the appropriate control word and inserting it into the descriptor associated with said transport packet. For each PID that marks a transport packet containing a PCR, the processor 160 may select a subroutine that contains the process to set the PCR marker and to calculate the offset, etc. The dynamic adjustment of the user specification and / or PSI data is described in more detail below. The processor 160 assigns a transmission queue to each device that transmits a remultiplexed TS, that is, the third adapter 110 that produces the TS TS3. The processor 160 also loads the PID filter maps in each cache 114 of the first adapter and second adapter 110 that receive TSs TSl and TS2, with the appropriate values to retain the transport packets to be sent in remultiplexed TS, TS3, to retain others. transport packets containing PSI, to be able to track the contents of TSl, and TS2, and to discard the transport packet. In addition to selecting reception PID manipulator subroutines, assigning transmission queues and loading appropriate modifications to the PID filter maps, the processor 160 illustratively selects a set of transmission PID manipulator subroutines for each adapter (or other device) that sends a remultiplexed TS. This is illustrated in Figure 3. The transmission PID manipulator subroutines are selected based on a PID and transmission TS. As above, in response to receiving an identifiable interruption (e.g., from a data link control circuit 112 of an adapter 110 transmitting a produced TS, for example TS3), the processor 160 executes step S4 . In step S4, the processor 160 examines descriptors from the receive queues (and / or possibly other queues containing transport packet descriptors not yet programmed for output) and identifies up to j >; 1 descriptors indicating transport packets to be sent from the interrupt adapter 110. The number j can be illustratively programmed and advantageously set to be equal to the number k of the transport packet transmitted from a specific adapter 110 from the which output TS is transmitted between each moment when the specific adapter 110 interrupts the processor 160. When executing step S4, the processor 160 examines each receive queue for descriptors indicating transport packets destined for the specific output TSs. The processor 160 determines which transport packets are destined for the outgoing TS by consulting a table of pointers to transmit to subroutines 404 of transmission PID handlers. As in the case of table 402, table 404 includes one entry for each PID 0x0000 to OxlFFF and indexed for each PID of this type. Each indexed entry contains a pointer or address TIV0, TIV1, ..., TIV8191, of a subroutine to be executed in response to a respective PID. The table of pointers to the transmission PID manipulator subroutines 404 is formulated through a processor 160 in accordance with the user specification received from the controller 20, and modified as described below. Below we present illustrative processes that can be combined in a PID manipulator subroutine of transmission: (1) Nothing: If the current transport packet should not be produced in the remultiplexing TS (or another current) of the device that issued the interruption of transmission to the processor 160, the PID of a transport packet of this type topographs a subroutine containing only this process. In accordance with this process, the processor 160 simply jumps the transport packet and its descriptor. The examined descriptor is not counted as one of the transport packets to be produced from the specific adapter 110 that interrupted the 160 processor. (2) Sort the descriptor for transmission: If the current transport packet must be sent in remultiplexed TS ( or another current) of the device that issued the transmission interrupt to the processor, the PID of a transport packet of this type topographs a subroutine containing this process (as well as possibly others). According to this process, the processor 160 allocates a transmit descriptor for this transport packet. The processor 160 then copies the pertinent information into the reception descriptor that points to the transport packet to the newly allocated transmission descriptor. The assigned transmission descriptor is then ordered in the appropriate sequence within a transmission queue associated with the device that requested the interruption, for transmission. Particularly, the processor 160 compares the estimated departure time of the packet to which the newly assigned descriptor points, with the actual sending time (the actual time when the transport packet will be transmitted) recorded in the other descriptors in the transmission queue. If possible, the descriptor is placed in the transmission queue before the descriptors with a subsequent real delivery time compared to the estimated exit time of the descriptor and after the descriptors with a real delivery time before the departure time estimate of the descriptor. Said insertion can be achieved by copying each transmission descriptor, from the sequence of the transmit descriptors with actual send times subsequent to the estimated send time of the descriptor to be inserted, at the respective sequentially sequential descriptor storage location 129 of the queue. The data of the assigned transmission descriptor can then be stored in the descriptor storage location 129 which is available by copying the sequence. (3) Determination of the actual delivery time: The processor 160 can determine the actual delivery time of the transport packet to which the allocated descriptor tops based on the estimated departure time of the transport packet. The actual sending time is established by determining in which transport packet time segment of the multiplexed TS sent, T3, transmit the transport packet (to which the inserted and newly assigned transmission descriptor points). That is, the transport packet time segment of the sent TS, T3, which is closest in time to the estimated exit time, is selected. The transport packet is considered as sent at the time of the selected transport packet time segment, relative to the internal reference time as set by the generator (s) of reference clock 113 of the the) adapter (s) 110 (mutually synchronized as described below). The time associated with the respective transport packet segment time is assigned as the actual shipping time. The actual sending time is then stored in field 129-5 of the transmission descriptor. As described below, the actual send time is actually an approximate time in which the data packet control circuit 112 of the third adapter 110 (which sends the remultiplexed TS, T3) submits the corresponding transport packet for delivery . The actual output time of the transport packet depends on the alignment of the transport packet time slots, in accordance with what is established by an unknown external clock of the processor 160. Additional steps may be carried out, as described later, to remove the fluctuations of PCRs as a result of this lack of alignment. Consider that the bit rate of TS from which the packet was received (ie TS1, or TS2) may be different from the bit rate of the TS sent, namely TS3. In addition, the transport packets will be internally buffered by a predetermined delay (which depends on the length of the reception and transmission queues). However, considering that there is no contention between different TS transport packets received for the same remultiplexed TS transport packet time segment sent, TS3, all transport packets will have approximately the same latency at the remultiplexer node 100. Since the latency averages this same, no fluctuation is introduced in the transport packets. Consider now the case in which two transport packets are received almost at the same time from TSs, that is, TSl and TS2, and both must be sent on the remultiplexed TS, TS3. Both transport packets may have different estimated times of departure which however correspond to the same transport packet time segment (they are closest in time to the same transport packet time segment) of the remultiplexed TS sent, TS3. The transport packet that has the earliest estimated exit time (or reception time) is assigned to the time segment and the actual delivery time of this time segment. The other transport packet is assigned to the next transport packet time segment of the remultiplexed TS sent, TS3, and to the actual sending time thereof. Note that the latency of the transport packet assigned to the next time segment is different from the average latency of the other transport packets of this program. Thus, the processor 160 takes illustrative measures to remove the latency that this transport packet has, including the adjustment of a PCR of the transport packet (if a PCR is found there). (4) PCR shift and latency adjustment: This process is illustratively found in the subroutine indicated by the pointer of table 404 indexed by the transport packet PIDs containing PCRs. The processor 160 determines that the PCR latency setting is not only necessary if a transport packet is not assigned to the transport packet time segment of the remultiplexed TS sent, TS3, closest in time to time estimated output of the transport packet (as is done in the case of other transport packets of this program) and if the PCR marker is set in the respective reception descriptor. The PCRs are corrected for the displacement in time that the assignment to the non-ideal segment has. This adjustment is equal to the number of segments from the ideal segment by which the transport packet is moved for the segment time. All PCRs are adjusted for displacement in accordance with what is described below unless the input and output TSs are exactly aligned in time or unless the PCR is received from an asynchronous communication link. In the first case, the internal clock offset does not affect the time in which the PCRs are sent. In the second case, a different displacement adjustment is used in accordance with what is described below. In all other cases, the time in which the received PCRs are sent is affected by the displacement of the reference clock generator 113 of the adapters 110 that received the transport packet and the adapter 110 that transmits the transport packet with respect to to the PCR program clock. That is, the transport packet containing the PCR is marked with a reception time print obtained from the reference clock generator 113. This reception time printout is used to determine the estimated time of departure and the actual time of receipt. Shipping. In accordance with what is described in detail below, the transport packets are sent according to their actual sending time in relation to the reference clock generator 113 in the adapter 110 transmitting the TS, TS3, and all the reference clock generators 113 of all adapters 110 are kept in sync. However, the reference clock generators 113, while all are synchronized with each other, are subject to relative displacement relative to the encoder system time clock that generated the transport packet and its PCR. This offset can have an impact on the time at which each PCR is sent from the remultiplexer node 100 in the remultiplexed TS sent, for example TS3. According to the invention, the remultiplexing node corrects said displacement 100. As noted above, part of the receiving manipulator subroutine for PCRs of each program is to maintain a current displacement measurement. A measurement of the displacement of the reference clock generators 113 in relation to the encoder system time clock of each program is maintained. For each PCR, the current offset for the PCR program (ie, between the reference clock generators 113 and the encoder system time clock of this program) is subtracted from the PCR. With the aforementioned assignment of queues, the selection of PID manipulator subroutine and modification of PID filter maps, remultiplexing is carried out in the following manner. The transport packets of TS1 are received in the data link control circuit 112 of the first adapter 110. In the same way, the transport packets TS2 are received in the data link control circuit 112 of the second adapter 110. The data link control circuit 112 in each of the first adapter and second adapter 110 consults the local PID filter map stored in the cache 114 and selectively discards each transport packet having a PID indicating that the transport packet it should not be withheld. Each data link control circuit 112 retrieves the next unused / unassigned descriptor from the cache 114 and determines the storage location of transport packets associated with the descriptor. (As indicated above and as indicated below, the ADM control circuit 116 continuously obtains control of a sequence of one or more of the following unused / unassigned descriptors from the receive queue assigned to the input port of the circuit. data link control 112 and the storage locations of transport packets to which these descriptors point). The following unused, unassigned descriptor follows the descriptor stored in the descriptor storage location 129 indicated by the end pointer 129-4, said end pointer 129-4 is available for the data link control circuit 112. (As indicated above, if the end pointer 129-4 is equal to the bottom of the ring direction 129-2, the descriptor indicated by the pointer of end 129-4 will have the bit end of descriptor ring command set in field 129-7 by processor 160. This will cause the data link control circuit 112 to allocate the descriptor stored in descriptor storage location 129 at the top of ring direction 129-1 using a wrapped addressing technique). The data link control circuit 112 obtains at the time of the reference clock generator 113 corresponds to the time at which the first byte of the transport packet is received and stores this value as reception time printing in the 129-5 field of the assigned descriptor. The data link control circuit 112 stores the number of bytes of the transport packet received in field 129-8. Likewise, if errors occurred in the reception of the transport package (e.g., loss of data link cutter TS1, cut packet, long packet, packet with errors), the data link control circuit 112 indicates such errors by setting appropriate exception bits of 129-6. The data link control circuit 112 then establishes a bit in the status layer 129-7 which indicates that the descriptor 129 has been processed or processed with exceptions and stores the transport packet in the storage location of the transport packet. of the cache 114 indicated by the pointer in field 129-4. (note that in the case of a long packet, a sequence of more than one of the following unassigned unused descriptors may be assigned to the received transport packet and the excess data may be allocated in the packet storage locations associated with the packet. Such descriptors An appropriate grouping / diffusion bit is set in the attribute field 129-1 of the first descriptor to indicate that the packet has more data than in the single transport packet storage space associated with the first of the descriptors. A corresponding bit can also be set in the case of attributes 129-1 of the last of the descriptors to indicate that it is the last descriptor of a multiple descriptor transfer, such a long packet typically occurs when the adapter receives packets from a current other than a TS). The DMA control circuit 116 writes the transport packet to its corresponding transport packet storage location of the transport packet set 122 in the guest memory 120. The DMA control circuit 116 also writes descriptor data indicating the packet of data. described transport in the respective descriptor storage location 129 of the reception queue assigned to the respective adapter 110. Note that the DMA control circuit 116 can identify which transport packets to write to the guest memory 120 by determining which descriptors have established the complete state bits of processing in processing layer 129-7, and the storage locations of transport packets to which such descriptors point. Note that the DMA control circuit 116 can write descriptor data and transport packets, one by one, as each is completed alternately, the DMA control circuit 116 can allow the accumulation of a certain threshold number of transport pads and descriptors . The DMA control circuit 116 then writes data of a sequence of i > 1 multiple finished descriptors and transport packages.

In one embodiment, an encoder / decoder circuit 115 is placed in the adapter 110. In this case, before the DMA control circuit 116 writes data from a transport packet in the guest memory 120, the encoder / decoder circuit 115 decodes each transport packet for which decoding must be carried out. This is described in more detail later. When the DMA control circuit 116 writes descriptor data and transport packets in the host memory 130, the DMA control circuit 116 interrupts the processor 160. Such interrupts can be initiated by the DMA control circuit 116 every i > 1 descriptors for which data is written to host memory 130. The interrupt causes processor 160 to execute one of the receive PID manipulator subroutines for each transport packet that is specific to both PID and input TS. As indicated above, the receive PID manipulator subroutines are selected through the appropriate alteration of the pointers in table 402 in such a way that the processor 160, among other things, discards transport packets that should not be sent in the TS remultiplexed, write an estimated timeout in the descriptors that indicate the transport packets to be sent and set the PCR marker bit in the descriptors that point to transport packets containing PCRs. further, the selected reception PID manipulator subroutines preferably cause the processor 160 to continuously acquire and update the PSI tables, adjust the PID filter map and select additional receive PID manipulator subroutines as necessary to effect a certain specification of user. For example, a user specification may specify that a particular program number must be sent continuously in the remultiplexed TS, TS3. However, the ESs that constitute this program are subject to changes due, among other things, to an event limit. Preferably, the processor 160 will detect these changes in the constitution of ES by monitoring the changes in the PAT and PMT and will change the PID filter map and select reception PID manipulator subroutines as necessary to continue causing the sending of the ESs of the program selected in the remultiplexed TS, TS3, whatever the constitution of this program may be according to the moment. Contemporaneously, while carrying out the above functions associated with the reception of transport packets, a DMA control circuit 116 and a data control link circuit 112 in the third adapter 110 also perform certain functions associated with the transmission of transport packets in TS3. Each time the data link control circuit 112 of this third adapter 110 produces k >; 1 transport packets, the data link control circuit 112 generates a transmission interruption. Illustratively, k may be selected by the processor 160. This transmission interrupt is received in the processor 160 executing a transmission PID manipulator subroutine appropriate for the remultiplexed TS sent, TS3. Particularly, the processor 160 examines the descriptors at the head of each queue containing descriptors indicating transport packets to be sent on TS3. As indicated above, two receive queues contain descriptors indicating transport packets to be sent on TS3, including a receive queue associated with the first adapter 110 (which receives TS1) and a recession queue associated with the second adapter 110 (which receives TS2). As described below, the processor 160 may allocate additional queues containing descriptors indicating transport packets to be sent on TS3. The processor 160 identifies the descriptors that point to the following transport packets to be sent in TS3. This is achieved by executing the transmission PID manipulator brigades of the set associated with the third adapter 110 and indexed by the PIDs of the transport packets at the head of the receiving queues. As noted above, if the transport packet corresponding to a descriptor in the queue examined by the processor 160 should not be sent from the third adapter 110 (which generated the interrupt), the PID of this transport packet will index a subroutine PID manipulator for the third adapter 110 that does nothing. If the transport packet corresponding to the descriptor in the queue examined by the processor 160 is to be sent from the third adapter 110 (which generated the interrupt), the transport packet's PID will index a pointer to a transmission PID manipulator subroutine. which will do the following: (1) assign a transmit descriptor for the transport packet, (2) order the transmit descriptor in the transmission queue associated with the third adapter 110 in the correct order of transmission, (3) assign a actual dispatch time to the assigned descriptor and transport packet and (4) carry out an approximate correction of PCR in the transport packet to take into account displacement and latency, if necessary. Illustratively, the processor 160 examines the descriptors in queues (of reception) until the identification of j descriptors indicating transport packets to be sent in TS3 or from the third adapter 110. The descriptors are examined in order from the head 124-3 to the extremity 124-4. If multiple queues with candidate descriptors are available for examination, the processor 160 may examine the queues with return to the point of origin, in the estimated time order of the way out or other order that might be appropriate considering the content of the transport packets. which indicate the descriptors (in accordance with what is described below). The DMA control circuit 116 retrieves from the host memory 120 data of a sequence j > 1 descriptors of the queue associated with TS3 or third adapter 110. The descriptors are retrieved from the descriptor storage locations 129 in the queue in order from header pointer 124-3 to end pointer 124-4. The DMA control circuit 116 also retrieves from the host memory 120 the transport packets from the transport packet storage locations of the set 122 to which these recovered descriptors point. The DMA control circuit 116 stores these recovered descriptors and transport packets in the cache 114. The data link control circuit 112 sequentially recovers from the cache 114 each descriptor in the transmission queue, in the order from the pointer of head 124-3, and the transport packet in the transport packet storage location indicated by the descriptor. When the reference clock generator time 113 of the third adapter 110 is equal to the time indicated in the send time field 129-5 of the recovered descriptor, the data link control circuit 112 transmits the transport packet as it points the descriptor (in the storage location indicated by the header pointer 124-3), in TS3. The send time is only the approximate transmission time since each transport packet must be transmitted in alignment with the TS3 transport packet time segment limits. Such limits are established with reference to an unknown external clock of the processor 160. Note also that the PCRs of each transport packet may exhibit slight fluctuations for the same reason. Accordingly, the data link control circuit 112 finally corrects the PCRs in accordance with the precise transmission time of the transport packet containing it. Specifically, the precise transmission time is less than the estimated transport packet time end time. The data link control circuit 112 employs a transport time segment limit clock, previously connected to the time segment boundaries TS3, to make the final adjustment of the estimated PCRs (i.e., by adding the difference between the sending time and the actual transmission time to the PCR of the transport packet). Note that the data link control circuit 110 may employ the PCR marker bit of the descriptor to determine whether or not a PCR is found fresh in the transport packet (and therefore whether or not to correct it). After transmitting a transport packet, the data link control circuit 112 establishes the appropriate status information in field 129-7 of the descriptor indicating the transmitted transport packet and un-allocates the descriptor. The DMA control circuit 116 then writes this state information to the appropriate descriptor storage location of the transmission queue. In another form of operation, the operator already has complete knowledge of the content of the entered TSs that must be remultiplexed. In this case, the operator simply prepares the user specification and transmits the user specification from the controller 20 to the remultiplexer diode 110 (or remultiplexer nodes 100 when several nodes operate in combination on a distributed remultiplexer in network 100) . Preferably, several types of information on the content of the remixed TSs to be remixed (such as PAT, PMT, etc.) are nevertheless acquired continuously. This allows instant reporting of the content to the operator (through the processor 160 and controller 20), for example, to allow the creation of a modified user specification and to dynamically adjust the remultiplexing according to the modified user specification without ceasing entry of the user. the TSs to be remultiplexed, the output of the remultiplexed TSs or the remultiplexing processing of the remultiplexer 100. In addition to the above basic remultiplexing functions, the remultiplexer node 100 can perform more advanced functions. These functions are described individually below.

Dynamic re-multiplexing and insertion of program-specific information As indicated above, the operator can use the controller 20 to generate a user specification that specifies programs and ESs to be withheld or discarded, programs or ESs to be encoded or decoded (or both), retopografiado of PIDs, etc. In addition, the processor 160 preferably acquires content information continuously (eg, PAT, PMT, ACT, NIT, ECM, tables, etc. data). This allows a simply dynamic modification, in real time, or "in the air" of the user specification and an alteration without sutures of the remultiplexing according to the new user specification. Specifically, the operator can alter the user specification and cause the remultiplexer 30 to switch without sutures for remultiplexing in accordance with the new user specification. However, remultiplexer 30 ensures that each remultiplexed TS sent is always a stream of continuous bits containing an interrupted sequence or stream of transport packets. Thus, the content of the remultiplexed TSs (s) sent is modified without introducing discontinuities in the remultiplexed TS (s) sent, that is, without interruption in the train of transport packets sent or detentions in the bit stream sent. Modifications without prior sutures can be affected due to the use of a programmable processor 160 that controls the flow of transport packets between input and output adapters 110 or interfaces 140 and 150 and other circuits such as decoder / encoder 170. Consider that the choice to preserve or discard a different set of ESs can be achieved simply by setting by the processor 160 of the appropriate PID filter maps and PID manipulator subroutines selected by the processor 160 for each PID. The choice of decoding or encoding certain ESs or programs can be achieved through the processor 160 by altering the PID manipulator subroutines executed in response to the PIDs assigned to such ESs or programs to include the appropriate coding or decoding processes (described above and below) . A different selection of the output ports for sending a different combination of remultiplexed TSs sent can be achieved by the processor 160 by assigning queues of transmission descriptors for the new output ports, by de-allocating transmission descriptor queues to output ports not needed, by generating 404 tables of pointers to transmit PID manipulator subroutines for each new output port and by scrapping each pointer table 404 to and transmit transmission PID manipulator subroutines for each queue of unassigned transmission. Similarly, a different selection of input ports can be achieved through the processor 160 by allocating and unassigning receiving queues and by generating and discarding tables 402 of receiving PID handlers pointers for such assigned and de-allocated receiving queues, respectively. In addition to selecting the correct transport packets for sending, the remultiplexer node 100 also provides illustratively the correct Psi for each remultiplexed TS sent. This is achieved d the following way. The controller 20 (figure 2) generates a user specification for output TS. Consider the previous example where the remultiplexer node 100 remultiplexes two TSs, namely TSl and TS2 to produce a third TS, namely TS3. Illustratively, table 1 establishes the content of each TSl and TS2. Table 1 TSl Program ES PID A video A PID (VA) A audio A PID (AA) A data A PID (DA) PMT Def. of Prog. A PID (a) B video B PID (VB) B audio B PID (AB) PMT Def. of Prog. B PID (b) C video C PID (VC) C audio C PID (AC) C decrypted C PID (ECMC) PMT Def. of Prog. C PID (c) D video D PID (VD) D audio ID PID (AID) D 2D PID audio (A2D) D data D PID (DD) PMT def. of Prog. D PID (d) PAT PAT 1 0X0000 TS2 Program ES PID E video E PID (VE) E audio E PID (AE) PMT Def. of Prog. E PID (e) F video F PID (VF) F audio F PID (AF) F data F PID (DF) PMT Def. of Prog. F PID (f) G video G PID (VG) G audio G PID (AIG) G data G PID (A2G) G deciphered G PID (ECMG PMT Def. Of Prog. G PID (g) PAT PAT 2 0X0000 Preferably, the controller 20 programs the processor 160 to extract the information illustrated in the table I using the process of acquisition of PID manipulator subroutines We assume that the user specification specifies that only programs A, B, F, and G should be retained and sent in the remultiplexed TS TS3, the user indicates this specification to controller 20 (Figure 1), example using the keyboard / mouse 27 (figure 1) The controller 20 determines whether or not the user specification is valid, particularly, the controller 20 determines whether or not each remultiplexed output TS, such as TS3, has a width of enough band to send all the specified programs A, B, F and G as well as associated PSI (ie, program definitions a, b, f, g and new substitute PAT3 which will be described below). Said information on liquid transfer rate can be obtained from the processor 160 if it is not known yet. For example, the processor can execute a PID manipulator subroutine that determines the bit rate (or transport packet transfer rate) of each program from the received time impressions assigned to each transport packet of the program. each program that carries a PCR. As described above, said information is obtained in two ways by the processor 160 for purposes of carrying out PCR adjustment. If the user specification is not valid, the driver 20 does not download the user specification. If the specification is valid, the driver 20 downloads the user specification to the processor 160. Consider that the user specification can be satisfied by the TS3 output bandwidth. If it does not already have them, the processor 160 acquires the PAT and PMT of the entered TSs, TSl and TS2. Based on the information in PAT1 and PAT2, processor 160 constructs a substitute PAT3 that includes only the inputs of PAT1 and PAT2 indicating the PIDs of program definitions a, b, f, and g associated with 'programs A, B, F, and G. Again, this can be achieved by extending an appropriate PID manipulator subroutine for the PIDs of PAT1 and PAT2 and is preferably executed continuously to ensure that any changes to the programs, as reflected in PAT1 and PAT2, it is incorporated in a substitute PAT3. The processor 160 generates a transport packet sequence containing this new substitute PAT3 and stores them in the packet buffer 122. The processor 160 also generates a PAT queue of descriptors indicating the transport packets carrying PAT3, said queue it is preferably implemented in the form of a ring 124.

The PAT descriptor queue for transport packets PAT3 is profitably dedicated to storing only the substitute PAT3 information. The processor 160 also generates estimated times of output and stores them in the descriptors of the PAT queue indicating the PAT3 transport packets. The processor 160 can now service the PAT3 descriptor queue in the same manner as any of the receive queues in response to a transmission interruption. That is, when the data link control circuit 112 transmits k = l packets and interrupts the processor 160, the processor 160 will extract descriptors from the queue PAT3 as well as the receive queues. Collectively, all queues that contain descriptors that indicate transport packages to be sent, for which transmission descriptor in a transmission queue have not yet been assigned are referred to herein as "connection queues". The processor 160 then constructs appropriate filter maps and transfers a filter map to a first adapter 110 that receives TSl and a second filter map to a second adapter 110 that receives TS2, respectively. For example, the first filter map may indicate extracting and retaining transport packets with the PIDs: PID (VA), PID (AA), PID (DA), PID (a), PID (VD), PID (AB) and PID (b) (as well as possibly other PIDs that correspond to PSI in TSl) In the same way, the second filter map can indicate extracting and retaining transport packets with PIDs: PID (VF), PID (AF), PID (DF), PID (f), PID (VG), PID (AIG), POID (A2G), PID (DG), PID (ECMG) and PID (g) (as well as possibly other PIDs corresponding to the PSI in TS2) In response, the first data link control circuit and the second data link control circuit 112 receiving TS1 and TS2 extract only the transport packets TS1 and TS2 in accordance with the filter maps provided by the processor 160. As indicated above, the first data link control circuit and the second data link control circuit 112 store these extracted packets in a cache 114 and assign descriptore The first DMA control circuit and the second DMA control circuit 116 periodically write the extracted transport packets and descriptor data for them in the guest memory 120. The data of the descriptors written by the first DMA control circuit 116 is stored in respective descriptor storage locations 129 of a first receive queue for the first data link control circuit 112 and data of the descriptors written by the second DMA control circuit 116 are stored in descriptor storage locations of a second receive queue for the second data link control circuit 112.

In addition, a third control circuit DMA 116 retrieves descriptors from a transmission queue associated with TS3, and transport packets corresponding to them, and stores them in a cache 114. A third data link control circuit 112 recovers each descriptor from the cache 114 and transmits them in TS3. The third data link control circuit 112 generates an interruption after transmitting k = l transport packets. This causes the processor 160 to access the PID manipulator subroutine pointer table of transmission to transmit a queue associated with the third data link control circuit 112. When executing the appropriate transmission PID manipulator subroutine, the processor 160 allocates unused transmission descriptors of the transmission queue TS3 for available connection queue descriptors and copies relevant information in such assigned descriptors from descriptors in available connection queues, i.e., the first receive queue, the second receive queue and the queue of PAT3. The transmission descriptors are assigned in the transmission queue TS3 in an order that depends on the estimated sending time of the reception descriptors. Note also that any type of ISP can be dynamically inserted, including new program definitions, EMMs, ECMs, CAT or NIT.

Consider now a situation in which a new user specification is generated while remultiplexing occurs according to a previous user specification. As mentioned above, the controller 20 initially verifies if there is sufficient bandwidth to satisfy the new user specification. If this is the case, the new user specification is downloaded to processor 160. The new user specification may require processor 160 to extract different programs and ESs, PIDs topography differently or generate: (a) a new ISP, (b) transport packages that carry the new ISP; and (c) descriptors that indicate the transport packages that carry the new ISP. In the case of modifying the programs or ESs contained in TS3, the processor 160 modifies the PID filter maps to retain the transport packets to be retained and to discard the transport packets to be disposed according to the new user specification. The new filter maps are transferred to the respective cams 114 which dynamically and immediately switch to the extraction of transport packets according to the new user specification. The processor 160 also selects appropriate reception PID manipulator subroutine for the new transport packets to be retained by modifying the pointers of the receive PID manipulator subroutine pointers 402 associated with the PIDs of the new transport packets. to retain. Modifications can also be carried out in the case of pointers of tables 402 of reception PID manipulator subroutine pointers indexed by PIDs of transport packets now to be discarded. In the case of a new PID surveying, the processor 160 selects appropriate subroutines to carry out the new PID surveying. Such changes may require the generation of a new ISP, for example, a PAT. The processor 160 selects a PID manipulator subroutine to generate the new PSI. For example, in the case of a new PAT, the PID manipulator subroutines can be activated by the PIDs of the TSP and TS2 PATs. The processor 160 generates a new PSI and inserts the new PSI into transport packets. Descriptors are assigned in the respective PSI queue for such transport packets with new PSI. The processor 160 stops servicing (i.e., regenerating and transferring transport packets) to PSI descriptor queues indicating transport packets containing old PSI and otherwise serving the descriptor queues with new PSI. According to each change, ie, each newly selected PID manipulator subroutine, each PSI insertion modification or each new PID filter map is available, the appropriate data link control circuit 112 or processor 160 changes its operation without sutures . Until said change, the data link control circuit 112 or processor 160 continues to operate under the user's pre-specification. Some care should be taken when each change occurs in such a way that the remultiplexed TS sent always complies with MPEG-2. For example, any changes to PID surveying, PID filtering, ESs programs, ECMs, etc., in the TS that have an impact on PMT or PAT are preferably delayed until a new version of the PMT (or specific definitions) of the same program) and / or PAT can be sent in TS and until an indication for switching to the new PMT, program definition or PAT is indicated in the TS. In the same way, if EMMs are included or if EMMs are abandoned for a conditional access system, the instruction of said EMMs is delayed until the transmission of a new version of the CAT in the TS. An additional judicious arrangement of the changes may be desirable for the management of internal resource processing, for example storing a pointer to a receiving PID handler subroutine in the appropriate PID manipulator subroutine pointer table entry for a PID of a transport packet to be retained (which was previously discarded) before altering the PID filter map of the respective adapter 110 to retain transport packets with this PID, etc. Here is an example to modify remultiplexing in accordance with a new user specification. We assume that the user offers a new user specification indicating that programs B and F should be abandoned and instead programs C and D should be retained. In response, controller 20 first determines if there is sufficient bandwidth in the remultiplexed TS sent, TS3 to host all the new program data, and new PSI that must be generated for them, when modifying the remultiplexed TS, TS3, in accordance with the new user specification. Considering that said sufficient bandwidth exists, the new user specification is downloaded to the remultiplexer node 100. The processor 160 modifies the PID filter map on the first adapter 110 in order to discard transport packets with PID PIDs (VB ), PID (AB), PID (b), and conserve transport packets with PIDs PID (VC), PID (AC), PID (ECMC), PID (c), PID (VD), PID (AlD), PID (A2D), PID (DD) and PID (d). In the same way, the processor 160 modifies the PID filter map on the second adapter 110 in order to discard transport packets with PIDs PPID (VF), PID (AF), PID (DF), and PID (f). Processor 160 selects PID manipulator subroutines for PID (VC), PID (AC), PID (ECMC), PID (c), PID (VD), PID (AID), PID (A2D), PID (DD) PIDs and PID (d), including program definition update processes for each of the PIDs, PID (c) and PID (d), a word control update process for PID (ECMC), a process for inserting decoding control word information for each of the encoded ESs of program C, for example, PID (VC). The processor 160 also generates a different substitute PAT3 that includes the program definitions a, b, c, d, and g, for example, in the course of executing PID manipulator subroutines (0) for each of the first adapter and second adapter 110. Consider now in the case in which another new user specification is provided which indicates that the program video A VA must be encoded. Again, the controller 20 first determines that there is sufficient bandwidth in TS3 to accommodate transport packets carrying SM for VA and new program definitions for program A. Whereas there is sufficient bandwidth, the new user specification is downloaded to the remultiplexer node 100. The processor 160 allocates a queue to store descriptors pointing to transport packets containing the VA ECMs. The processor 160 selects an appropriate PID manipulator subroutine for PID (VA) including the insertion of a coding control word into the descriptors indicating transport packets containing VA. The processor 160 also generates transport packets containing the control words as ECMs for VA and assigns descriptors indicating these transport packets. This can be achieved by employing an interrupt manipulator subroutine driven by a timer. Alternatively, additional (not illustrated) or programmatic equipment executed by the processor 160 generates control words periodically and interrupts the processor 160 when such control words are ready. The processor 160 responds to such interrupts by placing an available control word in one or more transport packets, assigning ECM descriptors of an ECM queue for such transport packets and loading the control word into the appropriate control word table. Processor 160 also selects a receive PID manipulator subroutine for PID (a) that includes a process for extracting the information in the program definition to and adds information about ECMA (e.g., PID (ECMA), the ES that encrypts it, etc.). Coding / decoding control A problem associated with coding and decoding is the selection of the correct control word or correct key for each transport packet. That is, encoded transport packet data can be encoded with a specific control word for a PID or with a specific control word for a group of PIDs. A rotary control word scheme can be used, in which the control word changes from time to time. In summary, there may be a large number of control words (e.g., keys) associated with each TS and the control words are changed periodically. In the case of decoding, a mechanism must be offered to continuously receive control words for each ES to decode or ESs to be decoded and to select the appropriate control word at each moment. In the case of coding, a mechanism must be provided to select the correct control word to encode an ES or a group of ESs and to insert the control word used to encode ESs in the remultiplexed TS sent sufficiently before any data of It is encoded formed there. The descriptors and their order within the reception and transmission queues can be used to simplify the coding and decoding TSs. Particularly, each reception descriptor has a field 129-9 where information relevant to encoding or decoding can be stored, such as the control word to be used to encode the transport packet or a pointer indicating the word table of appropriate control that has control words for use in encoding or decoding the transport packet. Consider first the steps taken to decode a transport package. The TS containing transport packets to be decoded contains transport packets that carry ECM (conditional access to ES) and EMM (specific conditional access to an entire group of ESs). The EMMs are carried in transport packets marked with unique PIDs for the group ESs to which they correspond and ECMs are carried in transport packages marked with unique PIDs for the specific ES to which each ECM corresponds. The PIDs of the EMMs can be correlated with the specific groups ESs to which they correspond with reference to the CAT. The PIDs of the ECMs can be correlated with each specific ES to which they correspond by reference to the PMT. Processor 160 selects PID manipulator subroutines to: (1) recover each CAT and PMT transmitted in the TS and to identify which version of the CAT or PMT is currently being used, (2) by reference to the PMT, recover a table of ECMs indexed by the PIDs of the transport packages that carry the ESs to which they correspond. Then, the processor 160 defines a sequence of processing steps to be carried out in each transport packet and descriptor. That is, the processor 160 defines the specific order in which the data link control circuit 112 of the receiving adapter 110, the receiving adapter decoder 110 (optional), the receiving adapter DMA control circuit 116. 110, the decoder 170 (optional) and the processor 160 can process a reception descriptor or packet indicated by a reception descriptor. For this purpose, the processor 160 can transfer appropriate control information to each of the devices 112, 115 and 116 to have them process the transport packet and descriptor that indicates it in the specific order of the defined sequence of processing steps. compliance with what is described below. If decoding 115 of adapter 110 is employed, the order of processing in the sequence is defined as follows. The link control circuit 112 of an adapter 110 receives transport packets and assigns reception descriptors for selected packets not discarded according to the PID filter map described above. After storing each transport packet held in the cache 114, the data link control circuit 112 illustratively establishes the status bit (s) 129-7 in the descriptor that indicates the transport packet to indicate that the The transport packet can now be processed by the next device in the order of the defined sequence of the processing steps.

The decoder 115 periodically examines the cache 114 for the following descriptor or the following descriptors for which the status bit (s) 129-7 is set (n) to indicate that the decoder 115 is authorized to modify the packet Of transport. Illustratively, the decoder 115 has access to the cache 114 after the decoder 155 has processed m = l descriptors. The decoder 115 accesses each cache descriptor 114 sequentially from the descriptor which was previously accessed by the decoder 115 until access to the descriptors or to a descriptor having the bit (s). state 129-7 set to indicate that the processing of a previous step in the transport packet descriptor and packet is being performed indicating in the order of the defined sequence of processing steps. In the processing of descriptors and transport packets, the decoder 115 employs the PID of the transport packet to which the currently examined descriptor points, to index a decoding map located in the cache 114. Illustratively, the processor 160 periodically updates the map of decoding in the cache 114 in accordance with what is described below. The location of the decode map is provided by a base address located in the descriptor field 129-9. Illustratively, processor 160 loads the base address of the decode map in fields 129-9 of each descriptor when allocating the queues of reception descriptor. The indexed entry of the decoding map indicates whether or not the transport packet is encoded, and if it is encoded, one or more control words that can be used to decode the transport packet. The indexed entry of the decoding map may contain the control words corresponding to the PID of the transport packet or a pointer to a memory location in which the respective control word is stored. If the indexed entry of the decode map indicates that the transport packet pointed to by the descriptor to which it is accessed must not be decoded, the decoder 115 simply sets the status bit (s) 129-7 of the descriptor for indicate that the next processing step, according to the order of the defined sequence of the processing steps, can be carried out in the descriptor and transport package that it indicates. If the indexed entry of the decode map indicates that the transport packet must be decoded, the decoder 115 obtains the control word corresponding to the PID of the transport packet and decodes the transport packet data using the control word. Note that a typical decoding scheme employs control words in a rotating fashion (ie, nones and pairs) in accordance with what is described above. The correct control word or pair for use in the decoding of a transport packet is indicated by control bits in the transport packet, such as, for example, the control_code_of_transmission bits. The decoder 115 uses these bits, as well as the PID of the transport packet, to index the correct control word. That is, the map constructed and maintained by the processor 160 is indexed both by the PID and by the indicator (s) non (is) / pair (s). The decoder 115 then stores the decoded transport packet data in the storage location of transport packets indicated by the currently examined descriptor, thus overwriting the data prior to the decoding of the transport packet. The decoder 115 then establishes the status bit (s) 129-7 of the descriptor to indicate that the next processing step in the order of the defined sequence of processing steps can be carried out in the descriptor and transport packet. which indicates. The DMA control circuit 116 periodically writes transport packet data and descriptor data indicating them from the cache 114 to respective storage locations 122 and 129 of the guest memory 130. By doing this, the DMA control circuit 116 periodically examines a sequence of one or more descriptors in the cache 114 that follow (in order of receiving queue) the last descriptor processed by the DMA control circuit 116. If the bit (s) ) of state 129-7 of a examined descriptor indicates (in) that the processing by the DMA control circuit 116 can be carried out in the examined descriptor, the DMA control circuit 116 establishes a status bit (s) appropriate (s) 129-7 in the descriptor indicating that the next processing step, according to the order of the defined sequence of processing steps, can be carried out in the descriptor and in the transport packet it indicates. The DMA control circuit 116 then writes the data of the descriptor, and the transport packet indicating in the guest memory 130. However, if the status bit (s) 129-7 is set (n) to indicate that a processing step preceding the processing carried out by the DMA control circuit 116 is still performed in the descriptor, the DMA control circuit 116 does not process the descriptor and transport packet it indicates. Illustratively, when enabled, the DMA control circuit 116 examines the descriptors until the DMA control circuit 116 writes data of a sequence of i = l descriptors, and transport packets indicating these descriptors, or a descriptor is found that has status bit (s) 129-7 which indicates (n) that a preprocessing step, according to the order of the defined sequence of processing steps, is still performed in the descriptor. Each time a DMA control circuit 116 transfers i = l transport packets, the DMA control circuit issues an interrupt. The processor 160 responds to the interrupt issued for example by the execution by the DMA control circuit 116 of the appropriate reception PID manipulator subroutine. The processor 160 examines one or several descriptors of the reception queue, corresponding to the adapter 110 from which the interruption was received, starting from the last descriptor processed by the processor 160. Illustratively, the processor 160 executes only the manipulator routines Appropriate reception PID for the descriptors having a status bit (s) 129-7 set (s) indicating that processing by the processor 160 can be carried out in the descriptor. Each time the processor 160 is interrupted, the processor 160 illustratively processes descriptors, and transport packets indicating, until the execution of PID manipulator subroutines for i = the transport packet or until a descriptor is found for which (the) appropriate status bit (s) 129-7 is set to indicate that processing of a preprocessing step (according to the order of the defined sequence of processing steps) is still being performed in the descriptor. In the course of executing the appropriate reception PID manipulator subroutines, the processor 160 retrieves all the control words for all the ESs and updates the decoding tables and control words or maps that are used by the decode. (or 170 as described below). In a control word scheme having rotation, the processor 170 maintains multiple keys 8 ie, nones and pairs) for each PID in the table of control words or map. Processor 160 may also carry out processing to allow subsequent encoding of decoded transport packets (as described below). After processing the reception descriptors, the processor 160 de-allocates these descriptors by setting their status bit (s) 129-7 to indicate that the descriptor is not valid (and therefore the link control circuit). data 112 is the next device to process the descriptors), deleting or restoring selected fields of the descriptor and advancing the header pointer 124-3 to the next "storage location of descriptor 129. We now consider the case in which the decoder 115 is not provided in the adapter 110 or is not A decoder 170 resident on bus 130 is used instead. A procedure very similar to the procedure used above is carried out, however, in this scenario, the order of processing steps of the defined sequence changes in such a way. that the DMA control circuit 116 processes the descriptors (and their corresponding transport packets) after the database control circuit and before the decoder and decoder 170 processes the descriptors (and their corresponding transport packets) after the circuit DMA control 116 but before the processor 160. Thus, after assignment by the database control circuit 112 of a descriptor for a transport packet and after the establishment of the appropriate status bit (s) 129-7 to enable the completion of the next processing step, the DMA control circuit 116 processes the descriptor and packet of data that indicates. As indicated above, the DMA 116 control circuit establishes the (the) status bit (s) 129-7 to indicate that the next processing step can be carried out in the descriptor and describes the transport packet and descriptor in the guest memory 130. The decoder 170 periodically examines the descriptors in the receive queue to identify descriptors that have the status bit (s) 129-7 set (s) to indicate that the decoding processing can be carried out on descriptors and transport packets indicating (according to the order of the defined sequence of processing steps). The decoder 170 processes these transport packets (s) identified in a manner similar to that discussed above for the decoder 115. After processing the transport packets, the decoder 170 establishes one or more status bit (s) 129-7 for indicate that the next processing step (according to the order of the defined sequence of processing steps) can now be carried out in the descriptor and transport packet it indicates. The processor 160 performs the processing indicated above in response to the interrupt issued by the DMA control circuit 166, including execution of the appropriate reception PID manipulator subroutine. Preferably, the queue length of the receive queue associated with adapter 110 that interrupted processor 160 is sufficiently long relative to the processing time of decoder 170 such that processor 160 examines and processes the descriptors that decoding 170 already has fully processed. In other words, the processor 160 and the decoder 170 preferably do not attempt to access the same descriptors simultaneously. Instead, the processor 160 begins to process the descriptors at a different point in the reception queue than the decoder 170. We now consider the processing associated with the encoding. As in the case of decoding, state bit (s) 129-7 are used in the descriptor to order the processing steps performed in each descriptor and transport packet to which said descriptors point according to an order of a defined sequence of steps of processing. Unlike decoding, encoding is preferably carried out after the processor 160 has assigned transmit descriptors to the transport packets to be encoded. As such, the control word field 129-9 can be used in one of two ways. As in the case of decoding, an address can be placed towards the base of a coding map in the control word descriptor field 129-9. Preferably, however, since the encoding occurs after the processor 160 has processed the descriptors in the transmission queue, the correct control word, itself, is placed in the control word descriptor field 129-9. Consider first the coding processing where the coding is carried out in a transmission adapter 115 encoder 110. The processor 160 obtains ECM transport packets containing encrypted preference control words. These ECM transport packets are formed in a queue in a respective corresponding connection queue and are programmed to be sent at the correct time. That is, the transport packets SM are programmed for injection into the TS sent sufficiently before the transport packets they decode to allow a decoder to remove the control word before receiving the control packets it decodes. At an appropriate time after transmission of the ECM transport packets containing the control word, the processor 160 changes the control word table to cause the data to be encrypted using a new key corresponding to the transmitted control word Recently. Since transport packets are transmitted from an output adapter, the processor 160 executes transmission PID manipulator subroutines associated with the PIDs of the transport packets indicated by the descriptors in examined connection queues. For each transport packet to be encoded of this type, the transmission PID manipulator subroutine includes a process for inserting a control word information into the descriptor associated with the transport packet. The control word information may simply be the base address of a coding map to be used to identify the control word for use in the coding of a transport packet. However, the control word information may be the correct control word to be used to encode the transport packet. The processor 160 may also toggle bits in the transport packet, such as, for example, the transmission_coding_control_bit, to indicate which of the most recently transmitted control words should be used to decrypt or decode the transport packet in the decoder. The processor 160 further illustratively establishes one or more status bits 129-7 of the newly allocated transmission descriptor to indicate that the next processing step (in the order of the defined sequence of processing steps) must be performed in the transmit descriptor and the transportation package that indicates. The DMA control circuit 116 of the transmission adapter 110 periodically retrieves descriptor data from the transmission queue and transport packets indicated by such descriptors. In this way, the DMA control circuit 116 examines the descriptors in the transmission queue following the last descriptor for which the DMA control circuit 116 transferred descriptor data to the cache 114. The DMA control circuit 116 transfers only data from transmission descriptors for which the status bit (s) 129-7 is set to indicate that processing by the DMA control circuit 116 can now be performed (in the order of the defined sequence of the processing steps) . For example, the DMA control circuit 116 can examine transmission descriptors up to the identification of a certain number k = 1 of transmission descriptors that the DMA control circuit 116 can process or until the identification of a descriptor having status bits 129- 7 established to indicate that a previous processing step continues to be carried out in the transmission descriptor and transportation package indicated. After transferring to the cache 114 data of such transmit descriptors, and the transport packets to which such transmit descriptors point, the DMA control circuit 116 establishes the status bit (s) 129-7 of such transmission descriptors transferred to indicate that the next processing step (in accordance with the order of the defined sequence of processing steps) can be carried out in the transmit descriptors, and the transport packets they indicate. Then the encoder 115 periodically examines the descriptors in the cache 114 for a sequence of one or more descriptors, and transport packets indicating, to be processed. The encoder 115 processes only the descriptors to which it had access that have one or more status bits 129-7 set to indicate that the coding processing step can be carried out therein (in the order of the defined sequence of steps of processing). The encoder 115 has access to the control word information field 129-9 and uses the information there to encode each of the transport packets to be encoded. As indicated above, the control word information can be indicated in two ways. If the control word information is a base address for a coding map, the encoder 115 uses the base address and PID information of the transport packet to index the coding map. The indexed entry of the coding map indicates whether or not the transport packet should be encoded, and if so, a control word that must be used to encode the transport packet. Alternatively, to the control word information in field 129-9, it itself indicates whether or not the transport packet should be coded and if so, the control word to be used to encode the transport packet. If the transport packet of the processed descriptor is not to be encoded, the encoder 115 simply sets the appropriate status bit (s) 129-7 to indicate that the next processing step (according to the order of the sequence) defined processing steps) can now be carried out in the transmission descriptor and in the transport package that it indicates. If the transport packet of the processed descriptor is to be encoded, the encoder encodes the transport packet data first, stores the transport packet in the cache instead of the unencrypted transport packet, and then sets the bit (s) ) of appropriate state (s) 129-7. The data link control circuit 112 periodically examines the transmission descriptors in the cache 114 to transmit descriptors having one or more status bits 129-7 set to indicate that processing by the data link control circuit 112 can be done there. For these transmission descriptors, the data link control circuit 112 transmits the transport packets to which these descriptors point, approximately at the time of sending indicated there. The data link control circuit 112 then unassigns the descriptors (and sets the status bits 129-7 as invalid). Illustratively, each time the data link control circuit 112 transmits a sequence of k = 1 descriptors, the data link control circuit 112 generates a transmission interruption for reception by the processor 160. In the case where the encoder 115 is not present or is not used, the encoder 170 is used illustratively instead. The sequence of processing steps presented above changes in such a way that the encoder 170 processes each transmit descriptor and transport packet which it indicates after the processor 160 and before the DMA control circuit 116 and the DMA control circuit 116 processes each transmitter descriptor. transmission and transport packet indicating after decoder 170 but before data link control circuit 110. Optimization of bandwidth As indicated above, often a TS carrying a program has empty transport packets inserted therein. Such empty transport packets are present because the excess bandwidth typically must be allocated for each program by the program encoder. This is the reason why the amount of coded data produced for each ES produced at each moment can only be controlled in this measure. If this "excess bandwidth" is absent, encoded ES data would often exceed the amount of bandwidth that is allocated causing ES encoded data to be omitted from TS. Alternatively, an ES encoder, especially an ES video encoder, may not always have data available to send when a transport packet time segment occurs. For example, a particular image may require an unexpectedly longer time to encode than previously anticipated, thus causing a delay in the production of the encoded video ES data. Such time segments are filled with empty transport packets. Even when the presence of empty transport packets must be tolerated at the remultiplexer node 110, it is desirable to reduce the number of such empty transport packets that waste bandwidth. However, in doing so, the bit rate of each program should not vary and the end-to-end delay should remain constant for these programs. According to one embodiment, a technique is used where empty transport packets are replaced with other transport packet data to be remultiplexed, if such other transport packet data are available. This is achieved in the following way. First, we consider that the processor 160 can have several connection queues available that contain transport packet descriptors to be programmed, that is, descriptors in reception queues, Psi alone or other data queues, etc. Not yet transferred to a transmission queue. As noted above, these descriptors may indicate transport packets associated with received incoming TS or other program related streams generated by the processor 160, such as a PAT stream, a PMT stream, an EMM stream, an EC stream , a current of NIT, a current of CAT, etc. However, other types of transport packets to be programmed and descriptors 129 for them may be available as a transport packet carrying private data of "burst" or "best effort". For example, such additional transport packets may contain transactional computational data, for example, data communicated between a web browser and a web server. (The remultiplexer node 110 can be a server, a terminal or simply an intermediate node in a communication system connected to the "Internet." Such connection to the Internet can be achieved using a modem, adapter 140 0 150 etc.). Such data does not have a constant end-to-end delay requirement. On the contrary, this data can be transmitted in bursts when there is an available bandwidth. The processor 160 can cause the disposal of each empty transport packet. This can be achieved through the use by the processor 160 of a reception PID manipulation subroutine that discards all empty transport packets, this technique being used illustratively when the empty transport packets are received from another device. adapter 110, such as interface 140 or 150. Alternatively, if empty transport packets are received from adapter 110, processor 160 may provide a PID filter map to data link control circuit 112 that causes the waste of each empty transport packet. Then, according to the receiving PID manipulation subroutine, each incoming transport packet that must be sent in TS is assigned an estimated exit time based on the reception time of the transport packet (registered in its descriptor) and a challenge of internal damping within the remultiplexer node 110. In each respective connection queue containing the transport packets to be scheduled, the assigned times of departure may not be successive transport packet transmission times. (corresponding to adjacent time segments) of the sent TS. On the contrary, two successive descriptors for transport pays to be sent in the same outgoing TS can have estimated times of departure separated by one or more transmission times of transport packets (or time segments) of the remultiplexed TS sent in where the transport packages must be transmitted. Preferably, descriptors indicating transport packets carrying program data, descriptors indicating transport packets carrying PSI, ECM, EMM as well as descriptors indicating burst data are kept in mutually prepared connection queues. At the time of implementation, the connection queues each receive a service priority that depends on the type of data in the transport packets to which the descriptors formed in queue point. Preferably, the program data received from outside the remultiplexer node (for example, through a reception adapter 110 or an interface 140 or 150) are assigned the highest priority. Connection queues that store PSI, ECM or EMM streams generated by the remultiplexer node 110 may also receive the same priority. Finally, connection queues with descriptors that indicate transport packets that contain data in bursts without specific continuity, propagation delay or bit rate requirement, receive the lowest priority. In addition, unlike PSI, ECM, and EMM program data, an estimated outbound time is not assigned to the transport packet descriptor that carries burst data, nor is an estimated outbound time recorded in the transport packet descriptors that they carry data in burst. When executing transmission PID manipulator subroutines, the processor 160 transfers descriptors associated with the transport packets to be programmed from their respective connection queues to a transmission queue. In doing so, the processor 160 preferentially (i.e., examines the descriptors) to each connection queue of a given preference before serving connection queues of a minor preference. In examining the descriptors, the processor 160 determines whether or not the examined descriptors of the high priority connection queues (i.e., containing transport packet descriptors carrying program, PSI, ECM or EMM data) indicate transport packets. which must be transmitted in the following real delivery time, based on the estimated departure time assigned to such transport packages. If this is the case, the processor 260 assigns a transmission descriptor for each transport packet of this type, copies pertinent information from the connection queue descriptor in the assigned transmission queue descriptor and assigns the appropriate delivery times to each transport packet for which a transmission descriptor is assigned. As previously observed, occasionally one or more transport packets compete for the same actual output time (i.e., the same remultiplexed TS transport packet time segment sent), in that case, a sequence of transport packets are allocated. to real output times and consecutive time segments. A PCR setting for such transport packets is carried out, if necessary. At another time, when the processor 160 services the connection queues, no transport packet of the highest priority connection queues has an estimated exit time that would cause the processor 160 to allocate this transport packet to the time slot. available next and actual sending time of the remultiplexed TS sent. Usually, this creates an empty time segment of the remultiplexed TS sent. Preferably, however, in this situation the processor 160 serves the lowest priority connection queues. The processor 160 examines the lower priority connection queues (in order from the leading pointer 124-3), selectively assign a transmit descriptor to each of a sequence of one or more transport packets to which such examined descriptors point, and copy the pertinent information from the examined descriptors to the assigned transmit descriptors. The processor 160 selectively assigns one of the vacant time segments to each transport packet to which such examined descriptors point and stores the actual send time associated with the assigned time slots in the corresponding assigned transmit descriptors. Occasionally, none of the packets indexed by the descriptors in a high or low preference connection queue can be assigned to a remultiplexed TS time segment sent. This may occur because no high priority transport packet has estimated departure times that correspond to the actual time of the time segment sending and no transport packet carrying burst data is buffered while waiting for transmission in the remultiplexer node 100. Alternatively, transport packets carrying burst data are buffered, but the processor 160 chooses not to assign transmission descriptors thereof at this particular time point for reasons discussed below. In such a case, the descriptors in the transmission queue will have real transmission times corresponding to a non-continuous sequence of transport packet time slots of the remultiplexed TS sent. When the data link control circuit 112 of the transmission adapter 110 encounters a discontinuity of this type, the data link control circuit 112 transmits an empty transport packet in each vacant time slot to which no packet is allocated. transport (by virtue of the actual transmission descriptor transmission time). For example, we consider that the sending times of two successive descriptors in the transmission queue associated with the first transport packet and the second transport packet indicate that the first transport packet must be transmitted in a first transport packet time segment. and that the second transport packet must be transmitted in a sixth transport packet time segment. The data link control circuit 112 transmits the first transport packet in the first transport packet time segment. In each of second, third, fourth and fifth transport packet time segments, the data link control circuit 112 automatically transmits an empty transport packet. In the sixth transport packet time segment, the data link control circuit 112 transmits the second transport packet. Note that burst or best effort data typically does not have a hard buffer buffer. That is, most bursty or best-effort data receivers and receiver applications do not specify a maximum buffer size, data fill rate, etc. On the contrary, a transport protocol, such as a transmission control protocol (TCP), can be used where, when a reception buffer is full, the receiver simply discards data received subsequently. The receiver does not acknowledge receipt of the discarded packets and the source retransmits the packets carrying the data without acknowledgment of receipt. This effectively blocks the speed of data transmission to the receiver. While said block technique can effectively achieve the correct transmission speed of data to the receiver, it poses two problems. First, the network must support two-way communication. Only a fraction of all cable television networks and no direct broadcast satellite network supports two-way communication between the transmitter and the receiver (a missing telephone return path). In any caseWhen a two-way communication is supported, the return path of the receiver to the transmitter has a bandwidth substantially less than the forward path of the transmitter to the receiver and frequently must be shared among several receivers. Thus, an aggressive use of TCP as a blocking mechanism uses a large part of the return path that must also be used for other communications from receiver to transmitter. In addition, it is not desirable to waste bandwidth from the forward path to transmit transport packets that are discarded. Preferably, the insertion of data in burst or best effort does not cause the overflow of these buffers. Illustratively, the PID manipulator subroutine (s) can control the speed of burst data insertion to achieve an average speed, in order not to exceed a peak rate or simply to avoid overflowing a buffer memory. receiver, taking into account a certain level of receiver memory (or rather the typical) occupation and pending data there. Thus, even at times when the processor 160 has available burst or best-effort data for insertion into one or more time segments of vacant transport packets (and no other data is available for insertion there), the processor 160 may choose to insert burst data only in some vacant transport paging time segments, select the burst data insertion in time segments of alternate or spaced transport packets, or select not to insert burst data in time segments of Vacant transport packets for the purpose of regulating the transmission of data or preventing the overflow of a burst data buffer of a receiver. In addition, transport packets destined for different multiple receivers can be interspersed, regardless of whether they were generated to maintain a certain speed of data transmission in the receiver. Either way, the remultiplexer node 100 offers a simple method to optimize the bandwidth of TSs. All empty transport packages on incoming TSs are discarded. If transport packages are available, they are inserted into the time segments that would normally be assigned to the empty transport packages discarded. If transport packages are not available, gaps are left for these time segments through the process of assigning normal shipping time. If no transport packet has a send time indicating that it must be transmitted in the next available time segment of the remultiplexed TS sent, the data link control circuit 112 automatically inserts an empty transport packet in said time slot. . The benefit of said bandwidth optimization scheme is two. First, a bandwidth gain is achieved in terms of the remultiplexed TS sent. The bandwidth normally wasted in empty transport packets is now used to transmit information. Second, best effort or burst data can be sent to the TS without specifically allocating bandwidth (or by allocating much less bandwidth) for this. For example, we assume a remultiplexed TS sent that have a bandwidth of 20 Mbit / sec. Four TSs that carry a program of 5 Mbit / sec. each one must be remultiplexed and sent in the remultiplexed TS of 20Mbit / sec. However, up to 5% of the bandwidth of each of the TSs carrying the program can be assigned to empty packets, so it is possible that up to one Mbit / sec can be (nominally) available for communication of transport packages that carry Burst data or better effort, even if without any guarantee or with only a limited guarantee of end-to-end delay constancy.

Resynchronization of non-synchronized data. As previously observed, program data to be remultiplexed can be received through the asynchronous interface 140. This presents a problem since the interface 140 and the communication link to which they are fixed, are not designed to transmit data at a specific time. and they tend to introduce a variable end-to-end delay in communicated data. By comparison, an assumption can be made for program data received at the remultiplexer node 100 through a synchronous communication link (such as that connected to a receiving adapter 110) that all transport packets received therefrom will be sent without fluctuations. This is because all packets of this type have the same delay in remultiplexer mode 100 (ie the internal damping delay), or else (as a result of time segment contention in accordance with described above), the additional delay is known and the PCRs are adjusted to remove the fluctuation introduced by such additional delays. In addition, the PCRs are additionally corrected for displacement of the internal clock mechanism in relation to the system time clock of each program and for the lack of alignment between a programmed exit time PCRs and an actual exit time in relation to the limits of segment of the TS sent. However, in the case of transport packets received from the interface 140 the transport packets are received in the remultiplexer mode 100 at a variable bit rate and in non-constant fluctuating times. Thus, if the actual reception times of the transport packet are used as the basis for estimating the output of the transport packet, the fluctuation will remain. The PCRs with fluctuations not only cause the decoding and discontinuities appear in the decoder, but they cause the overflow and subflow of the buffer. This is because the bit rate of each program is carefully regulated taking into account that the data will be removed from the decoder's buffer for decoding and presentation in relation to the system time clock of the program. According to one embodiment, these problems are overcome in the following manner. The processor 160 identifies the PCRs of each program of the received TS. Using the PCRs, the processor 160 determines the rate of transport packets per piece of the transport packets of each program between pairs of PCRs. Given the transport packet speed of each sequence (interleaved) of the transport packet of each program, the processor 160 may assign estimated times of departure based on the times at which each transport packet should have been received. Illustratively, as the interface 140 receives program data, the received program data is transferred from the interface 140 to the packet buffers 122 of the guest memory 120. specifically, the interface 140 stores program data received in some form from a reception queue. Preferably, the received program data is found in transport packets. The interface 140 periodically interrupts the processor 160 when it receives data. The interface 140 may interrupt the processor 160 each time it receives a quantity of data or may interrupt the processor 160 after receiving a certain amount of data. As in the case of the adapter 110, a PID manipulator subroutine pointer table 402 is specially created for the interface 140. The subroutines indicated by the pointers can be similar in many ways to the subroutines indicated by the pointers in the table. of reception PID manipulator subroutine pointers associated with a reception adapter 110. However, the subroutines are different in at least the following ways. First, an asynchronous interface 140 can not assign descriptors having the format illustrated in Figure 2 to received program data and can not receive program data in transport packets. For example, the program data may be PES packet data or PS packet data. In these cases, the subroutines executed by the processor 160 for PIDs of retained transport packets illustratively include a process for inserting program data into transport packets. In addition, a process may be provided to assign a receipt descriptor of a queue assigned to adapter 140 to each received transport packet. The processor 160 stores in the pointer field 129-4 of each assigned descriptor a pointer to the storage location of the corresponding transport packet. Illustratively, the actual reception time field 129-5 is initially left blank. Each transport packet that contains a PCR also includes the following process. The first time a transport packet carrying a PCR is received in a program, the processor 160 obtains a time stamp from the reference clock generator 113 of any adapter 110 (or, alternatively, another reference clock generator 113). synchronously locked with the reference clock generators 113 of the adapters 110). In accordance with what is described below, the reference clocks 113 are locked synchronously. The obtained time print is assigned to the first transport packet carrying PCR received from a program as the reception time of this transport packet. Note that other transport packets to be remultiplexed may have been received before this first transport packet carrying received PCR. The known internal buffer delay in the remultiplexer node 100 can be added to the reception time printout to generate an estimated output time that is allocated to the transport packet (which contains the first received PCR of a particular program). After receipt of the second successive transport packet carrying a PCR for a particular program, the processor 160 can estimate the transfer rate of transport packets between PCRs of this received program through the asynchronous interface 140. This is achieved by the following way The processor 160 forms the difference between the two successive PCRs of the program. The processor then divides this difference by a number of transport packets of the same program between the transport packet containing the first PCR and the transport packet containing the second PCR of the program. This produces the transport packet transfer rate for the program. The processor 160 estimates the output time of each transport packet of a program between the PCRs of this program by multiplying the transfer rate of transport packets for the program with the displacement of each transport packet of this type from of the transport packet containing the first PCR. The offset is determined by subtracting the transport packet tail position from the transport packet carrying the first PCR from the transport packet tail position for which an estimated exit time is being calculated. (Note that the queue position of a transport packet is relative to all transport packets received from all received streams. Processor 160 then adds the estimated exit time allocated to the transport packet containing the first PCR to the product produced in this way, the processor 160 stores in an illustrative manner the estimated time of departure of each transport packet of this type in case 129-10 of the descriptor that indicates it.After assigning an estimated timeout impression to the packets of transport of a program, processor 160 can discard transport packets (according to a user specification) that will not be sent in a TS. The above process is then repeated continuously for each successive pair of PCRs of each program carried in a TS. The data of the descriptors with the estimated times of output can then be transferred to the appropriate transmission queue (s) in the course of execution by the transmission PID manipulator subroutine processor 160. Note also that initially certain transport packets can be received for a program before receiving the first PCR of this program. For these transport packets only, the transport packet transfer rate is estimated as the transport packet speed between the first and second PCR of this program (even though these packets are not between the first and second PCR). The estimated time of departure is determined in accordance with the above. As in the case of PCRs received from a synchronous interface such as an adapter 110, the PCRs received through the asynchronous interface 140 are corrected to take into account the displacement between each program clock and the reference local clocks. employees to assign impressions of estimated time of receipt and to send transport packages. Unlike the transport packets received from an adapter 110, the transport packets received from the interface 140 have no actual received time stamp impressions. As such, there is no reference clock associated with each transport packet from which the displacement can be accurately measured. On the contrary, the processor 160 uses a measurement of the length of the transmission queue or the current delay in the remultiplexer mode 100 to estimate the displacement. Ideally, the length of the transmission queue should not vary from a known predetermined delay at the remultiplexer node 100. Any variation in the length of the transmission queue is the indication of a displacement of the generator (s). ) of reference clock 113 of the adapter (s) 110 in relation to program clocks of the programs. As such, the processor 160 adjusts a displacement measurement up or down according to the differences between the current transmission queue length and the ideal, expected transmission queue length. For example, each time a transmission descriptor is assigned to a transport packet, the processor 160 measures the current transmission queue length and the ideal transmission queue length subtraction at the remultiplexer 100 node. The difference is displacement. The displacement calculated in this way is used to adjust the PCRs and the estimated times of departure of the transport packets carrying such PCRs. That is, the displacement calculated in this way is subtracted from the PCR of a transport packet received through the asynchronous interface placed in the time segment after the time segment corresponding to the estimated delivery time of the transport packet. In the same way, the displacement can be subtracted from the estimated time of departure of the transport packet carried by PCR before the assignment of the real time of sending. Note that the estimated offset is used only to transport packets received from the asynchronous interface 140 and no other transport packets received through a synchronous interface such as adapter 110. Consider now the problem of competition. When two (or more) received transport packets compete for their allocation in the same transport packet time segment (and actual send time) of the remultiplexed TS, sent, a transport packet is assigned to the time segment and the another is assigned to the next time segment. If the other transport package contains a PCR, the PCR is adjusted by the number of displacement time segments of its ideal time segment to reflect the assignment to a subsequent time segment. Auxiliary output synchronization. As indicated above, interface 140 does not receive transport packets at any particular time. In the same way, an interface 140 does not transmit transport packets at any particular time. However, although the interface 140, and the communication link to which it is attached, do not provide a constant end-to-end delay, it is desirable to reduce the end-to-end delay variation to the greatest extent possible. The remultiplexer mode 100 offers a way to minimize such variations.

According to one embodiment, the processor 160 allocates a transmitter descriptor of a transmission queue assigned to the interface 140 to each transport packet to be sent through the interface 140. This can be achieved by employing the appropriate set of transmission PID manipulator subroutine. to transmit queues assigned to the output port of the interface 140. The processor 160 further assigns an adapter 110 to handle the data output from this interface 140. Even though the transmission queue is technically "assigned2 to the interface 140, the DMA control circuit 116 of the adapter 110 assigned to handle the output of the interface 140 actually obtains control of the descriptor queue descriptors assigned to the interface 140. The data link control circuit 112 has access to these descriptors , as described below, which can be maintained in cache 114. Thus, the set of PID manipulator subroutines of transmission assign Attached to this queue, and executed by the processor 160, it is in fact activated by an interrupt generated by the data link control circuit 112 which examines the queue. As indicated above, in response to the interruption, the processor 160 examines the descriptors to be programmed, that is, in connection queues, selects one or several descriptors of these connection queues to be sent from the output port of the interface 140 and allocates transmission descriptors for the selected descriptors of the connection queues at the end of the transmission queue associated with the output port of the interface 140. Unlike the transport packet transmission described above, the processor 160 may also 'group the transport packets associated with lps selected descriptors of the connection queues and physically arrange them in fact in a queue type buffer, if such buffering is necessary for the interface 140. As indicated above, the DMA control circuit 116 obtains control of a sequence of one or more descriptors, associated with the output port of the following 140 interface The last descriptor from which the DMA 116 control circuit gained control (note that it is irrelevant whether or not the transport packets corresponding to the descriptors are retrieved. Since the data link control circuit 112 controls the output of the transport packets at the interface 114, transport packets are not sent from the output port connected to this data link interface 112. Alternatively, the circuit The data link control 112 can operate exactly as described above, thus producing a mirror copy of the TS sent. In such a case, a second copy of each transport packet, accessible by the adapter 110, must also be provided). As mentioned above, the data link control circuit 112 recovers each descriptor of the memory beam and determines, based on the indicated sending time recorded in field 129-5, when the corresponding transport packet must be transmitted with relation to the time indicated by the reference clock generator 113. approximately when the reference clock generator time 113 is equal to the send time, the data link control circuit 112 generates an interrupt to the processor 160 indicating that the packet of data must be transmitted now. This can be the same interruption as that generated by the data link control circuit 112 when transmitting k = l transport packet. However, the interruption is preferably generated every K = l transport packets. In response, processor 160 examines the appropriate table of pointers for transmission PID manipulator subroutines and executes the correct transmission PID manipulator subroutine. When executing the transmission PID manipulator subroutine, the processor 160 sends a command or interrupt to cause interface 140 to transmit a transport packet. This causes the transmission of the next transport packet from the output port of the interface 140 approximately when the current time of the reference clock generator 113 corresponds to the sending time written in the descriptor corresponding to the transport packet. Note that some interrupt latency and bus will occur between the data link control circuit 112 that issues the interrupt and the interface 140 that the transport packet sends. further, a certain latency may occur in the communication link in which the interface 140 is fixed (if it is occupied, due to a collision, etc.). To some extent, the average amount of said latency can be included through the appropriate selection of times for sending the transport packets by the processor 160. However, the output of the transport packets can be very close to the time The processor 160 also transfers one or more descriptors to the transmission queue assigned to the output port of the interface 140 in accordance with what is described above. Reference synchronization lock between adapters A particular problem in any synchronization system that employs several clock generators is that the time or count of each generator is not exactly the same as that of other clock generators. The count of each clock generator is subject to displacements (for example, as a result of manufacturing tolerance, temperature variations, energy, etc.). Said concern is also present in the environment 10. Each remultiplexer node 100, data injector 50, data extractor 60, controller 20, etc., can have a reference clock generator, such as the clock generator for example. reference 113 of the adapter (s) 110 in the remultiplexer node 100. It is desirable to block the reference clock generators of each node 50, 70 or 100 in the same TS signal flow path in such a way that have the same time. In a broadcast environment, it is useful to synchronize all the equipment that generates, edits or transmits program information. In analog broadcasting, this can be achieved by using a burst generator or a SMPTE time code generator. Said synchronization allows the splicing without sutures of video feeds in real time and reduces the noise associated with the asynchronous coupling of video feeds. In the remultiplexer node 100, the need for synchronization is even more important. This is because the received transport packets are programmed to be sent based on a reference clock and actually recovered for shipment based on a second reference clock. It is considered that any latency incurred by the transport packets in the remultiplexer node 100 is identical. However, this assumption is valid only if there is an insignificant shift between the reference clock in accordance with which the packet output and the reference clock according to which the transport packets are actually sent is estimated. According to one embodiment, various techniques are provided for blocking, ie, synchronizing, reference clock generators 113. In each technique, the time of each "dependent" reference clock generator is periodically adjusted relative to a generator set. "master" reference clock. According to a first technique, a reference clock generator 113 of an adapter is designed as a master reference clock generator. Each other reference clock generator 113 of each other adapter 110 is considered as a dependent reference clock generator. The processor 160 periodically obtains the current system time of each reference clock generator 113, including the master reference clock generator and the dependent reference clock generators. Illustratively, this is achieved by employing a process that "sleeps" that is, is inactive for a particular period of time, wakes up and causes the processor 160 to obtain the current time of each reference clock generator 113. The processor 160 compares the time current of each dependent reference clock generator 113 with the current time of the master reference clock generator 113. Based on these compositions, the processor 160 adjusts each dependent reference clock generator 113 to synchronize them relative to the master reference clock generator 113. The adjustment can be achieved by simply reloading the reference clock generators 113, adding a time value set to time of the reference clock generator system 113 or (filtering y) by accelerating or lowering the speed of the pulses of the voltage controlled oscillator that supplies the clock pulses to the counter of the reference clock generator 113. This last form of adjustment is Analogous to a Loop Loop Feedback adjustment in phase described in the MPEG-2 system specification. We consider now in the case in which the master reference clock generator and the dependent reference clock generator are not located in the same node, but are connected to each other through a communication link. For example, the master reference clock generator may be in a first remultiplexer node 100 and the dependent reference clock generator may be in a second remultiplexer node 100, where the first remultiplexer node and the second remultiplexer node are connected to each other through a communication link extending between respective adapters 110 of the first remultiplexer node 100 and second remultiplexer node 100. Periodically, in response to a timer process, the processor 160 sends a command to obtain the time current of the master reference clock generator 113. The adapter 110 responds by providing the current time to the processor 160. The processor 160 then transmits the current time to each dependent reference clock through the communication link. The dependent reference clocks are then adjusted, for example as described above. It will be noted that any time source or time server can be used as a master reference clock generator. The time of this master reference clock generator is transmitted through the dedicated communication link with a constant end-to-end delay to the other nodes containing a dependent reference clock. If two or more nodes 20, 40, 50, 60 or 100 of a remultiplexer 30 are separated by a large geographical distance, it may not be desirable to synchronize the reference clock generators of each node to the reference clock generator of another node. This is due to the fact that any signal transmitted on a communication link is subject to a certain finite propagation delay. Said delay causes a latency in the transmission of transport packets, especially transport packets carrying synchronization time impressions. On the contrary, it may be desirable to employ a reference clock source more equally distant from each node of the remultiplexer 30. As is known, the North American government maintains reference clock generators both terrestrial and satellite. These sources reliably transmit time in well-known carrier signals. Each node, such as the remultiplexer node 100, may have a receiver, such as a GPS receiver 180 that can receive the reference clock issued. Periodically, the processor 160 (or another circuit) in each node 20, 40, 50, 60 or 100 obtains the reference clock of the receiver 180. The processor 160 can transfer the time obtained to the adapter 100 to charge it in the clock generator reference 113. Preferably, however, the processor 160 sends a command to the adapter 100 to obtain the current time of the reference clock generator 113. The processor 160 then sends a command to adjust, for example, to accelerate or decrease the voltage of the voltage controlled oscillator of the reference clock generator 113 based on the disparity between the time obtained from the receiver 180 and the actual time of the reference clock generator 113. Network remultiplexing Given the operation described above, the various functions of remultiplexing can be distributed in a network. For example, multiple remultiplexer nodes 100 may be interconnected to each other by several communication links, adapter 110 and interfaces 140 and 150. Each of these remultiplexer nodes 100 may be controlled by controller 20 (FIG. 1) to act in concert as a single remultiplexer 30. Said remultiplexer distributed in network 30 may be desirable for comfort or flexibility. For example, a remultiplexer node 100 may be connected to several file servers or storage devices 40 (Figure 1). A second remultiplexer node 100 may be connected to several other input sources, such as cameras, or demodulators / receivers. Other remultiplexer nodes 100 may be connected to one or more transmitters / modulators or recorders. Alternatively, the remultiplexer nodes 100 may be connected to provide redundant functionality and therefore fault tolerance in the case of the failure of a remultiplexer node 100 or if it is purposely removed from service. Consider a first network remultiplexer 30 'illustrated in Figure 3. In this scenario, multiple remultiplexer nodes 100', 100"and 100 '" are connected to each other through an asynchronous network, such as an Ethernet TX network with BASE 100. Each of the first two remultiplexer nodes 100 ', 100"receives four TSs, TS-10-TS13 or TS14-TS17, and produces a single remultiplexed TS TS18 or TS19. The third remultiplexer 100' "receives TSs TS18 and TS19, and produces TS remultiplexed output TS20. In the example illustrated in Figure 3, the remultiplexer node 100 'receives TSs transmitted in real time, TS10-TS13 from a demodulator / receiver through its adapter 110 (Figure 2). On the other hand, the remultiplexer 100"receives previously stored TSs, TS14-TS17, from a storage device through a synchronous interface 150 (Figure 2). Each of the remultiplexer nodes 100 'and 100" transmits its The remultiplexed TS sent respectively, ie TS18 or TS19, to the remultiplexer node 100 '"through an asynchronous interface 140 (100 BASE-TX Ethernet) (FIG. 2) to an asynchronous interface 140 (100 BASE-TX Ethernet) (FIG. 2) of the remultiplexer node 100 '". Advantageously, each of the remultiplexer nodes 100 'and 100"employs the auxiliary output synchronization technique described above to minimize variations in the end-to-end delays caused by said communication, however, the remultiplexer node 100 '"employs the unsynchronized data technique resynchronization described above to estimate the bit rate of each program in TS18 and TS19 and to remove fluctuations in TS18 and TS19. Optionally, a burst device 200 may also be included in at least one communication link of the system 30 '. For example, the communication medium can be shared with other terminals that carry out usual data processing, such as in a LAN. However, burst devices 200 may also be provided for purposes of injecting and / or extracting data in the TSs, for example, the TS 20. For example, the burst device 200 may be a server providing Internet access, a server of web, a web terminal, etc. Obviously, it is simply an example of a distributed remultiplexer network. Other configurations are possible. For example, the communication protocol of the network where the nodes are connected can be ATM, DS3, etc. Two important properties of network distributed remultiplexer 30 must be observed: First, in the particular network illustrated, any input port can receive data, such as burst data or TS data, from any input port. That is to say, the remultiplexer node 100 'can receive data from the remultiplexer nodes 100"or 100'" or from the burst device 200, the remultiplexer node 100"can receive data from the remultiplexer nodes 100 'or 100'" or In addition to the burst device 200, the remultiplexer node 100 '"can receive data from any of the remultiplexer nodes 100' or 100" or from the burst device 200, and the burst device 200 can receive data from any of the remultiplexer nodes 100 ', 100"or 100'". Second, a remultiplexer node that performs data extraction and data scrapping, i.e., the remultiplexer node 100 '"may receive data from more than one source, namely, the remultiplexer nodes 100' or 100" or well the burst device 200, in the same communication link. As a consequence of these two properties, the "signal flow pattern" of the transport packets from source nodes to destination nodes within the remultiplexer is independent of the network topology to which the nodes are connected. In other words, the node and the communication link path traversed by the transport packets in the distributed remultiplexer 30 'does not depend on the precise physical connection of the nodes by the communication links. Thus, a very general network topology can be used - remultiplexer nodes 100 can be connected in a relatively arbitrary topology (bus, ring, chain, tree, star, etc.) and yet can remultiplex TSs to achieve virtually any type of pattern of signal flow from node to node. For example, nodes 100 ', 100", 100'" and 200 are connected in a bus topology. However, any of the following signal flow patterns for transmitted data (eg, TSs) can achieve: from node 100 'to node 100"and then to node 100'"; of each of the nodes 100 'and 100"in parallel to the node 200, of the nodes 200 and 100', in parallel, to the node 100" and after the node 100"to the node 100 '", etc. In this type of transmission, time division multiplexing may be necessary to intersperse signal flows between different sets of communication nodes. For example, in the signal flow illustrated in Figure 3, TS18 and TS19 are multiplexed by time division in the shared communication medium. The above discussion is intended to illustrate the invention. Those with some experience in the field can invent many alternative modalities without departing from the spirit or scope of the following claims.

Claims (14)

1. CLAIMS 1. A method for optimizing the bandwidth of a transport stream comprising the steps of: (a) receiving a transport stream at a predetermined bit rate, said transport stream includes transport packets carrying data program variables and one or more empty transport packets (s), each of said empty transport packets is inserted into a time segment of said received transport stream to maintain said predetermined bit rate of said transport transport stream when none of the transport packets carrying compressed program data is available for insertion into said transport stream received in said transport packet time segment, and (b) selectively replacing one or more of said packets of transport packets. empty transport with another transport package that carries data to remultiplex.
2. 2. The method according to claim 1 wherein said other transport packet carrying data to remultiplexing contains program specific information.
3. 3. The method according to claim 1 wherein said other transport packet containing data to be remultiplexed contains transaction data that has no requirement for bit rate or transmission latency to present information continuously. .
4. The method according to claim 1 further comprising the steps of: (c) extracting selected packets between said transport packets from said received transport stream and discarding unselected transport packets, empty transport packets being discarded, (d) ) store said selected transport packages, (e) storing at least one other transport packet carrying data, (f) scheduling each of said transport packets stored for shipment in an outbound transport stream, and (g) sending each of said stored transport packets. in a segment of time corresponding to said program. .
5. The method according to claim 4 further comprising the steps of: (h) in each time segment of said output transport stream for which a corresponding transport packet of said stored transport packets is programmed, sending said packet of corresponding stored transport for said time segment, and (i) if no transport package is programmed to be sent in one of said time segments, send an empty transport packet, where said empty transport packets of said current of outgoing transport occupy less bandwidth of said outgoing transport stream than what said empty transport packets occupy in each transport stream received in step (a).
6. The method according to claim 3 wherein said step (b) further comprises the selective allocation of transport packets having data to time segments of said output transport stream in order to regulate a bit rate of transmitting said transport packets that carry data to a receiver buffer. .
7. A remultiplexer for optimizing the bandwidth of a transport stream, comprising: a first interface for receiving a transport stream at a predetermined bit rate, said transport stream includes transport packets carrying compressed program data of variably and one or more empty transport packets, each of said empty transport packets is inserted into a time segment of said received transport stream to maintain said predetermined bit rate of said transport stream when none of these transport packets carrying compressed program data is available for insertion into said transport stream received in said transport packet time segment, and a processor for selectively replacing one or more of said empty transport packets with another transport packet carrying data to remultiplex.
8. The remultiplexer according to claim 7 wherein said other transport packet carrying data to remultiplexing contains program specific information.
9. 9. The remultiplexer according to claim 7 wherein said other transport packet carrying data to remultiplexing contains transaction data that does not have a bit rate requirement or transmission latency to present the information continuously.
10. The remultiplexer according to claim 7 wherein said first interface and said processor extract selected packets of said transport packets from said received transport stream and discard each unselected transport packet, each of said empty transport packets being discarded Said remultiplexer further comprises: a memory in which said first interface and said processor store said selected transport packets, and wherein said processor stores at least another transport packet carrying data, said processor programs each of said transport packets stored for sending in an outgoing transport stream, and a second interface for sending each of said transport packets stored in a time segment corresponding to said program. .
11. The remultiplexer according to claim 10 wherein, in each time segment of said transport stream sent for which a corresponding packet of said stored transport packets is programmed, said second interface sends said corresponding stored transport packet programmed for said segment. of time and, if a transport packet is not programmed in one of said time segments, said second interface sends an empty transport packet, said empty transport packets of said output transport current occupy less bandwidth of said current of transport sent from what said empty transport packages occupy in each received transport stream.
12. 12. The remultiplexer according to claim 9 wherein said processor selectively allocates transport packets carrying data to time segments of said transport stream sent in order to regulate a transfer bit rate of said transport packets carrying data to a receiver buffer.
13. 13. A transport stream with optimization of the bandwidth, produced by the steps of: (a) receiving a transport stream with a predetermined bit rate, said transport stream includes transport packets carrying compressed program data variably and one or more empty transport packets, each of said empty transport packets is inserted into a time segment of said received transport stream to maintain said predetermined bit rate of said transport stream when none of said transport packets carrying compressed program data are available for insertion into said transport stream received in said transport packet time segment, and (b) selectively replacing one or more of said empty transport packets with another packet of transport packets. transport that carries data to remultiplex.
14. 14. The bit stream that optimizes the bandwidth according to claim 13 produced by the additional steps of: (c) extracting selected packets of said transport packets from said received transport stream and discarding the non-selected transport packets, discarding the empty transport packages, (d) store said selected transport packages, (e) storing at least one other transport packet carrying data, (f) scheduling each of said transport packets stored for shipment in an outbound transport stream, and (g) sending each of said stored transport packets. in a segment of time corresponding to said program. 5. The transport stream with optimized bandwidth of claim 14, produced by the additional steps of: (h) in each time segment of said output transport stream for which a corresponding packet of said stored transport packets is programmed, sending said corresponding stored transport packet programmed for said segment of transport. time, and (i) if no transport packet is programmed to be sent in one of said time segments, send an empty transport packet, where said empty transport packets of said transport stream take up less bandwidth than said output transport stream occupied by said empty transport packets in each transport stream received in step (a). The transport stream that optimizes the bandwidth of claim 13 wherein said step (b) further comprises the step of selectively allocating transport packets that carry data to time segments of said transport stream sent in order to regulate a transmission bit rate of said transport packets carrying data to a receiver buffer. 7. A method for remultiplexing one or more transport streams carrying a program, each program comprising one or more elementary streams, each transport stream comprising transport packets, including transport packets carrying elementary current data for one or more programs , said method comprises the steps of: (a) selectively extracting a particular transport packet from said transport packets from each of these transport streams carrying program according to an initial user specification for remultiplexed transport stream content, (b) reassembling said transport packets selected from said extracted transport packets, and, program-specific information containing transport packets, if any, in a remultiplexed transport stream, sent in accordance with said initial user specification for content of transport stream remultip lexada, (c) sending said reassembled remultiplexed transport stream as a stream of continuous bits, (d) while performing steps (a), (b) and (c) dynamically receiving one or more new user specifications for remultiplexed transport stream content specifying one or more of the following: (I) different transport packets to be extracted in said step (a), (II) different transport packets to be reassembled in said step (b), and (e) ) in response to receiving said new user specification or said new user specifications, dynamically suspending the removal or reassembly of transport packets according to said initial user specification and dynamically starting the removal or reassembly of transport packets according to said user specification. new user specification without introducing discontinuity in said remultiplexed transport stream, sent. The method according to claim 17 further comprising the step of: (f) responding to a new user specification to reassemble different transport packets in step (b) by generating a substitute program-specific information that refers to said transport packets other than said new user specification. The method according to claim 17 further comprising: (f) receiving said initial user specification and each new user specification, (g) determining a total bit rate request requirement for said reassembled remultiplexed transport stream in accordance with each of said user specifications received, (h) carrying out steps (a), (b) and (e) only if said determined bit rate request requirement is equal to or less than a bit rate of said re-multiplexed transport stream, sent. The method according to claim 17 further comprising the steps of: (f) continuously identifying available streams for assembly in said remultiplexed transport stream sent, and (g) prompting a user for a new user specification that it specifies a selection of said identified streams available as said content for said remultiplexed transport stream. The method according to claim 17 wherein said new user specification specifies a new topography of packet identifiers of one or more transport packets reassembled in said step (b), said step (e) comprises the topography of identifiers of packages of said transport package or said various transport packages according to said new topography. 2. The method according to claim 17 wherein said new user specification specifies the coding of one or more particular elementary streams, said method further comprising the steps of: (a) encoding said transport packets in said specified elementary streams employing words control, (b) provide transport packets containing said control words for reassembly in said remultiplexed transport stream, and (c) generate transport packets containing program-specific information that identifies which transport packets contain said control words and to which elementary streams correspond said transport packages that carry control words. 3. A method for remultiplexing transport packets in one or more transport streams entered into an outgoing transport stream, at least one of said transport streams entered contains one or more programs and program definitions, each of said programs comprises one or more elementary streams, and each said at least one input stream entered includes program definitions that identify which transport packets contain elementary current data for each elementary stream contained in said input stream and which of said elementary streams constitutes each program contained in said transport stream entered, said method comprises the steps of: (a) generating a user specification indicating one or several programs of said transport streams to be sent in said transport stream sent, (b) continuously capture those definitions of pr ogram (c) continuously determining from said captured program definitions which elementary streams constitute each program, and (d) sending in said transport stream sent each transport packet containing elementary current data of each elementary stream determined in said step ( c) to constitute each program indicated to be sent in said user specification without introducing a discontinuity in said transport stream sent. 4. A remultiplexer for remultiplexing one or more transport streams carrying a program, each program comprising one or more elementary streams, each transport stream comprising transport packets, including transport packets carrying elementary stream data for one or more programs, said method comprises: a first interface for selectively extracting only particular packets of said transport packets from each of said transport streams carrying program according to an initial user specification for remultiplexed transport stream content, a second interface for reassembling said packets selected from said transport packages extracted and, transport packets containing program-specific information, optionally, in a remultiplexed transport stream sent, according to said initial user specification for remultiplexed transport stream content, and for sending said re-multiplexed transport stream reassembled as a stream of continuous bits , and a processor for dynamically receiving one or more new user specifications to a remultiplexed transport stream content that specifies one or more of the following: (I) different transport packets to be extracted through said first interface, (II) different transport packets to be reassembled through said second interface, while said first interface and said second interface extract transport packets and reassemble and produce said remultiplexed transport stream and, in response to receipt of said new user specification or said new specifications user ions, to cause said first interface and said second interface to dynamically suspend the extraction or reassembly of transport packets according to said initial user specification and dynamically begin to extract or reassemble transport packets in accordance with said new user specification, without introduce discontinuity in said remultiplexed transport stream sent. 25. The remultiplexer according to claim 24 wherein said processor responds to a new user specification for reassembling different transport packets by generating information specific to a substitute program that references said transport packets other than said new user specification, for reassembly through said second interface. 26. The remultiplexer according to claim 24 further comprising: a controller for receiving said initial user specification and each new user specification, determining a total bit rate requirement for said re-multiplexed transport stream reassembled in accordance with each specification received user, and allow said first interface and said second interface to extract and reassemble in accordance with said new user interfaces only if said determined bit rate requirement is equal to or less than a bit rate of said remultiplexed transport stream sent . . The remultiplexer according to claim 24 wherein said processor continuously identifies available streams for assembly in said output remultiplexed transport stream, said remultiplexer further comprising: a driver for prompting a user to employ a new user specification specifying a selection of said available streams identified as said content for said remultiplexed transport stream. . The remultiplexer according to claim 24 wherein said new user specification specifies a new topography of packet identifiers of one or more transport packets reassembled by said second interface, said processor, topography identifiers of said transport packets or said transport packets of said transport packets. conformity with said new topography. . The remultiplexer according to claim 24 wherein said new user specification specifies the coding of one or more particular elementary streams, said additional remultiplexer further comprising: an encoder for encoding said transport packets of said specified elementary streams using control words, wherein said processor obtains transport packets containing said control words for reassembly in said re-multiplexed transport stream and transport packets containing program-specific information that identifies which transport packets contain said control words and to which elementary streams those control words correspond . . The remultiplexer for remultiplexing transport packets of one or more transport streams entered into an output transport stream, at least one of said input stream contains one or more programs and program definitions, each of said programs comprises one or several elementary streams, and each of said at least one input stream input includes program definitions that identify which transport packets of said input stream contains elementary current data for each elementary stream contained in said input stream input and what elementary streams constitute each program contained in said elementary stream, said remultiplexer comprises: a controller for generating a specification indicating one or several programs of said input streams to be sent in said output transport stream, a first adapter to capture continuously said program definitions, a processor for continuously determining from said captured program definitions which elementary streams constitute each program, and a second adapter for sending in said output transport stream each transport packet containing elementary current data of each elementary stream determined to constitute each program indicated for delivery in said user specification without introducing a discontinuity in said transport stream sent. 31. A remultiplexed transport stream sent, remultiplexed from one or more transport streams carrying program, each program comprises one or more elementary streams, each transport stream includes transport packets, including transport packets carrying current data elementary for one or several programs, said remultiplexed transport stream sent is produced through the steps of: (a) selectively extracting only particular packets of said transport packets from each of said transport streams carrying conformance program with an initial user specification for remultiplexed transport stream content, (b) reassembling said selected packets of said extracted transport packets, and, transport packets containing program-specific information, optionally, into a remultiplexed transport stream sent, of conformity ad with said initial user specification for remultiplexed transport stream content, (c) sending said re-multiplexed transport stream reassembled in the form of a stream of continuous bits, (d) while carrying out said steps (a), (b) and (c), dynamically receiving one or more new user specifications for remultiplexed transport stream content specifying one or more of the following: (I) different transport paysages to be extracted in said step (a), (II) different transport packages to be reassembled in said step (b), and (e) in response to the reception of said new user specification or said new user specifications , dynamically suspending the removal or reassembly of transport packets in accordance with said initial user specification and dynamically starting the removal or reassembly of transport packets in accordance with said new user specification without introducing discontinuity in said remultiplexed transport stream sent. 2. A transport stream sent remultiplexed from one or more transport streams entered, at least one of said transport streams entered contains one or more programs and program definitions, each of said programs comprises one or more elementary streams, and each of said at least one input stream includes program definitions that identify which transport packets contain elementary current data for each elementary stream contained in said input stream and which of said elementary streams constitute each program contained in said stream. transport stream entered, said output transport current is produced through the steps of: (a) generating a user specification that indicates one or several programs of said transport streams entered to be sent in said output transport stream, ( b) continuously capture said d program efficiencies, (c) continuously determining from said captured program definitions which elementary streams constitute each program, and (d) sending in said output transport stream each transport packet containing elementary current data from each elementary stream determined in said step (c) to constitute each program indicated to be sent in said user specification without introducing discontinuity in said transport stream sent. 3. A method for remultiplexing one or several streams of bits containing compressed program data in an asynchronous communication network comprising several nodes interconnected by one or more communication links, comprising the steps of: (a) receiving, starting of one of said communication links in a destination node of said asynchronous communication network, a first bit stream containing data of one or more programs, said first bit stream having one or more predetermined bit rates for portions of the same, (b) choose at least part of said first bit stream received for transmission, and (c) program the transmission of said selected part of said first bit stream in order to send said chosen part of said first bit stream in a transport stream at a speed that depends on said predetermined speed of said selected part of said pr imera bit stream. 34. At multiple nodes of a communication network, a method for remultiplexing one or more portions of bit streams into one or more transport streams containing compressed video program data, comprising the steps of: (a) enabling the communication between several nodes connected to a communication means shared by one or several respective communication links, (b) selecting a first set of one or more nodes of this type to transmit one or more streams of bits in said shared communication medium, (c) selecting a second set of one or more of said nodes to receive said transmitted bit streams from said shared communication means, to select portions of said transmitted bitstreams and to transmit one or more remultiplexed transport streams as a bit stream containing said selected portions, each of said remultiplexed transport streams transmitted as a bit stream is different from said streams of bits received from said streams of transmitted bits, and (d) causing said selected nodes to communicate said bit streams through said shared communication means according to one of several different signal flow patterns, including at least one flow pattern of signals different from a topological connection of said nodes to said shared communication medium. 5. The method according to claim 34 wherein at least one node can receive streams of bits from each of several other nodes through a single communication link of said respective communication links, said method further comprising the step of selecting a subset of said various other nodes and receiving bit streams in said at least one node of only said selected subset of nodes. The method according to claim 34 wherein at least one node receives bit streams from several others of said nodes through a single communication link of said respective communication links. 7. A network distributed remultiplexer for remultiplexing one or more streams of bits containing compressed program data, comprising: one or several communication links, and a plurality of nodes, interconnected by said communication link or said communication links in a communication network, said plurality of nodes includes a destination node that receives a first bit stream containing data of one or more programs through one or said communication links, said first bit stream having one or several speeds of predetermined bits for portions thereof, said destination node comprises: a processor for choosing at least a portion of said first bit stream received for transmission, and for scheduling the transmission of said chosen part of said first bit stream with the object of sending said chosen part of said first bit stream in a transport stream at a rate that depends on said predetermined speed of said selected part of said first bit stream. . A remultiplexer distributed in a network for remultiplexing a portion or several portions of bit streams into one or more transport streams containing compressed video program data, comprising: a shared communication medium comprising one or more communication links, one plurality of nodes, each of said nodes is connected to said shared communication means through one or several respective communication links of said communication links, said plurality of nodes includes: a first set of one or several of said nodes to transmit one or more streams of bits in said shared communication means, a second set of one or more of said nodes to receive said bit streams transmitted from said shared communication means, to select portions of said streams of transmitted bits and to transmit one or more remultiplexed transport streams As a stream of bits containing said selected portions, each of said remultiplexed transport streams transmitted as a bitstream is different from said streams received from said streams of transmitted bits, and a controller node for selecting said first set and said second set of nodes and to cause said selected nodes to communicate said bit streams through said shared communication means in accordance with one of several different signal stream patterns, including at least one signal flow pattern different from a topological connection of said nodes with said shared communication medium. . The network distributed remultiplexer according to claim 38, wherein said plurality of nodes further comprises at least one node that can receive bit streams from each of several other nodes of said nodes through a single communication link of said links. communication receiver, said controller node selects a subset of said several other nodes and said at least one node receiving bitstreams from only said selected subset of nodes.