CN104467759A - Differential signal peak-to-peak value detection circuit - Google Patents

Abstract

The invention discloses a differential signal peak-to-peak value detection circuit. According to the differential signal peak-to-peak value detection circuit, a common mode level Vcm of an input signal is extracted through a resistor, the peak-to-peak value detection voltage Vpp is generated through operational amplifier buffering, the threshold voltage Vpp is compared with the differential input voltage VP and VN, then a capacitor C0 is charged or discharged through a common-source amplifier to generate the voltage Vc value, and finally the peak-to-peak value detection result Z is generated.

Description

A kind of differential signal peak-to-peak value testing circuit

Technical field

The present invention relates generally to the design field of voltage detecting circuit, refers in particular to a kind of differential signal peak-to-peak value testing circuit.

Background technology

In the design of current analog CMOS integrated circuit, particularly in radio frequency signal receiver, owing to needing to quantize faint radiofrequency signal, usually digital signal is quantized into high-precision adc, because the excursion of radiofrequency signal is usually larger, in order to radio-frequency front-end signal meets ADC dynamic range, usually a programmable gain amplifier can all be increased in the front end of ADC, its objective is and control its gain according to the amplitude of radiofrequency signal, the input of ADC is made to drop within its dynamic range, thus the dynamic range requirement reduced ADC, alleviate the design pressure of high-precision adc, but the input range of ADC is limited, the Gain tuning of programmable gain amplifier must ensure that its output can not more than the maximum quantization scope of ADC, so usually have a judgment mechanism, i.e. peak detection circuit, be used for judging whether the output of programmable gain amplifier exceeds ADC quantizing range, if do not exceed, then can continue the gain increasing programmable gain amplifier, to ensure that ADC reaches optimum performance, otherwise, if the quantizing range of the ADC exceeded, then need the gain reducing programmable gain amplifier, ensure that ADC can not produce distortion.

Summary of the invention

The problem to be solved in the present invention is just: the technical problem existed for prior art, proposes a kind of differential signal peak-to-peak value testing circuit.

The solution that the present invention proposes is: this circuit is first by the common mode electrical level V of resistance extraction input signal _cm, produce peak-to-peak value by amplifier buffering and detect voltage V _pp, this threshold voltage V _pprespectively with differential input voltage V _pand V _ncompare, and then by commonsource amplifier to electric capacity C ₀carry out charge or discharge and produce voltage V _cvalue, final produce peak-to-peak value testing result Z.

Accompanying drawing explanation

Fig. 1 is circuit theory schematic diagram of the present invention;

Fig. 2 is Simulation results schematic diagram of the present invention;

Embodiment

Below with reference to accompanying drawing and concrete enforcement, the present invention is described in further details.

As shown in Figure 1, the threshold voltage of peak-to-peak value detection

$V_{\mathrm{PP}}=V_{\mathrm{cm}}\·\frac{R_4}{R_3+R_4}$

V _p, V _nthe positive-negative input end of differential signal to be detected, V _pPrespectively with V _p, V _nrelatively, comparative result V is exported _g1, V _g2; NMOS tube M ₁, M ₂respectively with bias current I _b2form commonsource amplifier, V _cfor the output of commonsource amplifier, be the schematic diagram of Fig. 1 Simulation results, wherein V as shown in Figure 2 _threpresent the threshold voltage of NMOS tube M1, M2.

V _p, V _nbe input differential signal to be detected, suppose V _p=Asin ω t+V _cm, V _n=-Asin ω t+V _cm, its common-mode voltage is V _cM, then:

(1), as | V _cM-V _pP| during >A, i.e. V _pPwith V _p, V _nwhen not having overlapping, V _pPbe less than the minimum voltage of input signal, V _g1, V _g2for low level, NMOS tube M ₁, M ₂turn off, now capacitance discharge current I _cbe zero, I _b2to V _cpoint equivalent capacity is charged, and this equivalent capacity comprises C ₀, M ₁, M ₂drain equivalent capacity over the ground, under normal circumstances, and C ₀value much larger than V _cother parasitic capacitances of point, at this, only consider electric capacity C ₀, ignore other parasitic capacitances, so V _ccan be charged, output inverter finally can be made to overturn, detecting and exporting Z is low level.

(2), as | V _cM-V _pK| during <A, i.e. V _pPwith V _p, V _nwhen having overlapping, V _pPbe greater than the minimum voltage of input signal, as shown in Figure 2, V _g1, V _g2for there will be high level, NMOS tube M ₁, M ₂can alternately open, now capacitance discharge current I _cnon-vanishing, i.e. electric capacity C ₀can discharge, and this discharging current equals M ₁, M ₂the leakage current I opened _dS, I _dSmust much larger than I _b2guarantee is worked as | V _cM-V _pP| when being slightly less than A, V _ccan be discharged into low level, output inverter finally can be made to overturn, detecting and exporting Z is high level.

In sum, this peak-to-peak value testing circuit detect input signal peak-to-peak value with relation, the value of R3 and R4 can be changed to change detection threshold, thus realize a kind of differential signal peak-to-peak value testing circuit.

Claims (1)

1. a differential signal peak-to-peak value testing circuit, is characterized in that:

V _p, V _nbe differential input voltage to be detected, be connected respectively to comparator CMP ₁and CMP ₂negative input end resistance R ₁and R ₂one end, resistance R ₁and R ₂the other end be connected to the positive input terminal of AMP, the negative input end of AMP and its output short circuit, and be connected to resistance R ₃one end; Resistance R ₃the other end be connected to resistance R ₄one end and CMP ₁and CMP ₂anode, CMP ₁output V _g1be connected to NMOS tube M ₁grid, CMP ₂output V _g2be connected to NMOS tube M ₂grid, NMOS tube M ₁, M ₂source ground, and respectively with bias current I _b2composition commonsource amplifier, V _cfor the output of commonsource amplifier; Electric capacity C ₀a termination power, another termination V _c; V _creceive the input of inverter INV, the output of INV and differential signal peak-to-peak value testing result Z.