CN103295634B

CN103295634B - Method, memory controller and system for reading data stored in flash memory

Info

Publication number: CN103295634B
Application number: CN201310056538.XA
Authority: CN
Inventors: 杨宗杰
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2012-02-22
Filing date: 2013-02-21
Publication date: 2017-10-27
Anticipated expiration: 2033-02-21
Also published as: CN103295634A; CN107240419B; CN107240419A

Abstract

According to an embodiment of the present invention, a method for reading data stored in a flash memory is disclosed, the method comprising: controlling the flash memory to execute a read operation on a first memory page of the flash memory; obtaining a first codeword of the first memory page; obtaining a first set of likelihood ratio corresponding values of the first codeword according to a first likelihood ratio corresponding rule; performing an error correction operation according to the first set of corresponding values of the approximate ratio; if the error correction operation indicates an uncorrectable result according to the first set of likelihood ratio corresponding values, obtaining a second set of likelihood ratio corresponding values of the first codeword according to a second likelihood ratio corresponding rule; and performing the error correction operation according to the second set of corresponding values of the approximate ratio.

Description

Read the methods of data stored in flash memory, Memory Controller with System

【Technical field】

The present invention is related to read data stored in flash memory (flash memory), espespecially a kind of to pass through ginseng According to the binary digit of the bit sequence (bit sequence) read-out by the memory cell (memory cell) of flash memory Distribution character (binary digit distribution characteristic) is stored to read in flash memory The method and Memory Controller of data.

【Background technology】

Flash memory can carry out data storage by erase (erase) of electronic type with write-in/stylized (program) Deposit, and be widely used in storage card (memory card), solid state hard disc (solid-state drive) and portable many Media player etc..Because flash memory system is non-volatile (non-volatile) memory, it therefore, there is no need to extra Electric power maintains the information stored by flash memory, in addition, flash memory can provide quick digital independent with preferably Shock resistance, and these characteristics also illustrate that the reason for why flash memory can so be popularized.

Flash memory can divide into NOR type flash memory and NAND type flash memory.For NAND flash memory For reservoir, it erases and write time and the less chip area of each memory cell needs with shorter, thus phase Compared with NOR type flash memory, NAND type flash memory can allow higher storage density and relatively low each bit of storage The cost of member.In general, flash memory stores data in the way of memory cell array, and memory cell be by One floating grid transistor (floating-gate transistor) is subject to implementation, and each memory cell can be by suitable Electric charge number on the floating grid of locality control floating grid transistor turns on the floating grid transistor implementation to set The memory cell required critical voltage, and then store the information more than information or a bit of single bit, Consequently, it is possible to when one or more predetermined control grid voltages put on the upper of the control gate of floating grid transistor, then float The conducting state of gridistor will indicate one or more binary digits stored in floating grid transistor (binary digit)。

However, due to some factors, the number of the electric charge stored originally in flash memory cells may be affected/ Upset, for example, the interference in the presence of flash memory may be from disturbing (write/program in write-in Disturbance), reading interference (read disturbance) and/or holding interference (retention disturbance). By taking the NAND type flash memory with the respective memory cell for storing information more than a bit as an example, an entity is deposited Reservoir paging (physical page) can include multiple logical storage pagings (logical page), and each logic is stored Device paging is read out using one or more control gate voltages.For example, for the money to store 3 bits For the flash memory cells of news, the flash memory cells can have to be corresponded to different electric charge numbers (that is, difference is faced respectively Boundary's voltage) one of 8 kinds of states (that is, electric charge level), however, due to the number of times (program/erase that writes/erase Count, P/E count) and/or data retention time (retention time) reason, depositing in flash memory cells The critical voltage distribution (threshold voltage distribution) of storage unit will be changed, and therefore, be used The control gate voltage setting (that is, critical voltage setting) of script come read in memory cell stored information may Because the critical transformation after changing is distributed and can not correctly obtain stored information.

Being set using different control gate voltage may have higher chance to obtain correctly to read flash memory Store information.However, all information acquired using the setting of different control gate voltages of storage may need more storages Space.In addition, set using different control gate voltage and be likely to result in longer reading to read flash memory Time a, accordingly, it would be desirable to reading or decoding program more efficiently.

【The content of the invention】

Therefore, an object of the present invention be to provide a kind of method for reading data stored in flash memory, Memory Controller and device, to solve the above problems.Read method, the memory control of data stored in flash memory Device and device processed.

According to one embodiment of the invention, a kind of method to read the data for being stored in a flash memory is taken off Dew, this method is included：Control a first memory paging of the flash memory to the flash memory to perform one and read running； Obtain one first code word of the first memory paging；General like than the rule of correspondence the one the of first code word is obtained according to one first One group general like than respective value；It is general like than respective value one error correction running of progress according to this first group；If general according to this first group Seemingly error correction running is carried out than respective value and indicate a result that can not be corrected, then generally seemingly taken according to one second than the rule of correspondence Obtain first code word one second group is general like than respective value；And generally seemingly carry out the error correction than respective value according to this second group Running.

According to another embodiment of the present invention, a kind of depositing for data that a flash memory is stored in read is disclosed Memory controller, the Memory Controller is included：One control logic circuit, to control the flash memory to the flash One first memory paging of device performs one and reads running to obtain one first code word of the first memory paging；Without exception like than Corresponding unit, to according to one first it is general like than the rule of correspondence obtain one first group of first code word it is general like than respective value；With And a decoding circuit, to according to this first group it is general like than respective value carry out an error correction running, if wherein according to this first Group is general like when carrying out error correction running than respective value and indicating the result that one can not correct, then this is general like more being used than corresponding unit According to one second it is general like than the rule of correspondence obtain one second group of first code word it is general like than respective value, and the decoding circuit is more For generally seemingly carrying out the error correction running than respective value according to this second group.

According to another embodiment of the present invention, a kind of storage to read the data for being stored in a flash memory is disclosed Device system, the accumulator system is included：One control logic circuit, to control the flash memory to the one of the flash memory First memory paging performs one and reads running to obtain one first code word of the first memory paging；Without exception like more single than correspondence Member, to according to one first it is general like than the rule of correspondence obtain one first group of first code word it is general like than respective value；And one solution Code circuit, to according to this first group it is general like than respective value carry out an error correction running, if wherein according to this first group it is general seemingly When carrying out the result that error correction running instruction one can not be corrected than respective value, then this is general seemingly than corresponding unit more for foundation One second it is general like than the rule of correspondence obtain one second group of first code word it is general like than respective value, and the decoding circuit be more used for according to Generally seemingly the error correction running is carried out according to this second group than respective value.

【Brief description of the drawings】

Fig. 1 is the schematic diagram of the first embodiment of accumulator system of the present invention.

The schematic diagram that Fig. 2 is distributed for physical memory paging P_0 to be read the first critical voltage.

The schematic diagram that Fig. 3 is distributed for physical memory paging P_0 to be read second of critical voltage.

Fig. 4 is that the least significant bit that soft bit member is read from one of flash memory 1100 memory cell reads behaviour The schematic diagram of work.

Fig. 5 is shown in the block diagram of Fig. 1 encoder 1223.

Fig. 6 illustrates the schematic diagram encoded to the binary digit read from flash memory cells.

Fig. 7 illustrates to encode the binary digit read from flash memory cells to obtain the signal of correct data Figure.

Fig. 8 illustrates to encode the binary digit read from flash memory cells to obtain the signal of correct data Figure.

Fig. 9 illustrates to encode the binary digit read from flash memory cells to obtain the signal of correct data Figure.

Figure 10 illustrates the schematic diagram of the corresponding relation of code word and memory cell.

Block diagrams of the Figure 11 to illustrate decoding unit 1228.

Figure 12 illustrates the flow chart for reading the program for the data for being stored in flash memory.

Figure 13 illustrates the schematic diagram of the critical voltage distribution of target entity memory paging.

【Main element symbol description】

102~flash memory

103~memory cell

104~Memory Controller

1000~accumulator system；

1100~flash memory；

1110~memory cell；

1200~Memory Controller；

1210~control logic circuit；

1220~error correction circuit；

1222~error correction decoding device；

1223~encoder；

1224~comparing unit；

1225~judging unit；

1227~storage device；

1228~decoding unit；

1229~error correction encoder；

12280~general like than training unit；

12282~general like than corresponding unit；

12284~decoding circuit；

1230~critical voltage tracing unit

200~214~step.

【Embodiment】

Some vocabulary have been used to censure specific element among specification and follow-up claim.Affiliated neck Has usually intellectual in domain, it is to be appreciated that manufacturer may call same element with different nouns.This specification And follow-up claim is not in the way of the difference of title is used as distinct elements, but with element functionally Difference is used as the benchmark of difference.It is open for one in the "comprising" of specification in the whole text and follow-up claims mentioned in Term, therefore " include but be not limited to " should be construed to.In addition, " coupling " one word is included any direct and indirectly electrically connected herein Take over section.Therefore, if a first device is electrically connected at a second device described in text, representing the first device can directly connect The second device is connected to, or the second device is coupled indirectly to by other devices or connection means.

Note that, read many stored by the memory cell in the physical memory paging of NAND type flash memory Individual bit is only as an embodiment, to illustrate the technical characteristic of the present invention, however, no matter flash memory is NAND quick flashing Memory or with other types of flash memory (such as NOR type flash memory), as long as fortune will be read from different Acquired binary digit is encoded into code word to carry out error correction running in work, meets the spirit of the present invention.

Referring to Fig. 1, its schematic diagram for the first embodiment of accumulator system of the present invention.Accumulator system 1000 is included There are a flash memory 1100 and a Memory Controller (memory controller) 1200, in the present embodiment, quick flashing Memory 1100 can be comprising multiple physical memory paging P_0, P_1, P_2 ..., P_N NAND type flash memory, its Each physical memory paging in middle physical memory paging P_0~P_N includes multiple memory cells (such as floating gate Gated transistors) 1110, for example, for target entity memory paging P_0 one of to be read, it includes storage Device unit M_0~M_K.Stored number in memory cell M_0~M_K in order to read target entity memory paging P_0 According to control gate voltage VG_0~VG_N just will should suitably be set, for example, control gate voltage VG_0~VG_N should be wanted Suitably it is set to ensure that memory cell (floating gate memories) 103 all in physical memory paging P_1~P_N are equal It is in the conduction state.If each memory cell 103 is to store N number of bit (for example, comprising least significant bit (least significant bit, LSB), middle effectively bit (central significant bit, CSB) have with highest Imitate 3 bits of bit (most significant bit, MSB)), then flash memory 102 can be by control gate voltage VG_ 0 is set as (2^N- 1) individual voltage quasi position, to pick out the N of each memory cell 103 in target entity memory paging P_0 Individual bit.

Referring to Fig. 2, its signal for physical memory paging P_0 to be read the first critical voltage distribution Figure.Physical memory paging P_0 memory cell M_0~M_K can include stylized with floating grid (programmed) for the memory cell with electric charge level L0 (that is, (MSB, CSB, LSB)=(1,1,1)), with floating Grid is turned to memory cell with electric charge level L1 (that is, (MSB, CSB, LSB)=(0,1,1)) by formula, with floating Grid is turned to memory cell with electric charge level L2 (that is, (MSB, CSB, LSB)=(0,0,1)) by formula, with floating Grid is turned to memory cell with electric charge level L3 (that is, (MSB, CSB, LSB)=(1,0,1)) by formula, with floating Grid is turned to memory cell with electric charge level L4 (that is, (MSB, CSB, LSB)=(1,0,0)) by formula, with floating Grid is turned to memory cell with electric charge level L5 (that is, (MSB, CSB, LSB)=(0,0,0)) by formula, with floating Grid by formula turn to electric charge level L6 (that is, (MSB, CSB, LSB)=(0,1,0)) memory cell and have Floating grid is turned to the memory cell with electric charge level L7 (that is, (MSB, CSB, LSB)=(1,1,0)) by formula.

In order to pick out memory cell M_0~M_K least significant bit, flash memory 102 is just by control gate Voltage VG_0 is set as the critical voltage VT_4 shown in Fig. 2, then, each memory cell in physical memory paging P_0 The least significant bit that conducting state will indicate the memory cell and have is " 0 " or " 1 ".In the present embodiment, when When the critical voltage VT_4 that one of physical memory paging P_0 memory cell is applied in its control gate is turned on, soon Flash memory 1100, which will be exported, represents one of its least significant bit binary digit " 1 "；Otherwise, flash memory 1100 Another binary digit for representing its least significant bit will be exported " 0 ".

In order to pick out the memory cell M_0~M_K effective bit in centre, flash memory 1100 is just by control gate Voltage VG_0 is respectively set as critical voltage VT_2 and VT_6 shown in Fig. 2, similarly, each in physical memory paging P_0 The conducting state of memory cell will indicate that the effective bit in centre that the memory cell has is " 0 " or " 1 ".Yu Ben In embodiment, when the critical voltage VT_2 that a memory cell can be applied in its control gate is led with any one in VT_6 When logical, flash memory 1100, which will be exported, represents one of its middle significance bit member binary digit " 1 "；When the memory list The critical voltage VT_2 that member will not be applied in its control gate is turned on, but can be applied in the critical of its control gate When voltage VT_6 is turned on, flash memory 102, which will be exported, represents one of its middle significance bit member binary digit " 0 "； And when the memory cell is turned on except that will not be applied in the critical voltage VT_2 of its control gate, will not also be applied in When the critical voltage VT_6 of its control gate is turned on, flash memory 1100, which will be exported, represents its middle significance bit member One binary digit " 1 ".

In order to pick out memory cell M_0~M_K highest significant position member, flash memory 1100 is just by control gate Voltage VG_0 is respectively set as critical voltage VT_1, VT_3, VT_5 and VT_7 shown in Fig. 2, similarly, physical memory paging The highest significant position member that the conducting state of each memory cell will indicate the memory cell and have in P_0 is " 0 " Or " 1 ".In the present embodiment, when a memory cell can be applied in critical voltage VT_1, VT_3, VT_5 of its control gate When being turned on any one in VT_7, flash memory 1100, which will be exported, represents one of its highest significant position member binary bit Numeral " 1 "；When the critical voltage VT_1 that the memory cell will not be applied in its control gate is turned on, but it can be applied When any one being added in critical voltage VT_3, VT_5 and VT_7 of its control gate is turned on, flash memory 1100 will Output represents one of its highest significant position member binary digit " 0 "；When the memory cell will not be applied in its control gate Critical voltage VT_1 and any one in VT_3 of pole are turned on, but can be applied in the critical voltage of its control gate When any one in VT_5 and VT_7 is turned on, flash memory 1100, which will be exported, represents one of its highest significant position member individual two Carry digit " 1 "；When the memory cell will not be applied in critical voltage VT_1, VT_3 and VT_5 of its control gate Any one is turned on, but when can be applied in the critical voltage VT_7 of its control gate and turning on, flash memory 1100 Will export and represent one of its highest significant position member binary digit " 0 "；And when the memory cell will not be applied in When any one in critical voltage VT_1, VT_3, VT_5 and VT_7 of its control gate is turned on, flash memory 1100 will Output represents one of its highest significant position member binary digit " 1 ".

However, the critical voltage distribution shown in Fig. 2 may be because of some factors (such as write-in/reading times and/or number According to the increase of retention time) influence and change into the distribution of another critical voltage, for example, correspondence is to each electric charge level The distribution of circular standing shape may broaden and/or produce skew.Referring to Fig. 3, it is physical memory to be read The schematic diagram of paging P_0 second of critical voltage distribution.It can be learnt by Fig. 3, critical voltage distribution is different from facing shown in Fig. 2 Boundary's voltage's distribiuting.Control gate voltage VG_0 is set as that above-mentioned critical voltage VT_1~VT_7 will be unable to correctly obtain mesh Least significant bit, middle effectively bit and the highest for marking physical memory paging P_0 memory cell M_0~M_K are effective Bit is furthermore, it is understood that when memory cell M_0~M_K has the critical voltage distribution shown in Fig. 3, it should to use newly Critical voltage VT_1 '~VT_7 ' correctly to obtain stored information, otherwise, put on memory cell M_0~ Error correction (error correction code, the ECC) operation of code word (codeword) read-out by M_K will be because of code (uncorrectable) mistake that can not be corrected in word and can not successful operation.In the present embodiment, Memory Controller 1200 The code word for being designed to adaptively read memory cell M_0~M_K performs soft decoding to strengthen decoding capability.Details It is described in detail in rear.

Referring to Fig. 1.Memory Controller 104 is that the access for controlling flash memory 102 (is read/write Enter), and include (but a being not limited to) control logic circuit 1210 and an error correction circuit (ECC circuit, its With an error correction decoding device 1222, an error correction encoder 1229 and a critical voltage tracing unit 1230).It please note Meaning, Fig. 1 only shows the element relevant with the technical characteristic of the present invention, that is, Memory Controller 104 can also include extra member Part supports other functions.In general, when receiving for memory cell M_0 in target entity memory paging P_0 During one of data stored by~M_K read requests (read request), control logic circuit 1210 can be asked in response to the reading Ask and control flash memory 1100 to read required data (requested data), then, when flash memory 102 When successfully picking out in memory cell M_0~M_K all bits stored by each memory cell, include memory The reading information of the unit M_0~M_K bit picked out will be received by control logic circuit 1210.Such as it is familiar with skill It is for storing error correction information (such as one positioned at one of physical memory paging part memory cell known to person Error correcting code (ECC code)), therefore, error correction circuit 1220 is for for being read by flash memory 1100 Reading information (a such as code word) out carries out an error correction operation.In the present embodiment, error correction circuit 1220 is wrapped Contain an error correction decoding device (ECC decoder) 1222 and an error correction encoder (ECC corrector) 1229. Error correction decoding device 1222 is the correctness that information is read for checking, thereby to detect the presence of any wrong bit.It is wrong By mistake corrigendum decoder 1222 be also used for found in the readings information that checked to wrong bit corrected however, working as reading Go out the wrong bit of physical presence in information quantity exceeded error correction decoding device 1222 have method according to hard decoder (for example BCH (Bose-Chaudhuri-Hocquenghem mode)) corrigendum wrong bit maximum quantity when, error correction decoding Device 1222 will indicate that control logic circuit 1210 is read in information and include the mistake that can not be corrected.Consequently, it is possible to control to patrol Soft reading (soft read) mechanism will be started to obtain soft information by collecting circuit 1210, and those soft information can be by ECC decoder 1222 are used for carrying out soft decoding mechanism.The critical voltage tracing unit 1230 is used to by comparing reading information judge critical electricity Press moving direction and judge an optimal critical voltage.Details is described in detail in rear.

In the present embodiment, error correction decoding device 1222 can be by low density parity check (low density parity- Check, LDPC) decoder is subject to implementation, and the control flash memory 1100 of control logic circuit 1210 will be by LDPC to provide The soft information (soft information) that decoder is decoded, so, under the control of control logic circuit 1210, quick flashing Memory 1100 just exports multiple binary digits and is used as the soft bit member that each memory cell M_0~M_K is read out (soft bit).Furthermore, it is understood that when carrying out the reading of least significant bit metadata, the middle effectively reading of bit Data or most During the high effectively reading of bit Data, control logic circuit 1210 is to control flash memory 1100 to be directed to target entity Each memory cell in memory cell M_0~M_K of memory paging performs repeatedly read operation (such as 7 times readings Operation).

Referring to Fig. 4, it is reads soft bit member (that is, soft information from one of flash memory 1100 memory cell Numerical value) least significant bit read operation schematic diagram.According to the example of the critical voltage distribution shown in Fig. 2 and Fig. 3, have The memory cell of any of electric charge level L0~L3 electric charge level will store LSB=1, and with electric charge level L4~ The memory cell of any of L7 electric charge levels can then store LSB=0.In the present embodiment, control logic circuit 1210 is determined A fixed initial control gate voltage V_LSBAnd voltage spacing (voltage spacing) D, then control flash memory 1100 each memory cell to be directed in memory cell M_0~M_K performs 7 read operations, and based on voltage adjustment Order (voltage adjusting order) OD1, flash memory 1100 can be sequentially with V_LSB、V_LSB+D、V_LSB-D、V_LSB+ 2D、V_LSB-2D、V_LSB+3D、V_LSB- 3D sets control gate voltage VG_0, therefore, because the grid-control voltage applied V_LSB、V_LSB+D、V_LSB-D、V_LSB+2D、V_LSB-2D、V_LSB+3D、V_LSBIt is each in -3D reason, bit sequence BS_0~BS_M Bit sequence all can sequentially obtain 7 bits.It note that each bit sequence in bit sequence BS_0~BS_M is soft as one Bit, it represents the soft information read out by a memory cell, and passes through initial control gate voltage V_LSBObtained Binary digit can be used as a sign bit (sign bit) (that is, hard bit (hard bit) numerical value).Utilize initial control Grid voltage V_LSBThe reading running carried out can be considered general and read running.And utilize control gate voltage V_LSB+D、V_LSB-D、 V_LSB+2D、V_LSB-2D、V_LSB+3D、V_LSBThe reading running that -3D is carried out can be respectively seen as reading running 1~6 again.

In the present embodiment, each bit sequence have eight kinds of possible binary digits combination BS1~BS8 wherein it One.When the electric charge for the floating grid for being stored in memory cell at present is so that the critical voltage of memory cell is higher than V_LSB+ 3D, The bit sequence then read out from memory cell will have binary digit to combine BS8=" 0000000 "；When current The electric charge of the floating grid of memory cell is stored in so that the critical voltage of memory cell is between V_LSB+ 2D and V_LSB+ 3D it Between, then the bit sequence read out from memory cell will have binary digit to combine BS7=" 0000010 "；When The electric charge of floating grid of memory cell is stored at present so that the critical voltage of memory cell is between V_LSB+ D and V_LSB+2D Between, then the bit sequence read out from memory cell will have binary digit to combine BS6=" 0001010 "； When the electric charge for the floating grid for being stored in memory cell at present is so that the critical voltage of memory cell is between V_LSBWith V_LSB+D Between, then the bit sequence read out from memory cell will have binary digit to combine BS5=" 0101010 "； When the electric charge for the floating grid for being stored in memory cell at present is so that the critical voltage of memory cell is less than V_LSB- 3D, then from The bit sequence that memory cell is read out will have binary digit to combine BS1=" 1111111 "；When current storage Cause the critical voltage of memory cell between V in the electric charge of the floating grid of memory cell_LSB- 2D and V_LSBBetween -3D, then The bit sequence read out from memory cell will have binary digit to combine BS2=" 1111110 "；When current storage The electric charge of the floating grid of memory cell is stored in so that the critical voltage of memory cell is between V_LSB- D and V_LSBBetween -2D, The bit sequence then read out from memory cell will have binary digit to combine BS3=" 1111010 "；And work as The electric charge of floating grid of memory cell is stored at present so that the critical voltage of memory cell is between V_LSBWith V_LSB- D it Between, then the bit sequence read out from memory cell will have binary digit to combine BS4=" 1101010 ".

When binary digit all in a bit sequence is " 1 " when, this represents corresponding memory cell tool There are electric charge level L0, L1, L2 or L3, and LSB=1 reliability (reliability) is very high.On the other hand, when a bit All binary digits are in sequence " 0 " when, this, which represents corresponding memory cell, has electric charge level L5, L6, L7 Or L8, and LSB=0 reliability is very high.However, there are different binary digits when a bit sequence " 0 " with " 1 " mix When wherein, this, which represents corresponding memory cell, has electric charge level L3 or L4, critical due to corresponding memory cell Voltage is between V_LSB- 3D and V_LSBBetween+3D, LSB=1/LSB=0 reliability will be higher and relatively low due to error rate, lifts For example, storage LSB=0 memory cell can have correspondence to face to electric charge level L4 electric charge stored number originally Boundary's voltage is higher than V_LSB+ 3D, however, when writing/erasing number of times or data retention time increase, the quantity of stored electric charge It will change, thus critical voltage may be caused to be less than V_LSB；Similarly, LSB=1 memory cell meeting is stored originally With correspondence to electric charge level L3 electric charge stored number with cause critical voltage be less than V_LSB- 3D, compared to hard decoder, is present Correct probability is decoded when the reliability of soft information numerical value can increase and carry out soft decoding.But soft information numerical value is contained in Running and multiple binary digits acquired by follow-up stressed running 1~6 are typically read, as previously described seven binary digits Word.In order to perform soft decoding, error correction decoding device 1222 must obtain and store complete soft information numerical value, therefore, mistake Corrigendum decoder 1222 needs substantial amounts of storage area to store complete soft information numerical value.This will increase chip area with into This.

To reduce storage area, the binary digit obtained from reading running just can first be encoded before storing or decoding For a shorter code word.Referring now to Fig. 1, as it was previously stated, error correction circuit 1220 is used for from flash memory 1100 The reading information of middle acquirement carries out error correction running.And error correction decoding device 1222 is used for checking the correct of reading information Property.In addition, error correction decoding device 1222 further includes an encoder 1223, a storage device 1227 and a decoding unit 1228.Encoder 1223 is used to produce a shorter code word representative according to the binary digit read from flash memory 1100 The binary digit.The code word and the stored code word of offer that storage device 1227 is produced to store by encoder, which are given, decodes single Member 1228.Decoding unit 1228 is to perform error correction running to the code word.Details is described in detail in rear.

In one embodiment, control logic circuit 1210 controls flash memory 1100 according to initial control gate voltage V_LSBTo memory cell, such as physical memory paging P_0 memory cell factory M_0~M-K carries out one and reads running To recognize memory cell factory M_0~M-K least significant bit.According to initial control gate voltage V_LSBThe reading carried out Take running to can be considered general and read running.Flash memory 1100 provides and contains data division, spare part and an at least school The binary digit (a page of binary digits) for testing the storage paging of one of code (parity) part is electric to control logic Road 1210.Its binary digit for being received of the transmission of control logic circuit 1210 is to error correction circuit 1220.In an embodiment In, the binary digit received is divided into two parts by error correction circuit 1220.Part I comprising data division with Its corresponding check code part.Part II includes spare part and its corresponding check code part.Error correction circuit 1220 pairs of Part I carry out soft decoding running (soft decode operation), and carry out rigid solution to Part II Code running (hard decode operation).This is illustrative, and the limitation of non-invention.Enter to the two of the paging It is scope of the invention that any portion of bit digital, which carries out soft decoding or rigid decoding running,.In this embodiment, encode Device 1223 produces a code word according to the binary digit of Part I.Details is described in detail in rear.

Fig. 5 and Fig. 6 are refer to, Fig. 5 is shown in the block diagram of Fig. 1 encoder 1223.Fig. 6 illustrates to reading from flash memory The schematic diagram that the binary digit of unit is encoded.Encoder 1223 includes a comparing unit 1224 and a judging unit 1225.Fig. 5 only shows the element relevant with the technical characteristic of the present invention, that is, encoder 1223 can also include extra element To support other functions.Comparing unit 1224 is used for the binary digit for comparing the Part I sent from control logic circuit And it is stored in the positive and negative bit of storage device 1227.When reading a target entity memory paging, (for example physical memory divides Page P_0) when, control logic circuit 1210 controls flash memory 1100 according to an initial control gate voltage V_LSBTo memory Cell factory (such as physical memory paging P_0 memory cell M_0~M_K) carries out one and reads running with recognition memory Cell M_0~M_K least significant bit.As shown in fig. 6, the binary digit of the Part I of the physical memory paging is passed Deliver to encoder 1223.Note that, each bit of those binary digits represents physical memory paging P_0 storage The hard bit (hard bit, also referred to as hard information (hard information)) of the least significant bit of device cell factory. For example, the leftmost binary digit of those binary digits is " 1 ", the memory that it represents physical memory paging P_0 is thin The hard bit system of born of the same parents M_0 least significant bit is " 1 ".Two beside the leftmost binary digit of those binary digits enter Bit digital is " 1 ", its represent the hard bit of physical memory paging P_0 memory cell M_1 least significant bit as " 1 ", by that analogy.Because the binary digit of Part I is derived to those memory cell factories according to initial control gate electricity Pressure is read out running, and those binary digits can be considered the sign bit of those memory cells.Accordingly, encoder 1223 Produce (and setting) high intensity bit as " 1 " low-intensity bit be " 1 ", to represent positive and negative bit " 1 " there is highest Reliability.In other words, memory cell M_0 is assumed to be " 1 ", and with highest reliability.In addition, including hard bit " 1 " and soft bit it is first (soft bit, also referred to as soft information (soft information)) " 11 " code word " 111 " be used for generation Information stored by table memory cell M_0.For representing the code word of other memory cells also according to similar mode progress. Then, the code word of the binary digit of Part I is sent to storage device 1227.Then, storage device 1227 puies forward the code word Supply decoding unit 1228 is operated with performing error correction.In one embodiment, the decoding unit 1228 is performed according to the code word One error correction hard decoder (error correction hard decode) in another embodiment, the decoding unit 1228 according to If performing error correction hard decoder error correction running according to the sign bit points out that the code word is correct or can correct (in other words Error correction hard decoder indicates a result that can be corrected), then this result is notified control logic circuit by error correction circuit 1220 1210, and correct data are supplied to control logic circuit 1210.If the code word (or sign is pointed out in error correction running Bit) can not correct (in other words error correction hard decoder indicates the result that can not correct), error correction circuit 1220 by this As a result control logic circuit 1210 is notified, and control logic circuit 1210 controls flash memory 1100 according to control gate voltage V_LSB+ D carries out one to memory cell factory and reads running again (D is a predetermined voltage spaces).Details is described in detail in rear.

Fig. 7 is refer to, Fig. 7 illustrates to encode the binary digit read from flash memory cells to obtain positive exact figures According to schematic diagram.When reading a target entity memory paging (for example, physical memory paging P_0), control logic circuit 1210 control flash memories 1100 are according to the second control gate voltage V_LSB+ D is to memory cell (for example, physical memory point Page P_0 memory cell M_0~M_K) a reading running is performed with interpretation memory cell M_0~M_K least significant bit Member.This, which reads running again, can be considered as reading running again for the first time.As shown in fig. 7, the two of the Part I of the physical memory paging Carry digit delivers to coding unit 1223.Note that, each bit of those binary digits represents a physical memory point The soft bit member of one of the page P_0 least significant bit of memory cell factory.For example, those binary digits leftmost two enter Bit digital is " 1 ", its represent the soft bit member of physical memory paging P_0 memory cell M_0 least significant bit as " 1”.Binary digit beside the leftmost binary digit of those binary digits is " 0 ", it represents physical memory paging The soft bit member of P_0 memory cell M_1 least significant bit is " 0 ", by that analogy.Note that, two shown in Fig. 7 enter Bit digital (stressed data) may be not exclusively identical with sign bit.Because the control gate read again for the first time running Pole tension is V_LSB+ D, so utilizing grid-control voltage V_LSBWith V_LSB+ D reads critical voltage and fallen in V_LSBWith V_LSB+ D's deposits Different results can be obtained during storage unit.For example, according to control gate voltage V_LSBAcquired memory cell M_1 is most The sign bit of low order member is " 0 ", and according to control gate voltage V_LSBMemory cell M_1 acquired by+D is most Low order member soft bit member be " 1 ".Therefore, encoder 1223 needs to update memory cell M_1 least significant bit Code word reliability.Details is described in detail in rear.

According to control gate voltage V_LSBRead data (binary digit) acquired by+D again and deliver to comparing unit 1224.Compare Unit 1224 accesses the sign bit for being stored in storage device 1227, and compares sign bit with stressed data to update code Word.If the stressed data (binary digit) of sign bit corresponding thereto are identical, comparing unit 1224 indicates the result Judging unit 1225.And judging unit 1225 judges to maintain the reliability of the sign bit.In other words, it is relative for expressing The code word for the memory cell answered is not changed.If the stressed data (binary digit) of sign bit corresponding thereto not phase Together, the result is indicated judging unit 1225 by comparing unit 1224.And judging unit 1225 judges to update the sign bit Reliability to a minimum reliability.In other words, it is changed for expressing the code word of corresponding memory cell.For example, according to According to control gate voltage V_LSBThe sign bit of acquired memory cell M_1 least significant bit is " 0 ", and according to Control gate voltage V_LSBThe soft bit member of the least significant bit of memory cell M_1 acquired by+D is " 1 ".Accordingly, judge single Member 1225 judges a high intensity bit " 0 " and a low-intensity bit " 0 " to represent sign bit " and 1 " have it is minimum reliable Degree.In other words, memory cell M_1 least significant bit is updated to minimum reliability " 0 ".In addition, including hard position The code word of member " 0 " and soft bit member " 00 " " 000 " is used for representing memory cell M_1 least significant bit.For expressing it The code word of his memory cell is also carried out according to similar mode.Then, the code of the binary digit of the Part I after renewal Word delivers to the code word original to update of storage device 1227.Then, the code word after renewal is supplied to solution by storage device 1227 Code unit 1228 is operated with performing error correction.In one embodiment, decoding unit 1228 carries out one according to the code word after renewal The soft decoding (error correction soft decode) of error correction notes that the code word after renewal is by comparing foundation Control lock and voltage V_LSBStressed data (binary digit) acquired by+D and according to control lock and voltage V_LSBAcquired Sign bit and obtain.In other words, the soft decoding of error correction is entered according to sign bit with stressed data (binary digit) Capable.If error correction running points out that the code word after updating is correct or can correct that (the in other words soft decoding of error correction indicates that one can The result of corrigendum), then this result is notified control logic circuit 1210 by error correction circuit 1220, and correct data are provided To control logic circuit 1210.If error correction running points out that the code word after updating can not correct (the in other words soft solution of error correction Code indicates a result that can not be corrected), this result is notified control logic circuit 1210 by error correction circuit 1220, and controls to patrol Collect circuit 1210 and control flash memory 1100 according to control gate voltage V_LSB- D carries out one to memory cell factory and reads fortune again Make (D is a predetermined voltage spaces).According to control gate voltage V_LSBThe stressed running that-D is carried out to memory cell factory It can be considered that second reads running again.Note that, the general voltage spaces and general reading fortune for reading running and the first stressed running Make identical with the voltage spaces that second reads running again.Therefore, the rule for updating code word reliability should be similar, according to second of weight The generation of the stressed data acquired by running is read to omit herein with storing the details of code word.If second of weight is pointed out in error correction running Read the code word after the renewal obtained by running correctly or can correct (the in other words soft decoding of error correction indicates a result that can be corrected), Then this result is notified control logic circuit 1210 by error correction circuit 1220, and correct data are supplied into control logic electricity Road 1210.If error correction running points out that second code word read again after the renewal obtained by running can not correct (in other words mistake The soft decoding of corrigendum indicates a result that can not be corrected), this result is notified control logic circuit 1210 by error correction circuit 1220, And control logic circuit 1210 controls flash memory 1100 according to control gate voltage V_LSB+ 2D enters to memory cell factory Row one reads running again (D is a predetermined voltage spaces).According to control gate voltage V_LSB+ 2D is entered to memory cell factory Capable stressed running can be considered that the 3rd reads running again.In addition, running and the first stressed running are read by comparing from general Acquired binary digit, can obtain reading running and the first binary digit for reading Part I in running again general Bit change (bit flopping) sum, and bit changing number BF1 can be designated as.Similarly, by comparing from general Read running and read the binary digit acquired by operating again with second, can obtain reading running and the second stressed running general The bit of the binary digit of middle Part I changes sum, and can be designated as bit changing number BF2.Bit changing number BF1 It can be used to follow the trail of an optimal critical voltage with BF2.After details is specified in.

Fig. 8 is refer to, Fig. 8 illustrates to encode the binary digit read from flash memory cells to obtain positive exact figures According to schematic diagram.When reading a target entity memory paging (for example, physical memory paging P_0), control logic circuit 1210 control flash memories 1100 are according to the 3rd control gate voltage V_LSB+ 2D is to memory cell (for example, physical memory Paging P_0 memory cell M_0~M_K) a reading running is performed with the minimum effective of interpretation memory cell M_0~M_K Bit.This, which reads running again, can be considered as the stressed running of third time.As shown in figure 8, the Part I of the physical memory paging Binary digit delivers to coding unit 1223.Note that, each bit of those binary digits represents a physical memory The soft bit member of the least significant bit of one of paging P_0 memory cell factories.For example, those binary digits leftmost two Carry digit is " 0 ", it represents the soft bit member of physical memory paging P_0 memory cell M_0 least significant bit.Please It is noted that the binary digit (stressed data) shown in Fig. 8 may be not exclusively identical with sign bit.Because to carry out It is V that three times, which are read again the control gate voltage operated,_LSB+ 2D, so utilizing grid-control voltage V_LSBWith V_LSB+ 2D reads critical Voltage falls in V_LSBWith V_LSBDifferent results can be obtained during+2D memory cell.For example, according to control gate voltage V_LSBInstitute The sign bit of the memory cell M_0 of acquirement least significant bit is " 0 ", and according to control gate voltage V_LSB+ 2D institute The soft bit member of the memory cell M_0 of acquirement least significant bit is " 1 ".Therefore, encoder 1223 needs more new memory The reliability of the code word of unit M_0 least significant bit.Details is described in detail in rear.

According to control gate voltage V_LSBRead data (binary digit) acquired by+2D again and deliver to comparing unit 1224.Compare Unit 1224 accesses the sign bit for being stored in storage device 1227, and compares sign bit with stressed data to update code Word.Note that, some binary digits may be corresponding thereto in reading running again in first time and reading running again for the second time Sign bit it is different.The reliability of those binary digits will be no longer updated.Comparing unit 1224 can be neglected those two Carry digit.Judging unit 1225 then maintains the reliability of the code word after the renewal.In other words, when high intensity bit and low strong Degree bit has been updated, and judging unit 1225 maintains the value of high intensity bit and low-intensity bit.If sign bit Stressed data (binary digit) corresponding thereto are differed, and the result is indicated judging unit 1225 by comparing unit 1224. And judging unit 1225 judges to maintain the reliability of the sign bit.In other words, to express corresponding memory list The code word of member does not change.If the stressed data (binary digit) of sign bit corresponding thereto are differed, comparing unit The result is indicated judging unit 1225 by 1224.And judging unit 1225 judges to update the reliability of the sign bit to one Higher reliability.In other words, it is changed for expressing the code word of corresponding memory cell.For example, according to control gate Voltage V_LSBThe sign bit of acquired memory cell M_0 least significant bit is " 0 ", and according to control gate electricity Press V_LSBThe soft bit member of the least significant bit of memory cell M_0 acquired by+2D is " 1 ".Accordingly, judging unit 1225 is sentenced The low-intensity bit of a fixed high intensity bit " 0 " and one " 1 " is to represent sign bit " 1 " there is higher reliability.Change speech It, memory cell M_0 least significant bit is updated to compared with high-reliability " 0 ".In addition, including hard bit " 0 " with And soft bit member " 01 " code word " 001 " be used for representing memory cell M_0 least significant bit.For expressing other memories The code word of unit is also carried out according to similar mode.Then, the code word of the binary digit of the Part I after renewal delivers to storage The code word original to update of cryopreservation device 1227.Then, the code word after renewal is supplied to decoding unit by storage device 1227 1228 are operated with performing error correction.In one embodiment, decoding unit 1228 carries out a mistake more according to the code word after renewal Just soft decoding.Note that, the code word after renewal is by comparing according to control lock and voltage V_LSBStressed data acquired by+2D (binary digit) and according to control lock and voltage V_LSBAcquired sign bit and obtain.In other words, the soft solution of error correction What code was carried out according to sign bit and stressed data (binary digit).If the code word after updating is pointed out in error correction running Be correct or (the in other words soft decoding of error correction indicates the result that can correct) can be corrected, then error correction circuit 1220 by this As a result control logic circuit 1210 is notified, and correct data are supplied to control logic circuit 1210.If error correction is operated Point out that the code word after updating can not correct (the in other words soft decoding of error correction indicates a result that can not be corrected), error correction electricity This result is notified control logic circuit 1210 by road 1220, and control logic circuit 1210 controls flash memory 1100 according to control Grid voltage V processed_LSB- 2D carries out one to memory cell factory and reads running again (D is a predetermined voltage spaces).Details is described in detail Yu Hou.

According to control gate voltage V_LSBThe stressed running that -2D is carried out to memory cell factory can be considered that the 4th reads again Running.Note that, general reading running is operated and the 4th stressed fortune with the voltage spaces of the 3rd stressed running and general read The voltage spaces of work are identical.Therefore, the rule for updating code word reliability should be similar, is read again according to the 4th time acquired by running Data generation is read again to omit herein with storing the details of code word.If error correction running is pointed out to read again obtained by running more for the 4th time Code word after new is correct or can correct (the in other words soft decoding of error correction indicates a result that can be corrected), then error correction circuit This result is notified control logic circuit 1210 by 1220, and correct data are supplied into control logic circuit 1210.If mistake Correct running and point out that the code word after the renewal obtained by the 4th stressed running can not correct (the in other words soft decoding instruction of error correction One result that can not be corrected), this result is notified control logic circuit 1210, and control logic circuit by error correction circuit 1220 1210 control flash memories 1100 are according to control gate voltage V_LSB+ 3D carries out one to memory cell factory and reads running again.According to According to control gate voltage V_LSBThe stressed running that+3D is carried out to memory cell factory can be considered that the 5th reads running again.Except this it Outside, running and the binary digit acquired by the 3rd stressed running are read by comparing from general, can obtains typically reading Running changes (bit flopping) sum with the 3rd bit for reading the binary digit of Part I in running again, and can be by it It is designated as bit changing number BF3.Similarly, running and the binary digit acquired by the 4th stressed running are read by comparing from general Word, can obtain changing sum in the general bit for reading running and the 4th binary digit for reading Part I in running again, And bit changing number BF4 can be designated as.Bit changing number BF3 and BF4 can be used to follow the trail of an optimal critical voltage.Details is detailed After being set forth in.

Fig. 9 is refer to, Fig. 9 illustrates to encode the binary digit read from flash memory cells to obtain positive exact figures According to schematic diagram.When reading a target entity memory paging (for example, physical memory paging P_0), control logic circuit 1210 control flash memories 1100 are according to the 5th control gate voltage V_LSB+ 5D is to memory cell (for example, physical memory Paging P_0 memory cell M_0~M_K) a reading running is performed with the minimum effective of interpretation memory cell M_0~M_K Bit.This, which reads running again, can be considered as the 5th stressed running.As shown in figure 9, the Part I of the physical memory paging Binary digit delivers to coding unit 1223.Note that, each bit of those binary digits represents a physical memory The soft bit member of the least significant bit of one of paging P_0 memory cell factories.For example, the two of those binary digit rightmosts Carry digit is " 0 ", it represents the soft bit member of physical memory paging P_0 memory cell M_0 least significant bit.Please It is noted that the binary digit (stressed data) shown in Fig. 9 may be not exclusively identical with sign bit.Because to carry out It is V that five times, which are read again the control gate voltage operated,_LSB+ 3D, so utilizing grid-control voltage V_LSBWith V_LSB+ 3D reads critical Voltage falls in V_LSBWith V_LSBDifferent results can be obtained during+3D memory cell.For example, according to control gate voltage V_LSBInstitute The sign bit of the memory cell M_K of acquirement least significant bit is " 1 ", and according to control gate voltage V_LSB+ 3D institute The soft bit member of the memory cell M_0 of acquirement least significant bit is " 1 ".Therefore, encoder 1223 needs more new memory The reliability of the code word of unit M_K least significant bit.Details is described in detail in rear.

According to control gate voltage V_LSBRead data (binary digit) acquired by+3D again and deliver to comparing unit 1224.Compare Unit 1224 accesses the sign bit for being stored in storage device 1227, and compares sign bit with stressed data to update code Word.Note that, what some binary digits may be corresponding thereto in reading again and operate at first, second, third, fourth time Sign bit is different.The reliability of those binary digits will be no longer updated.Comparing unit 1224 can be neglected those and two enter Bit digital.Judging unit 1225 then maintains the reliability of the code word after the renewal.In other words, when high intensity bit and low-intensity Bit has been updated, and judging unit 1225 maintains the value of high intensity bit and low-intensity bit.If sign bit with Its corresponding stressed data (binary digit) is identical, and the result is indicated judging unit 1225 by comparing unit 1224.Change speech It, to express, the code word of corresponding memory cell does not change.If the stressed data (two of sign bit corresponding thereto Carry digit) differ, the result is indicated judging unit 1225 by comparing unit 1224.And judging unit 1225 judges to update The reliability of the sign bit is to a higher reliability.In other words, for expressing the code word of corresponding memory cell It is changed.For example, according to control gate voltage V_LSBThe sign bits of acquired memory cell M_K least significant bit Member is " 0 ", and according to control gate voltage V_LSBThe soft bit member of the least significant bit of memory cell M_K acquired by+3D It is " 1 ".Accordingly, judging unit 1225 judges a high intensity bit " 1 " and a low-intensity bit " 0 " to represent sign bits Member " 1 " has higher reliability.In other words, memory cell M_K least significant bit has been updated to compared with high-reliability " 0 ".In addition, including hard bit " 0 " and soft bit member " 10 " code word " 010 " be used for represent the minimum of memory cell M_K Effective bit.For expressing the code word of other memory cells also according to similar mode progress.Then, first after renewal The code word of the binary digit divided delivers to the code word original to update of storage device 1227.Then, storage device 1227 will more Code word after new is supplied to decoding unit 1228 to perform error correction running.In one embodiment, the foundation of decoding unit 1228 Code word after renewal carries out the soft decoding of an error correction.Note that, the code word after renewal is by comparing according to control lock and electricity Press V_LSBStressed data (binary digit) acquired by+3D and according to control lock and voltage V_LSBAcquired sign bit And obtain.In other words, the soft decoding of error correction is carried out according to sign bit and stressed data (binary digit).If mistake Corrigendum running points out that the code word after updating is correct or can correct that (the in other words soft decoding of error correction indicates the knot that can correct Really), then this result is notified control logic circuit 1210 by error correction circuit 1220, and is supplied to control to patrol correct data Collect circuit 1210.If error correction running points out that the code word after updating can not correct (the in other words soft decoding instruction one of error correction The result that can not be corrected), this result is notified control logic circuit 1210, and control logic circuit by error correction circuit 1220 1210 control flash memories 1100 are according to control gate voltage V_LSB- 3D carries out one to memory cell factory and reads running again.Carefully After section is specified in.

According to control gate voltage V_LSBThe stressed running that -3D is carried out to memory cell factory can be considered that sixfold is read Running.Note that, the voltage spaces and general reading of general reading running and the 5th stressed running are operated transports with sixfold reading The voltage spaces of work are identical.Therefore, the rule for updating code word reliability should be similar, and the weight acquired by running is read according to sixfold Data generation is read to omit herein with storing the details of code word.If the 6th renewal read again obtained by running is pointed out in error correction running Code word afterwards is correct or can correct (the in other words soft decoding of error correction indicates the result that can correct), then error correction circuit This result is notified control logic circuit 1210 by 1220, and correct data are supplied into control logic circuit 1210.If mistake Corrigendum running point out the 6th time read again running obtained by renewal after code word be can not correct (in other words error correction it is soft decoding refer to Show a result that can not be corrected), this result is notified control logic circuit 1210 by error correction circuit 1220, and control logic is electric Road 1210 controls flash memory 1100 according to control gate voltage V_LSB+ 4D carries out one to memory cell factory and reads running again. According to control gate voltage V_LSBThe stressed running that+4D is carried out to memory cell factory can be considered that septuple reads running.Or Person, if error correction running points out that the code word after the renewal obtained by the 6th stressed running is can not to correct (to be in other words stored in The data of memory cell can not be obtained correctly), this result is notified control logic circuit by error correction circuit 1220 1210, and control logic circuit 1210 judge to target entity memory paging P_0 read fail, and will read unsuccessfully return to One main frame (host).The number of times for reading running can arbitrary decision, its non-limitation for the present invention.In addition, by compare from It is general to read the binary digit operated with acquired by the 5th stressed running, it can obtain reading again in general reading running and the 5th The bit of the binary digit of Part I changes (bit flopping) sum in running, and can be designated as bit changing number BF5.Similarly, running and the binary digit acquired by sixfold reading running are read by comparing from general, can obtained The general bit for reading the binary digit of Part I in running and sixfold reading running changes sum, and can be designated as position First changing number BF6.Bit changing number BF5 and BF6 can be used to follow the trail of an optimal critical voltage.

Figure 10 is refer to, Figure 10 illustrates the schematic diagram of the corresponding relation of code word and memory cell.For example, when receive according to During one of the acquired hard bits of memory cell of initial control gate voltage VLSB, the hard bit is considered as this by encoder 1223 The sign bit of the least significant bit of memory cell and preset the sign bit there is highest reliability, for example, Code word " 011 " represent it is very strong " 0 ", and code word " 111 " represent it is very strong " 1 ".However, read again in first time in running, Critical voltage is located at V_LSBWith V_LSBMemory cell between+D will be by corresponding to very weak " 0 ", and be encoded to " 000 ". In second is read again and operated, critical voltage is located at V_LSBWith V_LSBMemory cell between-D will be by corresponding to very weak " 1 ", and be encoded to " 100 ".In third time reads running again, critical voltage is located at V_LSB+ D and V_LSBMemory between+2D Unit will be by corresponding to weak " 0 ", and be encoded to " 001 ".In the 4th time is read again and operated, critical voltage is located at V_LSB- D with V_LSBMemory cell between -2D will be by corresponding to weak " 1 ", and be encoded to " 101 ".In the 5th time is read again and operated, face Boundary's voltage is located at V_LSB+ 2D and V_LSBMemory cell between+3D will be by corresponding to strong " 0 ", and be encoded to " 010 ". In 6th stressed running, critical voltage is located at V_LSB- 2D and V_LSBMemory cell between -3D will be by corresponding to weak " 1 ", and be encoded to " 110 ".Note that, the corresponding relation of code word and critical voltage can be determined arbitrarily, as long as sign bits The reliability of (the hard bit) of member can be recognized by different code words.In addition, the code word size of code word is three bits, its Than one memory cell reads running and binary digit (word acquired in first to the 6th this reading running general String) come short.For example, the critical voltage of a memory cell is located at V_LSB+ 2D and V_LSBBetween+3D.Typically reading This binary digit for reading the least significant bit of the acquired memory cell in running is with first to the 6th for running " 0000000 " (binary digit combines BS8).The binary digit includes seven bits, and it is long compared with the code word size of code word. If error correction decoding device 1222, which needs to store all seven bits, could perform error correction running, rather than only need to storage three Individual bit, error correction decoding device needs more storage space.Therefore, acquired two will be read in running enter different Bit word, which is encoded to shorter code word, can reduce storage space, and cost can also be reduced.

In another embodiment, if error correction running indicates that the renewal code word obtained in reading again and operate at the 6th time can not Corrigendum (data in other words, being stored in memory cell can not be obtained correctly) decoding unit 1228 start it is general like than (LLR, log-likelihood ratio) training program is advised with adjusting to perform the general of the soft decoding of error correction like than correspondence Then (LLR mapping rule).Please compares figure 11, block diagrams of the Figure 11 to illustrate decoding unit 1228.Decoding unit 1228 Comprising without exception like than training unit 12280, without exception like than the decoding circuit 12284 of corresponding unit 12282 and one.Note that, Technical characteristic only related to the present invention is just shown in Figure 11.That is, decoding unit 1228 can be used to comprising other elements Carry out other functions.Because the 6th stressed running can not obtain correct data, therefore be corresponded into generally seemingly for code word after updating The general of ratio will should seemingly adjust than the rule of correspondence.Details is described in detail in rear.

After the renewal of target entity storage paging (such as physical memory paging P_0) being obtained in reading again and operate at the 6th time Code word.It is general like than corresponding unit 12282 according to it is predetermined it is general like than the rule of correspondence by after the renewal of target entity memory paging Code word corresponds into one group first generally like than respective value.For example, it is corresponding for expressing each code word of each memory cell It is specific general like than respective value to one.First group is generally seemingly supplied to decoding circuit 12284 than respective value.Decoding circuit 12284 according to It is general like than respective value one error correction running of progress according to this first group.If general like the mistake carried out than respective value according to this this first group Corrigendum running indicates a result that can not be corrected by mistake, general to collect one of flash memory 1100 like than training unit 12280 The statistics of the correct data of the code word for the error correction unit that can be corrected and the code word for the error correction unit that can be corrected Feature.For example, the target entity memory paging includes 8 sections, and individual section is an error correction unit.At this In 8 sections, the first section S0 is to correct, and other sections are to correct.It is general seemingly to be deposited than training unit 12280 from target The second section S1 code word is obtained in the code word of reservoir paging.Second section S1 is adjacent to the first section S1 and comprising x storage Device unit.In this x memory cell, there is n0 memory cell to be encoded to code word " 000 ", have n1 memory cell volume Code be code word " 001 " ... and there is n7 memory cell to be encoded to code word " 111 ".Mistake is being carried out more to the second section S1 After positive running, the second section S1 correct data can be correctly obtained.It is encoded as those " 000 " memory list Member, has A0 memory cell to be correctly decoded for 1, and have A0 memory cell to be correctly decoded as 0.Therefore, code The general of word " 000 " seemingly should be configured as log (A0/B0) than respective value.Code word " 001 ", code word " 010 " ... and code word " 111 " it is general like also being similarly obtained than respective value.Code word and from the second section S1 code word with the second section S1 just Exact figures like than the corresponding relation between respective value according to can generally be considered as after an adjustment obtained by the statistical nature collected Generally like than the rule of correspondence.One generally can be built up generally like than corresponding table like than the rule of correspondence after adjustment.Because the second section S1 can Corrigendum, thus from after the adjustment acquired by the second section S1 it is general like than the rule of correspondence may show one it is more general like than correspondence than predetermined Rule will also be appropriate it is general like than the rule of correspondence.

It is general general like than corresponding unit 12282 like being provided to than the rule of correspondence after adjustment.Consequently, it is possible to general like than correspondence Unit 12282 is according to general like the target entity memory paging that will be obtained than the rule of correspondence from the 6th stressed running after adjustment Code word correspond into second group it is general like than respective value.Second group is generally seemingly supplied to decoding circuit 12284 than respective value.Decoding circuit 12284 is general like than respective value progress error correction running (such as the soft decoding running of error correction) according to second group.If mistake is more Positive running indicates a result that can be corrected, general like can be used to enter next physical memory paging than respective value after adjustment Row decoding.For example, another entity of the control flash memory 1100 of control logic circuit 1210 to flash memory 1100 Memory paging (such as physical memory paging P_1) is read out running, and obtains the code word of another physical memory paging. Generally one of code word group generally is obtained generally like than respective value like than the rule of correspondence according to after the adjustment like than corresponding unit 12282. 12284 pairs of groups of decoding circuit are general to carry out error correction running like than respective value.

Note that, generally can seemingly be obtained than the rule of correspondence with different modes after adjustment.For example, after adjustment it is general like than The rule of correspondence can be by the code word and the positive exact figures of other sections of other sections (such as section S2, S3 ... and S7) According to statistical nature and obtain.In addition, after adjustment generally seemingly physical memory paging can be corrected by other than the rule of correspondence The code word of (such as physical memory paging P_N) and this can correct physical memory paging correct data statistical nature and .This, which can correct physical memory paging, can physically be adjacent to target entity storage paging.And find out after adjustment It is general similar like more foregoing than the details drizzle of rule of correspondence embodiment.Therefore, those explanations are omitted for the sake of clarity.

Figure 12 is refer to, it is the flow chart for the program that explanation reads the data for being stored in flash memory.In step 200 In, control logic circuit 1210 controls flash memory 1100 according to initial threshold voltage V_LSBTo a target entity memory point The memory cell of page carries out general read and operated, to obtain the first binary digit of a paging to represent each respectively The least significant bit of memory cell.In step 202., first binary bit of the error correction decoding device 1222 according to the paging Numeral carries out error correction hard decoder.If error correction hard decoder indicates a result that can be corrected, into step 214, read Take next physical memory paging.In step 204, if error correction hard decoder indicates a result that cannot be corrected, Control logic circuit 1210 controls flash memory 1100 according to initial threshold voltage V_LSB+ D and V_LSB- D is deposited to target entity The memory cell of reservoir paging carries out first and second and reads running again, is used to the second binary digit for obtaining two pagings The least significant bit of each memory cell is represented respectively.Error correction decoding device 1222 according to from the first binary digit with Code word obtained by second binary digit coding carries out the soft decoding of error correction.If the soft decoding of error correction, which indicates one, to correct Result, then into step 212, carry out critical voltage tracing program.Details is described in detail in rear.Step 206, if the soft solution of error correction Code indicates a result that can not be corrected, and control logic circuit 1210 controls flash memory 1100 according to initial threshold voltage V_LSB+ 2D and V_LSB- 2D carries out the 3rd and the 4th to the memory cell of target entity memory paging and reads running again, to obtain Least significant bit of 3rd binary digit of two pagings to represent each memory cell respectively.Error correction decoding Device 1222 is wrong according to being carried out from code word obtained by the first binary digit, the second binary digit and the 3rd binary digit coding Soft decoding is corrected by mistake.If the soft decoding of error correction indicates a result that can be corrected, into step 212, critical voltage is carried out Tracing program.In step 208, if the soft decoding of error correction indicates a result that can not be corrected, control logic circuit 1210 is controlled Flash memory 1100 processed is according to initial threshold voltage V_LSB+ 3D and V_LSBMemories of-the 3D to target entity memory paging Unit carries out the 5th and sixfold reading running, to obtain the 4th binary digit of two pagings to represent each storage respectively The least significant bit of device unit.Error correction decoding device 1222 is according to from the first binary digit, the second binary digit, Code word obtained by three binary digits and the 4th binary digit coding carries out the soft decoding of error correction.If the soft decoding of error correction A result that can be corrected is indicated, then into step 212, carries out critical voltage tracing program.If soft in step 210 error correction Decoding indicates a result that can not be corrected, general like than training into general like than training stage (LLR training stage) The details in stage has been specified in Figure 11 and related description.Therefore details is omitted in the hope of succinct in this.

Figure 13 is refer to, it illustrates the schematic diagram of the critical voltage distribution of target entity memory paging.Mark entity storage The critical voltage distribution of device paging derives from different stressed runnings.For example, critical voltage is located at V_LSBWith V_LSBStorage between+D The quantity of device unit is X1.And quantity X1 is equal to bit changing number BF1.As it was previously stated, bit changing number BF1 is read from relatively more general Running is taken to read the binary digit obtained by running again with first and obtain.Similarly, critical voltage is located at V_LSBWith V_LSBBetween-D The quantity of memory cell is X2.And quantity X2 is equal to bit changing number BF2.Critical voltage is located at V_LSB+ D and V_LSBBetween+2D The quantity of memory cell be X3.And quantity X3 subtracts bit changing number BF1 equal to bit changing number BF3.Similarly, it is critical Voltage is located at V_LSB- D and V_LSBThe quantity of memory cell between -2D is X4.And quantity X4 is equal to bit changing number BF4 and subtracted Remove bit changing number BF2.In addition, critical voltage is located at V_LSB+ 2D and V_LSBThe quantity of memory cell between+3D is X5.And Quantity X5 subtracts bit changing number BF3 and bit changing number BF1 equal to bit changing number BF5.Similarly, critical voltage is located at V_LSB- 2D and V_LSBThe quantity of memory cell between -3D is X6.And quantity X6 subtracts bit equal to bit changing number BF6 and become Dynamic number BF2 and bit changing number BF4.Critical voltage tracing unit 1230 finds out quantity X1~X6, and sentences according to quantity X1~X6 A disconnected critical voltage moving direction SD.Because quantity X1 is more than quantity X2, one preferably critical voltage may migration one compared with Low voltage rather than V_LSB.In addition, the preferably critical voltage may fall within V_LSB- D, because small relative with X4 of quantity X2.Please It is noted that in preferably critical voltage (such as V_LSB- D) find after, the preferable voltage can be used to do for control logic circuit 1210 For the initial threshold voltage (control gate voltage) for the next physical memory paging for reading flash memory circuit 1100.

The foregoing is only presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with Modification, should all belong to the covering scope of the present invention.

Claims

1. a kind of method to read the data for being stored in a flash memory, this method is included：

Control a first memory paging of the flash memory to the flash memory to perform one and read running；

Obtain one first code word of the first memory paging；

According to one first it is general like than the rule of correspondence obtain one first group of first code word it is general like than respective value；

It is general like than respective value one error correction running of progress according to this first group；

If generally the result that error correction running instruction one can not be corrected is carried out like than respective value according to this first group, according to one Second it is general like than the rule of correspondence obtain one second group of first code word it is general like than respective value；And

Generally seemingly the error correction running is carried out according to this second group than respective value；

Wherein, this second it is general like than the rule of correspondence by collecting one of the flash memory error correction unit that can be corrected Code word and its statistical nature of correct data of code word of the error correction unit that can be corrected obtain, and should by collecting Acquired by one statistical nature of the correct data of the part of a part for the first code word and first code word.

2. the method according to claim 1 to read the data for being stored in a flash memory, it is characterised in that according to One first section of the first memory paging is pointed out according to this first group general error correction running seemingly carried out than respective value not It can correct, and one second section for being adjacent to first section can be corrected, this is second general like should by collecting than the rule of correspondence Acquired by one statistical nature of one second code word of the second section and the correct data of second section.

3. the method according to claim 1 to read the data for being stored in a flash memory, it is characterised in that according to One first section of the first memory paging is pointed out according to this first group general error correction running seemingly carried out than respective value not Can correct, and other sections of the first memory paging can be corrected, this second it is general like than the rule of correspondence by collect one its Acquired by one statistical nature of one second code word of his section and the correct data of other sections.

4. the method according to claim 1 to read the data for being stored in a flash memory, it is characterised in that should Second is general like than one second code word of the rule of correspondence by a second memory paging of the neighbouring first memory paging of collection With acquired by a statistical nature of the correct data of the second memory paging.

5. the method according to claim 1 to read the data for being stored in a flash memory, it is characterised in that should Second is generally seemingly obtained than the rule of correspondence by following steps：

One second code word is obtained from the flash memory；

The error correction running is carried out to second code word；

Obtain the correct data of second code word；And

It is second general like than the rule of correspondence to obtain this to collect a statistical nature of the correct data and second code word.

6. the method according to claim 1 to read the data for being stored in a flash memory, it is characterised in that should Method is further included：

The flash memory is controlled to perform reading running to one the 3rd memory paging of the flash memory；

Obtain a third yard word of the 3rd memory paging；

According to this second it is general like than the rule of correspondence obtain one the 3rd group of the third yard word it is general like than respective value；And

It is general to the 3rd group seemingly to carry out the error correction running than respective value.